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sereg.h revision 1.2 
      1 /*	$NetBSD: sereg.h,v 1.2 1997/10/25 18:04:20 gwr Exp $	*/
      2 
      3 /*-
      4  * Copyright (c) 1997 The NetBSD Foundation, Inc.
      5  * All rights reserved.
      6  *
      7  * This code is derived from software contributed to The NetBSD Foundation
      8  * by Gordon W. Ross.
      9  *
     10  * Redistribution and use in source and binary forms, with or without
     11  * modification, are permitted provided that the following conditions
     12  * are met:
     13  * 1. Redistributions of source code must retain the above copyright
     14  *    notice, this list of conditions and the following disclaimer.
     15  * 2. Redistributions in binary form must reproduce the above copyright
     16  *    notice, this list of conditions and the following disclaimer in the
     17  *    documentation and/or other materials provided with the distribution.
     18  * 3. All advertising materials mentioning features or use of this software
     19  *    must display the following acknowledgement:
     20  *        This product includes software developed by the NetBSD
     21  *        Foundation, Inc. and its contributors.
     22  * 4. Neither the name of The NetBSD Foundation nor the names of its
     23  *    contributors may be used to endorse or promote products derived
     24  *    from this software without specific prior written permission.
     25  *
     26  * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
     27  * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
     28  * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
     29  * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
     30  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
     31  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
     32  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
     33  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
     34  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
     35  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
     36  * POSSIBILITY OF SUCH DAMAGE.
     37  */
     38 
     39 /*
     40  * Sun3/E SCSI/Ethernet board.  This is a VME board with some memory,
     41  * an Intel Ether, and an NCR5380 SCSI with a cheap DMA engine.
     42  * The Sun3/E H/W manual says the ivec2 register is at offset 1E,
     43  * but the SunOS sereg.h file has it at offset 1F (more likely).
     44  * Perhaps the H/W really implements a short at 1E or something.
     45  */
     46 
     47 /*****************************************************************
     48  * Register definitions for the SCSI portion.
     49  * (size=0x20)
     50  */
     51 struct se_regs {
     52 	u_char			ncrregs[8];
     53 	u_short			unused1;
     54 	u_short			dma_addr;	/* DMA offset register	*/
     55 	u_short			unused2;
     56 	u_short			dma_cntr;	/* DMA count down register */
     57 	u_short			unused3[5];
     58 	u_short			se_csr;		/* control/status register */
     59 	u_char			unused9[3];
     60 	u_char			se_ivec;	/* interrupt vector	*/
     61 };
     62 
     63 /*
     64  * SCSI Control and Status Register.
     65  * Note:
     66  *	(ro) 	indicates bit is read only.
     67  *	(rw)	indicates bit is read or write.
     68  */
     69 #define SE_CSR_SBC_IP		0x0200	/* (ro) sbc interrupt pending */
     70 #define SE_CSR_SEND 		0x0008	/* (rw) dma dir, 1=to device */
     71 #define SE_CSR_INTR_EN		0x0004	/* (rw) interrupts enable */
     72 #define	SE_CSR_VCC  		0x0002	/* (ro) power signal to the chip */
     73 #define SE_CSR_SCSI_RES		0x0001	/* (rw) reset sbc and udc, 0=reset */
     74 
     75 
     76 /*****************************************************************
     77  * Register definitions for the SCSI portion.
     78  * (size=0x100)
     79  */
     80 struct ie_regs {
     81 	u_short			ie_pad0;
     82 	u_short			ie_csr;
     83 	u_short			ie_pad1[6];
     84 	u_char			ie_pad2[3];
     85 	u_char			ie_ivec; /* interrupt vector */
     86 	u_short			ie_pad3[128-10];
     87 };
     88 
     89 /*
     90  * Ether Control and Status Register.
     91  */
     92 #define IE_CSR_RESET		0x8000	/* board reset */
     93 #define IE_CSR_NOLOOP		0x4000	/* loopback disable */
     94 #define IE_CSR_ATTEN		0x2000	/* channel attention */
     95 #define IE_CSR_IENAB		0x1000	/* interrupt enable */
     96 #define IE_CSR_IPEND		0x0100	/* interrupt pending */
     97 
     98 
     99 /*****************************************************************
    100  * Register definitions for the entire SCSI/Ethernet board.
    101  * I had the impression that there were overlaps in this map,
    102  * which was the reason for existence of the "sebuf" driver.
    103  * Now it looks like the "sebuf" driver was unnecessary. XXX
    104  */
    105 
    106 #define SE_NCRBUFSIZE	0x10000
    107 #define SE_IEBUFSIZE	0x20000
    108 struct sebuf_regs {
    109 	char	se_scsi_buf[SE_NCRBUFSIZE];
    110 	struct se_regs se_scsi_regs;
    111 	char	se_pad[0x10000 - 0x120];
    112 	struct ie_regs se_eth_regs;
    113 	char	se_eth_buf[SE_IEBUFSIZE];
    114 };	/* 128KB total */
    115