si.c revision 1.7.2.2 1 1.7.2.2 gwr /*
2 1.7.2.2 gwr * Copyright (C) 1994 Adam Glass, Gordon W. Ross
3 1.7.2.2 gwr * Copyright (C) 1993 Allen K. Briggs, Chris P. Caputo,
4 1.7.2.2 gwr * Michael L. Finch, Bradley A. Grantham, and
5 1.7.2.2 gwr * Lawrence A. Kesteloot
6 1.7.2.2 gwr * All rights reserved.
7 1.7.2.2 gwr *
8 1.7.2.2 gwr * Redistribution and use in source and binary forms, with or without
9 1.7.2.2 gwr * modification, are permitted provided that the following conditions
10 1.7.2.2 gwr * are met:
11 1.7.2.2 gwr * 1. Redistributions of source code must retain the above copyright
12 1.7.2.2 gwr * notice, this list of conditions and the following disclaimer.
13 1.7.2.2 gwr * 2. Redistributions in binary form must reproduce the above copyright
14 1.7.2.2 gwr * notice, this list of conditions and the following disclaimer in the
15 1.7.2.2 gwr * documentation and/or other materials provided with the distribution.
16 1.7.2.2 gwr * 3. All advertising materials mentioning features or use of this software
17 1.7.2.2 gwr * must display the following acknowledgement:
18 1.7.2.2 gwr * This product includes software developed by the Alice Group.
19 1.7.2.2 gwr * 4. The names of the Alice Group or any of its members may not be used
20 1.7.2.2 gwr * to endorse or promote products derived from this software without
21 1.7.2.2 gwr * specific prior written permission.
22 1.7.2.2 gwr *
23 1.7.2.2 gwr * THIS SOFTWARE IS PROVIDED BY THE ALICE GROUP ``AS IS'' AND ANY EXPRESS OR
24 1.7.2.2 gwr * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
25 1.7.2.2 gwr * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
26 1.7.2.2 gwr * IN NO EVENT SHALL THE ALICE GROUP BE LIABLE FOR ANY DIRECT, INDIRECT,
27 1.7.2.2 gwr * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
28 1.7.2.2 gwr * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
29 1.7.2.2 gwr * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
30 1.7.2.2 gwr * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
31 1.7.2.2 gwr * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
32 1.7.2.2 gwr * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 1.7.2.2 gwr *
34 1.7.2.2 gwr * $Id: si.c,v 1.7.2.2 1994/09/20 16:21:47 gwr Exp $
35 1.7.2.2 gwr */
36 1.7.2.2 gwr
37 1.7.2.2 gwr /* #define DEBUG 1 */
38 1.7.2.2 gwr
39 1.7.2.2 gwr /* XXX - Need to add support for real DMA. -gwr */
40 1.7.2.2 gwr /* #define PSEUDO_DMA 1 (broken) */
41 1.7.2.2 gwr
42 1.7.2.2 gwr static int si_debug=0;
43 1.7.2.2 gwr
44 1.7.2.2 gwr #include <sys/types.h>
45 1.7.2.2 gwr #include <sys/malloc.h>
46 1.7.2.2 gwr #include <sys/param.h>
47 1.7.2.2 gwr #include <sys/systm.h>
48 1.7.2.2 gwr #include <sys/errno.h>
49 1.7.2.2 gwr #include <sys/buf.h>
50 1.7.2.2 gwr #include <sys/proc.h>
51 1.7.2.2 gwr #include <sys/user.h>
52 1.7.2.2 gwr #include <sys/device.h>
53 1.7.2.2 gwr
54 1.7.2.2 gwr #include <machine/autoconf.h>
55 1.7.2.2 gwr #include <machine/isr.h>
56 1.7.2.2 gwr #include <machine/obio.h>
57 1.7.2.2 gwr
58 1.7.2.2 gwr #include <scsi/scsi_all.h>
59 1.7.2.2 gwr #include <scsi/scsi_debug.h>
60 1.7.2.2 gwr #include <scsi/scsiconf.h>
61 1.7.2.2 gwr
62 1.7.2.2 gwr #include "scsi_defs.h"
63 1.7.2.2 gwr #include "scsi_5380.h"
64 1.7.2.2 gwr
65 1.7.2.2 gwr #define SCI_PHASE_DISC 0 /* sort of ... */
66 1.7.2.2 gwr #define SCI_CLR_INTR(regs) {register int temp = regs->sci_iack;}
67 1.7.2.2 gwr #define SCI_ACK(ptr,phase) (ptr)->sci_tcmd = (phase)
68 1.7.2.2 gwr #define SCSI_TIMEOUT_VAL 10000000
69 1.7.2.2 gwr #define WAIT_FOR_NOT_REQ(ptr) { \
70 1.7.2.2 gwr int scsi_timeout = SCSI_TIMEOUT_VAL; \
71 1.7.2.2 gwr while ( ((ptr)->sci_bus_csr & SCI_BUS_REQ) && \
72 1.7.2.2 gwr ((ptr)->sci_bus_csr & SCI_BUS_REQ) && \
73 1.7.2.2 gwr ((ptr)->sci_bus_csr & SCI_BUS_REQ) && \
74 1.7.2.2 gwr (--scsi_timeout) ); \
75 1.7.2.2 gwr if (!scsi_timeout) { \
76 1.7.2.2 gwr printf("scsi timeout--WAIT_FOR_NOT_REQ---%s, line %d.\n", \
77 1.7.2.2 gwr __FILE__, __LINE__); \
78 1.7.2.2 gwr goto scsi_timeout_error; \
79 1.7.2.2 gwr } \
80 1.7.2.2 gwr }
81 1.7.2.2 gwr #define WAIT_FOR_REQ(ptr) { \
82 1.7.2.2 gwr int scsi_timeout = SCSI_TIMEOUT_VAL; \
83 1.7.2.2 gwr while ( (((ptr)->sci_bus_csr & SCI_BUS_REQ) == 0) && \
84 1.7.2.2 gwr (((ptr)->sci_bus_csr & SCI_BUS_REQ) == 0) && \
85 1.7.2.2 gwr (((ptr)->sci_bus_csr & SCI_BUS_REQ) == 0) && \
86 1.7.2.2 gwr (--scsi_timeout) ); \
87 1.7.2.2 gwr if (!scsi_timeout) { \
88 1.7.2.2 gwr printf("scsi timeout--WAIT_FOR_REQ---%s, line %d.\n", \
89 1.7.2.2 gwr __FILE__, __LINE__); \
90 1.7.2.2 gwr goto scsi_timeout_error; \
91 1.7.2.2 gwr } \
92 1.7.2.2 gwr }
93 1.7.2.2 gwr #define WAIT_FOR_BSY(ptr) { \
94 1.7.2.2 gwr int scsi_timeout = SCSI_TIMEOUT_VAL; \
95 1.7.2.2 gwr while ( (((ptr)->sci_bus_csr & SCI_BUS_BSY) == 0) && \
96 1.7.2.2 gwr (((ptr)->sci_bus_csr & SCI_BUS_BSY) == 0) && \
97 1.7.2.2 gwr (((ptr)->sci_bus_csr & SCI_BUS_BSY) == 0) && \
98 1.7.2.2 gwr (--scsi_timeout) ); \
99 1.7.2.2 gwr if (!scsi_timeout) { \
100 1.7.2.2 gwr printf("scsi timeout--WAIT_FOR_BSY---%s, line %d.\n", \
101 1.7.2.2 gwr __FILE__, __LINE__); \
102 1.7.2.2 gwr goto scsi_timeout_error; \
103 1.7.2.2 gwr } \
104 1.7.2.2 gwr }
105 1.7.2.2 gwr
106 1.7.2.2 gwr #ifdef DDB
107 1.7.2.2 gwr int Debugger();
108 1.7.2.2 gwr #else
109 1.7.2.2 gwr #define Debugger() panic("Should call Debugger here %s:%d", \
110 1.7.2.2 gwr __FILE__, __LINE__)
111 1.7.2.2 gwr #endif
112 1.7.2.2 gwr
113 1.7.2.2 gwr struct ncr5380_softc {
114 1.7.2.2 gwr struct device sc_dev;
115 1.7.2.2 gwr void *sc_regs;
116 1.7.2.2 gwr int sc_adapter_target;
117 1.7.2.2 gwr struct scsi_link sc_link;
118 1.7.2.2 gwr };
119 1.7.2.2 gwr
120 1.7.2.2 gwr static u_int ncr5380_adapter_info(struct ncr5380_softc *ncr5380);
121 1.7.2.2 gwr static void ncr5380_minphys(struct buf *bp);
122 1.7.2.2 gwr static int ncr5380_scsi_cmd(struct scsi_xfer *xs);
123 1.7.2.2 gwr
124 1.7.2.2 gwr static int ncr5380_show_scsi_cmd(struct scsi_xfer *xs);
125 1.7.2.2 gwr static int ncr5380_reset_target(int adapter, int target);
126 1.7.2.2 gwr static int ncr5380_poll(int adapter, int timeout);
127 1.7.2.2 gwr static int ncr5380_send_cmd(struct scsi_xfer *xs);
128 1.7.2.2 gwr
129 1.7.2.2 gwr void ncr5380_intr(int adapter);
130 1.7.2.2 gwr
131 1.7.2.2 gwr static int si_generic(int adapter, int id, int lun,
132 1.7.2.2 gwr struct scsi_generic *cmd, int cmdlen,
133 1.7.2.2 gwr void *databuf, int datalen);
134 1.7.2.2 gwr static int si_group0(int adapter, int id, int lun,
135 1.7.2.2 gwr int opcode, int addr, int len,
136 1.7.2.2 gwr int flags, caddr_t databuf, int datalen);
137 1.7.2.2 gwr
138 1.7.2.2 gwr static char scsi_name[] = "si";
139 1.7.2.2 gwr
140 1.7.2.2 gwr struct scsi_adapter ncr5380_switch = {
141 1.7.2.2 gwr ncr5380_scsi_cmd, /* scsi_cmd() */
142 1.7.2.2 gwr ncr5380_minphys, /* scsi_minphys() */
143 1.7.2.2 gwr 0, /* open_target_lu() */
144 1.7.2.2 gwr 0, /* close_target_lu() */
145 1.7.2.2 gwr ncr5380_adapter_info, /* adapter_info() */
146 1.7.2.2 gwr scsi_name, /* name */
147 1.7.2.2 gwr 0, 0 /* spare[2] */
148 1.7.2.2 gwr };
149 1.7.2.2 gwr
150 1.7.2.2 gwr /* This is copied from julian's bt driver */
151 1.7.2.2 gwr /* "so we have a default dev struct for our link struct." */
152 1.7.2.2 gwr struct scsi_device ncr_dev = {
153 1.7.2.2 gwr NULL, /* Use default error handler. */
154 1.7.2.2 gwr NULL, /* Use default start handler. */
155 1.7.2.2 gwr NULL, /* Use default async handler. */
156 1.7.2.2 gwr NULL, /* Use default "done" routine. */
157 1.7.2.2 gwr "si", /* name of device type */
158 1.7.2.2 gwr 0, /* device type dependent flags */
159 1.7.2.2 gwr 0, 0 /* spare[2] */
160 1.7.2.2 gwr };
161 1.7.2.2 gwr
162 1.7.2.2 gwr extern int matchbyname();
163 1.7.2.2 gwr static int si_match();
164 1.7.2.2 gwr static void si_attach();
165 1.7.2.2 gwr
166 1.7.2.2 gwr struct cfdriver sicd = {
167 1.7.2.2 gwr NULL, "si", si_match, si_attach, DV_DULL,
168 1.7.2.2 gwr sizeof(struct ncr5380_softc), NULL, 0,
169 1.7.2.2 gwr };
170 1.7.2.2 gwr
171 1.7.2.2 gwr static int
172 1.7.2.2 gwr si_print(aux, name)
173 1.7.2.2 gwr void *aux;
174 1.7.2.2 gwr char *name;
175 1.7.2.2 gwr {
176 1.7.2.2 gwr if (name)
177 1.7.2.2 gwr printf("%s: (sc_link = 0x%x)", name, (int) aux);
178 1.7.2.2 gwr return UNCONF;
179 1.7.2.2 gwr }
180 1.7.2.2 gwr
181 1.7.2.2 gwr static int
182 1.7.2.2 gwr si_match(parent, cf, aux)
183 1.7.2.2 gwr struct device *parent;
184 1.7.2.2 gwr struct cfdata *cf;
185 1.7.2.2 gwr void *aux;
186 1.7.2.2 gwr {
187 1.7.2.2 gwr caddr_t si_addr;
188 1.7.2.2 gwr struct obio_cf_loc *obio_loc = (struct obio_cf_loc *) CFDATA_LOC(cf);
189 1.7.2.2 gwr
190 1.7.2.2 gwr si_addr = OBIO_DEFAULT_PARAM(caddr_t, obio_loc->obio_addr, OBIO_NCR_SCSI);
191 1.7.2.2 gwr return !obio_probe_byte(si_addr);
192 1.7.2.2 gwr }
193 1.7.2.2 gwr
194 1.7.2.2 gwr static void
195 1.7.2.2 gwr si_attach(parent, self, aux)
196 1.7.2.2 gwr struct device *parent, *self;
197 1.7.2.2 gwr void *aux;
198 1.7.2.2 gwr {
199 1.7.2.2 gwr caddr_t dvma_malloc();
200 1.7.2.2 gwr int si_addr, level;
201 1.7.2.2 gwr int unit = DEVICE_UNIT(self);
202 1.7.2.2 gwr struct ncr5380_softc *ncr5380 = (struct ncr5380_softc *) self;
203 1.7.2.2 gwr struct obio_cf_loc *obio_loc = OBIO_LOC(self);
204 1.7.2.2 gwr struct cfdata *new_match;
205 1.7.2.2 gwr
206 1.7.2.2 gwr si_addr = OBIO_DEFAULT_PARAM(int, obio_loc->obio_addr, OBIO_NCR_SCSI);
207 1.7.2.2 gwr ncr5380->sc_regs = (sci_regmap_t *)
208 1.7.2.2 gwr obio_alloc(si_addr, OBIO_NCR_SCSI_SIZE);
209 1.7.2.2 gwr
210 1.7.2.2 gwr level = OBIO_DEFAULT_PARAM(int, obio_loc->obio_level, 2);
211 1.7.2.2 gwr
212 1.7.2.2 gwr ncr5380->sc_link.scsibus = unit; /* needed? */
213 1.7.2.2 gwr ncr5380->sc_link.adapter_softc = ncr5380;
214 1.7.2.2 gwr ncr5380->sc_link.adapter_targ = 7;
215 1.7.2.2 gwr ncr5380->sc_link.adapter = &ncr5380_switch;
216 1.7.2.2 gwr ncr5380->sc_link.device = &ncr_dev;
217 1.7.2.2 gwr
218 1.7.2.2 gwr obio_print(si_addr, level);
219 1.7.2.2 gwr printf("\n");
220 1.7.2.2 gwr
221 1.7.2.2 gwr config_found(self, &(ncr5380->sc_link), si_print);
222 1.7.2.2 gwr }
223 1.7.2.2 gwr
224 1.7.2.2 gwr static u_int
225 1.7.2.2 gwr ncr5380_adapter_info(struct ncr5380_softc *ncr5380)
226 1.7.2.2 gwr {
227 1.7.2.2 gwr return 1;
228 1.7.2.2 gwr }
229 1.7.2.2 gwr
230 1.7.2.2 gwr #define MIN_PHYS 65536 /*BARF!!!!*/
231 1.7.2.2 gwr static void
232 1.7.2.2 gwr ncr5380_minphys(struct buf *bp)
233 1.7.2.2 gwr {
234 1.7.2.2 gwr if (bp->b_bcount > MIN_PHYS) {
235 1.7.2.2 gwr printf("Uh-oh... ncr5380_minphys setting bp->b_bcount = %x.\n", MIN_PHYS);
236 1.7.2.2 gwr bp->b_bcount = MIN_PHYS;
237 1.7.2.2 gwr }
238 1.7.2.2 gwr }
239 1.7.2.2 gwr #undef MIN_PHYS
240 1.7.2.2 gwr
241 1.7.2.2 gwr static int
242 1.7.2.2 gwr ncr5380_scsi_cmd(struct scsi_xfer *xs)
243 1.7.2.2 gwr {
244 1.7.2.2 gwr int flags, s, r;
245 1.7.2.2 gwr
246 1.7.2.2 gwr flags = xs->flags;
247 1.7.2.2 gwr if (xs->bp) flags |= (SCSI_NOSLEEP);
248 1.7.2.2 gwr if ( flags & ITSDONE ) {
249 1.7.2.2 gwr printf("Already done?");
250 1.7.2.2 gwr xs->flags &= ~ITSDONE;
251 1.7.2.2 gwr }
252 1.7.2.2 gwr if ( ! ( flags & INUSE ) ) {
253 1.7.2.2 gwr printf("Not in use?");
254 1.7.2.2 gwr xs->flags |= INUSE;
255 1.7.2.2 gwr }
256 1.7.2.2 gwr
257 1.7.2.2 gwr if ( flags & SCSI_RESET ) {
258 1.7.2.2 gwr printf("flags & SCSIRESET.\n");
259 1.7.2.2 gwr if ( ! ( flags & SCSI_NOSLEEP ) ) {
260 1.7.2.2 gwr s = splbio();
261 1.7.2.2 gwr ncr5380_reset_target(xs->sc_link->scsibus, xs->sc_link->target);
262 1.7.2.2 gwr splx(s);
263 1.7.2.2 gwr return(SUCCESSFULLY_QUEUED);
264 1.7.2.2 gwr } else {
265 1.7.2.2 gwr ncr5380_reset_target(xs->sc_link->scsibus, xs->sc_link->target);
266 1.7.2.2 gwr if (ncr5380_poll(xs->sc_link->scsibus, xs->timeout)) {
267 1.7.2.2 gwr return (HAD_ERROR);
268 1.7.2.2 gwr }
269 1.7.2.2 gwr return (COMPLETE);
270 1.7.2.2 gwr }
271 1.7.2.2 gwr }
272 1.7.2.2 gwr #if 0
273 1.7.2.2 gwr /*
274 1.7.2.2 gwr * OK. Now that that's over with, let's pack up that
275 1.7.2.2 gwr * SCSI puppy and send it off. If we can, we'll just
276 1.7.2.2 gwr * queue and go; otherwise, we'll wait for the command
277 1.7.2.2 gwr * to finish.
278 1.7.2.2 gwr */
279 1.7.2.2 gwr if ( ! ( flags & SCSI_NOSLEEP ) ) {
280 1.7.2.2 gwr s = splbio();
281 1.7.2.2 gwr ncr5380_send_cmd(xs);
282 1.7.2.2 gwr splx(s);
283 1.7.2.2 gwr return(SUCCESSFULLY_QUEUED);
284 1.7.2.2 gwr }
285 1.7.2.2 gwr #endif
286 1.7.2.2 gwr
287 1.7.2.2 gwr r = ncr5380_send_cmd(xs);
288 1.7.2.2 gwr xs->flags |= ITSDONE;
289 1.7.2.2 gwr scsi_done(xs);
290 1.7.2.2 gwr switch(r) {
291 1.7.2.2 gwr case COMPLETE:
292 1.7.2.2 gwr case SUCCESSFULLY_QUEUED:
293 1.7.2.2 gwr r = SUCCESSFULLY_QUEUED;
294 1.7.2.2 gwr if (xs->flags&SCSI_NOMASK)
295 1.7.2.2 gwr r = COMPLETE;
296 1.7.2.2 gwr break;
297 1.7.2.2 gwr default:
298 1.7.2.2 gwr break;
299 1.7.2.2 gwr }
300 1.7.2.2 gwr return r;
301 1.7.2.2 gwr #if 0
302 1.7.2.2 gwr do {
303 1.7.2.2 gwr if (ncr5380_poll(xs->sc_link->scsibus, xs->timeout)) {
304 1.7.2.2 gwr if ( ! ( xs->flags & SCSI_SILENT ) )
305 1.7.2.2 gwr printf("cmd fail.\n");
306 1.7.2.2 gwr cmd_cleanup
307 1.7.2.2 gwr xs->error = XS_DRIVER_STUFFUP;
308 1.7.2.2 gwr splx(s);
309 1.7.2.2 gwr }
310 1.7.2.2 gwr } while ( ! ( xs->flags & ITSDONE ) );
311 1.7.2.2 gwr #endif
312 1.7.2.2 gwr }
313 1.7.2.2 gwr
314 1.7.2.2 gwr static int
315 1.7.2.2 gwr ncr5380_show_scsi_cmd(struct scsi_xfer *xs)
316 1.7.2.2 gwr {
317 1.7.2.2 gwr u_char *b = (u_char *) xs->cmd;
318 1.7.2.2 gwr int i = 0;
319 1.7.2.2 gwr
320 1.7.2.2 gwr if ( ! ( xs->flags & SCSI_RESET ) ) {
321 1.7.2.2 gwr printf("si(%d:%d:%d)-",
322 1.7.2.2 gwr xs->sc_link->scsibus,
323 1.7.2.2 gwr xs->sc_link->target,
324 1.7.2.2 gwr xs->sc_link->lun);
325 1.7.2.2 gwr while (i < xs->cmdlen) {
326 1.7.2.2 gwr if (i) printf(",");
327 1.7.2.2 gwr printf("%x",b[i++]);
328 1.7.2.2 gwr }
329 1.7.2.2 gwr printf("-\n");
330 1.7.2.2 gwr } else {
331 1.7.2.2 gwr printf("si(%d:%d:%d)-RESET-\n",
332 1.7.2.2 gwr xs->sc_link->scsibus,
333 1.7.2.2 gwr xs->sc_link->target,
334 1.7.2.2 gwr xs->sc_link->lun);
335 1.7.2.2 gwr }
336 1.7.2.2 gwr }
337 1.7.2.2 gwr
338 1.7.2.2 gwr /*
339 1.7.2.2 gwr * Actual chip control.
340 1.7.2.2 gwr */
341 1.7.2.2 gwr
342 1.7.2.2 gwr void
343 1.7.2.2 gwr ncr5380_intr(int adapter)
344 1.7.2.2 gwr {
345 1.7.2.2 gwr register struct ncr5380_softc *ncr5380 = sicd.cd_devs[adapter];
346 1.7.2.2 gwr register volatile sci_regmap_t *regs = ncr5380->sc_regs;
347 1.7.2.2 gwr
348 1.7.2.2 gwr SCI_CLR_INTR(regs);
349 1.7.2.2 gwr regs->sci_mode = 0x00;
350 1.7.2.2 gwr #ifdef DEBUG
351 1.7.2.2 gwr printf ("ncr_intr\n");
352 1.7.2.2 gwr #endif
353 1.7.2.2 gwr }
354 1.7.2.2 gwr
355 1.7.2.2 gwr int
356 1.7.2.2 gwr scsi_irq_intr(void)
357 1.7.2.2 gwr {
358 1.7.2.2 gwr #if 0 /* XXX - no way to get regs */
359 1.7.2.2 gwr register volatile sci_regmap_t *regs = ncr;
360 1.7.2.2 gwr if (regs->sci_csr != SCI_CSR_PHASE_MATCH)
361 1.7.2.2 gwr printf("scsi_irq_intr called (not just phase match -- "
362 1.7.2.2 gwr "csr = 0x%x, bus_csr = 0x%x).\n",
363 1.7.2.2 gwr regs->sci_csr, regs->sci_bus_csr);
364 1.7.2.2 gwr ncr5380_intr(0);
365 1.7.2.2 gwr #endif
366 1.7.2.2 gwr return 1;
367 1.7.2.2 gwr }
368 1.7.2.2 gwr
369 1.7.2.2 gwr int
370 1.7.2.2 gwr scsi_drq_intr(void)
371 1.7.2.2 gwr {
372 1.7.2.2 gwr #if 0
373 1.7.2.2 gwr printf("scsi_drq_intr called.\n");
374 1.7.2.2 gwr ncr5380_intr(0);
375 1.7.2.2 gwr #endif
376 1.7.2.2 gwr return 1;
377 1.7.2.2 gwr }
378 1.7.2.2 gwr
379 1.7.2.2 gwr static int
380 1.7.2.2 gwr ncr5380_reset_target(int adapter, int target)
381 1.7.2.2 gwr {
382 1.7.2.2 gwr register struct ncr5380_softc *ncr5380 = sicd.cd_devs[adapter];
383 1.7.2.2 gwr register volatile sci_regmap_t *regs = ncr5380->sc_regs;
384 1.7.2.2 gwr int dummy;
385 1.7.2.2 gwr
386 1.7.2.2 gwr regs->sci_icmd = SCI_ICMD_TEST;
387 1.7.2.2 gwr regs->sci_icmd = SCI_ICMD_TEST | SCI_ICMD_RST;
388 1.7.2.2 gwr delay(2500);
389 1.7.2.2 gwr regs->sci_icmd = 0;
390 1.7.2.2 gwr
391 1.7.2.2 gwr regs->sci_mode = 0;
392 1.7.2.2 gwr regs->sci_tcmd = SCI_PHASE_DISC;
393 1.7.2.2 gwr regs->sci_sel_enb = 0;
394 1.7.2.2 gwr
395 1.7.2.2 gwr SCI_CLR_INTR(regs);
396 1.7.2.2 gwr SCI_CLR_INTR(regs);
397 1.7.2.2 gwr }
398 1.7.2.2 gwr
399 1.7.2.2 gwr static int
400 1.7.2.2 gwr ncr5380_poll(int adapter, int timeout)
401 1.7.2.2 gwr {
402 1.7.2.2 gwr }
403 1.7.2.2 gwr
404 1.7.2.2 gwr static int
405 1.7.2.2 gwr ncr5380_send_cmd(struct scsi_xfer *xs)
406 1.7.2.2 gwr {
407 1.7.2.2 gwr int s;
408 1.7.2.2 gwr int sense;
409 1.7.2.2 gwr
410 1.7.2.2 gwr /* ncr5380_show_scsi_cmd(xs); */
411 1.7.2.2 gwr s = splbio();
412 1.7.2.2 gwr sense = si_generic( xs->sc_link->scsibus, xs->sc_link->target,
413 1.7.2.2 gwr xs->sc_link->lun, xs->cmd, xs->cmdlen,
414 1.7.2.2 gwr xs->data, xs->datalen );
415 1.7.2.2 gwr splx(s);
416 1.7.2.2 gwr if (sense) {
417 1.7.2.2 gwr switch (sense) {
418 1.7.2.2 gwr case 0x02: /* Check condition */
419 1.7.2.2 gwr #ifdef DEBUG
420 1.7.2.2 gwr printf("check cond. target %d.\n",
421 1.7.2.2 gwr xs->sc_link->target);
422 1.7.2.2 gwr #endif
423 1.7.2.2 gwr delay(10); /* Phil's fix for slow devices. */
424 1.7.2.2 gwr s = splbio();
425 1.7.2.2 gwr si_group0(xs->sc_link->scsibus,
426 1.7.2.2 gwr xs->sc_link->target,
427 1.7.2.2 gwr xs->sc_link->lun,
428 1.7.2.2 gwr 0x3, 0x0,
429 1.7.2.2 gwr sizeof(struct scsi_sense_data),
430 1.7.2.2 gwr 0, (caddr_t) &(xs->sense),
431 1.7.2.2 gwr sizeof(struct scsi_sense_data));
432 1.7.2.2 gwr splx(s);
433 1.7.2.2 gwr xs->error = XS_SENSE;
434 1.7.2.2 gwr return HAD_ERROR;
435 1.7.2.2 gwr case 0x08: /* Busy */
436 1.7.2.2 gwr xs->error = XS_BUSY;
437 1.7.2.2 gwr return HAD_ERROR;
438 1.7.2.2 gwr default:
439 1.7.2.2 gwr xs->error = XS_DRIVER_STUFFUP;
440 1.7.2.2 gwr return HAD_ERROR;
441 1.7.2.2 gwr }
442 1.7.2.2 gwr }
443 1.7.2.2 gwr xs->error = XS_NOERROR;
444 1.7.2.2 gwr return (COMPLETE);
445 1.7.2.2 gwr }
446 1.7.2.2 gwr
447 1.7.2.2 gwr static int
448 1.7.2.2 gwr si_select_target(register volatile sci_regmap_t *regs,
449 1.7.2.2 gwr u_char myid, u_char tid, int with_atn)
450 1.7.2.2 gwr {
451 1.7.2.2 gwr register u_char bid, icmd;
452 1.7.2.2 gwr int ret = SCSI_RET_RETRY;
453 1.7.2.2 gwr
454 1.7.2.2 gwr if ((regs->sci_bus_csr & (SCI_BUS_BSY|SCI_BUS_SEL)) &&
455 1.7.2.2 gwr (regs->sci_bus_csr & (SCI_BUS_BSY|SCI_BUS_SEL)) &&
456 1.7.2.2 gwr (regs->sci_bus_csr & (SCI_BUS_BSY|SCI_BUS_SEL)))
457 1.7.2.2 gwr return ret;
458 1.7.2.2 gwr
459 1.7.2.2 gwr /* for our purposes.. */
460 1.7.2.2 gwr myid = 1 << myid;
461 1.7.2.2 gwr tid = 1 << tid;
462 1.7.2.2 gwr
463 1.7.2.2 gwr regs->sci_sel_enb = 0; /* we don't want any interrupts. */
464 1.7.2.2 gwr regs->sci_tcmd = 0; /* get into a harmless state */
465 1.7.2.2 gwr regs->sci_mode = 0; /* get into a harmless state */
466 1.7.2.2 gwr
467 1.7.2.2 gwr regs->sci_odata = myid;
468 1.7.2.2 gwr regs->sci_mode = SCI_MODE_ARB;
469 1.7.2.2 gwr /* regs->sci_mode |= SCI_MODE_ARB; XXX? */
470 1.7.2.2 gwr /* AIP might not set if BSY went true after we checked */
471 1.7.2.2 gwr for (bid = 0; bid < 20; bid++) /* 20usec circa */
472 1.7.2.2 gwr if (regs->sci_icmd & SCI_ICMD_AIP)
473 1.7.2.2 gwr break;
474 1.7.2.2 gwr if ((regs->sci_icmd & SCI_ICMD_AIP) == 0) {
475 1.7.2.2 gwr goto lost;
476 1.7.2.2 gwr }
477 1.7.2.2 gwr
478 1.7.2.2 gwr delay(2200); /* 2.2 millisecond arbitration delay */
479 1.7.2.2 gwr
480 1.7.2.2 gwr if (regs->sci_icmd & SCI_ICMD_LST) {
481 1.7.2.2 gwr #ifdef DEBUG
482 1.7.2.2 gwr printf ("lost 1\n");
483 1.7.2.2 gwr #endif
484 1.7.2.2 gwr goto lost;
485 1.7.2.2 gwr }
486 1.7.2.2 gwr
487 1.7.2.2 gwr regs->sci_mode &= ~SCI_MODE_PAR_CHK;
488 1.7.2.2 gwr bid = regs->sci_data;
489 1.7.2.2 gwr
490 1.7.2.2 gwr if ((bid & ~myid) > myid) {
491 1.7.2.2 gwr #ifdef DEBUG
492 1.7.2.2 gwr printf ("lost 2\n");
493 1.7.2.2 gwr #endif
494 1.7.2.2 gwr goto lost;
495 1.7.2.2 gwr }
496 1.7.2.2 gwr if (regs->sci_icmd & SCI_ICMD_LST) {
497 1.7.2.2 gwr #ifdef DEBUG
498 1.7.2.2 gwr printf ("lost 3\n");
499 1.7.2.2 gwr #endif
500 1.7.2.2 gwr goto lost;
501 1.7.2.2 gwr }
502 1.7.2.2 gwr
503 1.7.2.2 gwr /* Won arbitration, enter selection phase now */
504 1.7.2.2 gwr icmd = regs->sci_icmd & ~(SCI_ICMD_DIFF|SCI_ICMD_TEST);
505 1.7.2.2 gwr icmd |= (with_atn ? (SCI_ICMD_SEL|SCI_ICMD_ATN) : SCI_ICMD_SEL);
506 1.7.2.2 gwr icmd |= SCI_ICMD_BSY;
507 1.7.2.2 gwr regs->sci_icmd = icmd;
508 1.7.2.2 gwr
509 1.7.2.2 gwr if (regs->sci_icmd & SCI_ICMD_LST) {
510 1.7.2.2 gwr #ifdef DEBUG
511 1.7.2.2 gwr printf ("nosel\n");
512 1.7.2.2 gwr #endif
513 1.7.2.2 gwr goto nosel;
514 1.7.2.2 gwr }
515 1.7.2.2 gwr
516 1.7.2.2 gwr /* XXX a target that violates specs might still drive the bus XXX */
517 1.7.2.2 gwr /* XXX should put our id out, and after the delay check nothi XXX */
518 1.7.2.2 gwr /* XXX ng else is out there. XXX */
519 1.7.2.2 gwr
520 1.7.2.2 gwr delay2us();
521 1.7.2.2 gwr
522 1.7.2.2 gwr regs->sci_tcmd = 0;
523 1.7.2.2 gwr regs->sci_odata = myid | tid;
524 1.7.2.2 gwr regs->sci_sel_enb = 0;
525 1.7.2.2 gwr
526 1.7.2.2 gwr /* regs->sci_mode &= ~SCI_MODE_ARB; 2 deskew delays, too */
527 1.7.2.2 gwr regs->sci_mode = 0; /* 2 deskew delays, too */
528 1.7.2.2 gwr
529 1.7.2.2 gwr icmd |= SCI_ICMD_DATA;
530 1.7.2.2 gwr icmd &= ~(SCI_ICMD_BSY);
531 1.7.2.2 gwr
532 1.7.2.2 gwr regs->sci_icmd = icmd;
533 1.7.2.2 gwr
534 1.7.2.2 gwr /* bus settle delay, 400ns */
535 1.7.2.2 gwr delay2us(); /* too much (was 2) ? */
536 1.7.2.2 gwr
537 1.7.2.2 gwr /* regs->sci_mode |= SCI_MODE_PAR_CHK; */
538 1.7.2.2 gwr
539 1.7.2.2 gwr {
540 1.7.2.2 gwr register int timeo = 2500;/* 250 msecs in 100 usecs chunks */
541 1.7.2.2 gwr while ((regs->sci_bus_csr & SCI_BUS_BSY) == 0) {
542 1.7.2.2 gwr if (--timeo > 0) {
543 1.7.2.2 gwr delay(100);
544 1.7.2.2 gwr } else {
545 1.7.2.2 gwr goto nodev;
546 1.7.2.2 gwr }
547 1.7.2.2 gwr }
548 1.7.2.2 gwr }
549 1.7.2.2 gwr
550 1.7.2.2 gwr icmd &= ~(SCI_ICMD_DATA|SCI_ICMD_SEL);
551 1.7.2.2 gwr regs->sci_icmd = icmd;
552 1.7.2.2 gwr /* regs->sci_sel_enb = myid;*/ /* looks like we should NOT have it */
553 1.7.2.2 gwr return SCSI_RET_SUCCESS;
554 1.7.2.2 gwr nodev:
555 1.7.2.2 gwr ret = SCSI_RET_DEVICE_DOWN;
556 1.7.2.2 gwr regs->sci_sel_enb = myid;
557 1.7.2.2 gwr nosel:
558 1.7.2.2 gwr icmd &= ~(SCI_ICMD_DATA|SCI_ICMD_SEL|SCI_ICMD_ATN);
559 1.7.2.2 gwr regs->sci_icmd = icmd;
560 1.7.2.2 gwr lost:
561 1.7.2.2 gwr regs->sci_mode = 0;
562 1.7.2.2 gwr
563 1.7.2.2 gwr return ret;
564 1.7.2.2 gwr }
565 1.7.2.2 gwr
566 1.7.2.2 gwr sci_data_out(regs, phase, count, data)
567 1.7.2.2 gwr register volatile sci_regmap_t *regs;
568 1.7.2.2 gwr unsigned char *data;
569 1.7.2.2 gwr {
570 1.7.2.2 gwr register unsigned char icmd;
571 1.7.2.2 gwr register int cnt=0;
572 1.7.2.2 gwr
573 1.7.2.2 gwr /* ..checks.. */
574 1.7.2.2 gwr
575 1.7.2.2 gwr icmd = regs->sci_icmd & ~(SCI_ICMD_DIFF|SCI_ICMD_TEST);
576 1.7.2.2 gwr loop:
577 1.7.2.2 gwr if (SCI_CUR_PHASE(regs->sci_bus_csr) != phase)
578 1.7.2.2 gwr return cnt;
579 1.7.2.2 gwr
580 1.7.2.2 gwr WAIT_FOR_REQ(regs);
581 1.7.2.2 gwr icmd |= SCI_ICMD_DATA;
582 1.7.2.2 gwr regs->sci_icmd = icmd;
583 1.7.2.2 gwr regs->sci_odata = *data++;
584 1.7.2.2 gwr icmd |= SCI_ICMD_ACK;
585 1.7.2.2 gwr regs->sci_icmd = icmd;
586 1.7.2.2 gwr
587 1.7.2.2 gwr icmd &= ~(SCI_ICMD_DATA|SCI_ICMD_ACK);
588 1.7.2.2 gwr WAIT_FOR_NOT_REQ(regs);
589 1.7.2.2 gwr regs->sci_icmd = icmd;
590 1.7.2.2 gwr ++cnt;
591 1.7.2.2 gwr if (--count > 0)
592 1.7.2.2 gwr goto loop;
593 1.7.2.2 gwr scsi_timeout_error:
594 1.7.2.2 gwr return cnt;
595 1.7.2.2 gwr }
596 1.7.2.2 gwr
597 1.7.2.2 gwr sci_data_in(regs, phase, count, data)
598 1.7.2.2 gwr register volatile sci_regmap_t *regs;
599 1.7.2.2 gwr unsigned char *data;
600 1.7.2.2 gwr {
601 1.7.2.2 gwr register unsigned char icmd;
602 1.7.2.2 gwr register int cnt=0;
603 1.7.2.2 gwr
604 1.7.2.2 gwr /* ..checks.. */
605 1.7.2.2 gwr
606 1.7.2.2 gwr icmd = regs->sci_icmd & ~(SCI_ICMD_DIFF|SCI_ICMD_TEST);
607 1.7.2.2 gwr
608 1.7.2.2 gwr loop:
609 1.7.2.2 gwr if (SCI_CUR_PHASE(regs->sci_bus_csr) != phase)
610 1.7.2.2 gwr return cnt;
611 1.7.2.2 gwr
612 1.7.2.2 gwr WAIT_FOR_REQ(regs);
613 1.7.2.2 gwr *data++ = regs->sci_data;
614 1.7.2.2 gwr icmd |= SCI_ICMD_ACK;
615 1.7.2.2 gwr regs->sci_icmd = icmd;
616 1.7.2.2 gwr
617 1.7.2.2 gwr icmd &= ~SCI_ICMD_ACK;
618 1.7.2.2 gwr WAIT_FOR_NOT_REQ(regs);
619 1.7.2.2 gwr regs->sci_icmd = icmd;
620 1.7.2.2 gwr ++cnt;
621 1.7.2.2 gwr if (--count > 0)
622 1.7.2.2 gwr goto loop;
623 1.7.2.2 gwr
624 1.7.2.2 gwr scsi_timeout_error:
625 1.7.2.2 gwr return cnt;
626 1.7.2.2 gwr }
627 1.7.2.2 gwr
628 1.7.2.2 gwr static int
629 1.7.2.2 gwr si_command_transfer(register volatile sci_regmap_t *regs,
630 1.7.2.2 gwr int maxlen, u_char *data, u_char *status, u_char *msg)
631 1.7.2.2 gwr {
632 1.7.2.2 gwr int xfer=0, phase;
633 1.7.2.2 gwr
634 1.7.2.2 gwr /* printf("command_transfer called for 0x%x.\n", *data); */
635 1.7.2.2 gwr
636 1.7.2.2 gwr regs->sci_icmd = 0;
637 1.7.2.2 gwr
638 1.7.2.2 gwr while (1) {
639 1.7.2.2 gwr
640 1.7.2.2 gwr WAIT_FOR_REQ(regs);
641 1.7.2.2 gwr
642 1.7.2.2 gwr phase = SCI_CUR_PHASE(regs->sci_bus_csr);
643 1.7.2.2 gwr
644 1.7.2.2 gwr switch (phase) {
645 1.7.2.2 gwr case SCSI_PHASE_CMD:
646 1.7.2.2 gwr SCI_ACK(regs,SCSI_PHASE_CMD);
647 1.7.2.2 gwr xfer += sci_data_out(regs, SCSI_PHASE_CMD,
648 1.7.2.2 gwr maxlen, data);
649 1.7.2.2 gwr return xfer;
650 1.7.2.2 gwr case SCSI_PHASE_DATA_IN:
651 1.7.2.2 gwr printf("Data in phase in command_transfer?\n");
652 1.7.2.2 gwr return 0;
653 1.7.2.2 gwr case SCSI_PHASE_DATA_OUT:
654 1.7.2.2 gwr printf("Data out phase in command_transfer?\n");
655 1.7.2.2 gwr return 0;
656 1.7.2.2 gwr case SCSI_PHASE_STATUS:
657 1.7.2.2 gwr SCI_ACK(regs,SCSI_PHASE_STATUS);
658 1.7.2.2 gwr printf("status in command_transfer.\n");
659 1.7.2.2 gwr sci_data_in(regs, SCSI_PHASE_STATUS,
660 1.7.2.2 gwr 1, status);
661 1.7.2.2 gwr break;
662 1.7.2.2 gwr case SCSI_PHASE_MESSAGE_IN:
663 1.7.2.2 gwr SCI_ACK(regs,SCSI_PHASE_MESSAGE_IN);
664 1.7.2.2 gwr printf("msgin in command_transfer.\n");
665 1.7.2.2 gwr sci_data_in(regs, SCSI_PHASE_MESSAGE_IN,
666 1.7.2.2 gwr 1, msg);
667 1.7.2.2 gwr break;
668 1.7.2.2 gwr case SCSI_PHASE_MESSAGE_OUT:
669 1.7.2.2 gwr SCI_ACK(regs,SCSI_PHASE_MESSAGE_OUT);
670 1.7.2.2 gwr sci_data_out(regs, SCSI_PHASE_MESSAGE_OUT,
671 1.7.2.2 gwr 1, msg);
672 1.7.2.2 gwr break;
673 1.7.2.2 gwr default:
674 1.7.2.2 gwr printf("Unexpected phase 0x%x in "
675 1.7.2.2 gwr "command_transfer().\n", phase);
676 1.7.2.2 gwr scsi_timeout_error:
677 1.7.2.2 gwr return xfer;
678 1.7.2.2 gwr break;
679 1.7.2.2 gwr }
680 1.7.2.2 gwr }
681 1.7.2.2 gwr }
682 1.7.2.2 gwr
683 1.7.2.2 gwr static int
684 1.7.2.2 gwr si_data_transfer(register volatile sci_regmap_t *regs,
685 1.7.2.2 gwr int maxlen, u_char *data, u_char *status, u_char *msg)
686 1.7.2.2 gwr {
687 1.7.2.2 gwr int retlen = 0, xfer, phase;
688 1.7.2.2 gwr
689 1.7.2.2 gwr regs->sci_icmd = 0;
690 1.7.2.2 gwr
691 1.7.2.2 gwr *status = 0;
692 1.7.2.2 gwr
693 1.7.2.2 gwr while (1) {
694 1.7.2.2 gwr
695 1.7.2.2 gwr WAIT_FOR_REQ(regs);
696 1.7.2.2 gwr
697 1.7.2.2 gwr phase = SCI_CUR_PHASE(regs->sci_bus_csr);
698 1.7.2.2 gwr
699 1.7.2.2 gwr switch (phase) {
700 1.7.2.2 gwr case SCSI_PHASE_CMD:
701 1.7.2.2 gwr printf("Command phase in data_transfer().\n");
702 1.7.2.2 gwr return retlen;
703 1.7.2.2 gwr case SCSI_PHASE_DATA_IN:
704 1.7.2.2 gwr SCI_ACK(regs,SCSI_PHASE_DATA_IN);
705 1.7.2.2 gwr #if PSEUDO_DMA
706 1.7.2.2 gwr xfer = sci_pdma_in(regs, SCSI_PHASE_DATA_IN,
707 1.7.2.2 gwr maxlen, data);
708 1.7.2.2 gwr #else
709 1.7.2.2 gwr xfer = sci_data_in(regs, SCSI_PHASE_DATA_IN,
710 1.7.2.2 gwr maxlen, data);
711 1.7.2.2 gwr #endif
712 1.7.2.2 gwr retlen += xfer;
713 1.7.2.2 gwr maxlen -= xfer;
714 1.7.2.2 gwr break;
715 1.7.2.2 gwr case SCSI_PHASE_DATA_OUT:
716 1.7.2.2 gwr SCI_ACK(regs,SCSI_PHASE_DATA_OUT);
717 1.7.2.2 gwr #if PSEUDO_DMA
718 1.7.2.2 gwr xfer = sci_pdma_out(regs, SCSI_PHASE_DATA_OUT,
719 1.7.2.2 gwr maxlen, data);
720 1.7.2.2 gwr #else
721 1.7.2.2 gwr xfer = sci_data_out(regs, SCSI_PHASE_DATA_OUT,
722 1.7.2.2 gwr maxlen, data);
723 1.7.2.2 gwr #endif
724 1.7.2.2 gwr retlen += xfer;
725 1.7.2.2 gwr maxlen -= xfer;
726 1.7.2.2 gwr break;
727 1.7.2.2 gwr case SCSI_PHASE_STATUS:
728 1.7.2.2 gwr SCI_ACK(regs,SCSI_PHASE_STATUS);
729 1.7.2.2 gwr sci_data_in(regs, SCSI_PHASE_STATUS,
730 1.7.2.2 gwr 1, status);
731 1.7.2.2 gwr break;
732 1.7.2.2 gwr case SCSI_PHASE_MESSAGE_IN:
733 1.7.2.2 gwr SCI_ACK(regs,SCSI_PHASE_MESSAGE_IN);
734 1.7.2.2 gwr sci_data_in(regs, SCSI_PHASE_MESSAGE_IN,
735 1.7.2.2 gwr 1, msg);
736 1.7.2.2 gwr if (*msg == 0) {
737 1.7.2.2 gwr return retlen;
738 1.7.2.2 gwr } else {
739 1.7.2.2 gwr printf( "message 0x%x in "
740 1.7.2.2 gwr "data_transfer.\n", *msg);
741 1.7.2.2 gwr }
742 1.7.2.2 gwr break;
743 1.7.2.2 gwr case SCSI_PHASE_MESSAGE_OUT:
744 1.7.2.2 gwr SCI_ACK(regs,SCSI_PHASE_MESSAGE_OUT);
745 1.7.2.2 gwr sci_data_out(regs, SCSI_PHASE_MESSAGE_OUT,
746 1.7.2.2 gwr 1, msg);
747 1.7.2.2 gwr break;
748 1.7.2.2 gwr default:
749 1.7.2.2 gwr printf( "Unexpected phase 0x%x in "
750 1.7.2.2 gwr "data_transfer().\n", phase);
751 1.7.2.2 gwr scsi_timeout_error:
752 1.7.2.2 gwr return retlen;
753 1.7.2.2 gwr break;
754 1.7.2.2 gwr }
755 1.7.2.2 gwr }
756 1.7.2.2 gwr }
757 1.7.2.2 gwr
758 1.7.2.2 gwr static int
759 1.7.2.2 gwr si_dorequest(register volatile sci_regmap_t *regs,
760 1.7.2.2 gwr int target, int lun, u_char *cmd, int cmdlen,
761 1.7.2.2 gwr char *databuf, int datalen, int *sent, int *ret)
762 1.7.2.2 gwr {
763 1.7.2.2 gwr /* Returns 0 on success, -1 on internal error, or the status byte */
764 1.7.2.2 gwr int cmd_bytes_sent, r;
765 1.7.2.2 gwr u_char stat, msg, c;
766 1.7.2.2 gwr
767 1.7.2.2 gwr *sent = 0;
768 1.7.2.2 gwr
769 1.7.2.2 gwr if ( ( r = si_select_target(regs, 7, target, 1) ) != SCSI_RET_SUCCESS) {
770 1.7.2.2 gwr *ret = r;
771 1.7.2.2 gwr SCI_CLR_INTR(regs);
772 1.7.2.2 gwr switch (r) {
773 1.7.2.2 gwr case SCSI_RET_RETRY:
774 1.7.2.2 gwr return 0x08;
775 1.7.2.2 gwr default:
776 1.7.2.2 gwr printf("si_select_target(target %d, lun %d) failed(%d).\n",
777 1.7.2.2 gwr target, lun, r);
778 1.7.2.2 gwr case SCSI_RET_DEVICE_DOWN:
779 1.7.2.2 gwr return -1;
780 1.7.2.2 gwr }
781 1.7.2.2 gwr }
782 1.7.2.2 gwr
783 1.7.2.2 gwr c = 0x80 | lun;
784 1.7.2.2 gwr
785 1.7.2.2 gwr if ((cmd_bytes_sent = si_command_transfer(regs, cmdlen,
786 1.7.2.2 gwr (u_char *) cmd, &stat, &c))
787 1.7.2.2 gwr != cmdlen) {
788 1.7.2.2 gwr SCI_CLR_INTR(regs);
789 1.7.2.2 gwr *ret = SCSI_RET_COMMAND_FAIL;
790 1.7.2.2 gwr printf("Data underrun sending CCB (%d bytes of %d, sent).\n",
791 1.7.2.2 gwr cmd_bytes_sent, cmdlen);
792 1.7.2.2 gwr return -1;
793 1.7.2.2 gwr }
794 1.7.2.2 gwr
795 1.7.2.2 gwr *sent=si_data_transfer(regs, datalen, (u_char *)databuf,
796 1.7.2.2 gwr &stat, &msg);
797 1.7.2.2 gwr
798 1.7.2.2 gwr *ret = 0;
799 1.7.2.2 gwr return stat;
800 1.7.2.2 gwr }
801 1.7.2.2 gwr
802 1.7.2.2 gwr static int
803 1.7.2.2 gwr si_generic(int adapter, int id, int lun, struct scsi_generic *cmd,
804 1.7.2.2 gwr int cmdlen, void *databuf, int datalen)
805 1.7.2.2 gwr {
806 1.7.2.2 gwr register struct ncr5380_softc *ncr5380 = sicd.cd_devs[adapter];
807 1.7.2.2 gwr register volatile sci_regmap_t *regs = ncr5380->sc_regs;
808 1.7.2.2 gwr int i,j,sent,ret;
809 1.7.2.2 gwr
810 1.7.2.2 gwr if (cmd->opcode == TEST_UNIT_READY) /* XXX */
811 1.7.2.2 gwr cmd->bytes[0] = ((u_char) lun << 5);
812 1.7.2.2 gwr
813 1.7.2.2 gwr i = si_dorequest(regs, id, lun, (u_char *) cmd, cmdlen,
814 1.7.2.2 gwr databuf, datalen, &sent, &ret);
815 1.7.2.2 gwr
816 1.7.2.2 gwr return i;
817 1.7.2.2 gwr }
818 1.7.2.2 gwr
819 1.7.2.2 gwr static int
820 1.7.2.2 gwr si_group0(int adapter, int id, int lun, int opcode, int addr, int len,
821 1.7.2.2 gwr int flags, caddr_t databuf, int datalen)
822 1.7.2.2 gwr {
823 1.7.2.2 gwr register struct ncr5380_softc *ncr5380 = sicd.cd_devs[adapter];
824 1.7.2.2 gwr register volatile sci_regmap_t *regs = ncr5380->sc_regs;
825 1.7.2.2 gwr unsigned char cmd[6];
826 1.7.2.2 gwr int i,j,sent,ret;
827 1.7.2.2 gwr
828 1.7.2.2 gwr cmd[0] = opcode; /* Operation code */
829 1.7.2.2 gwr cmd[1] = (lun << 5) | ((addr >> 16) & 0x1F); /* Lun & MSB of addr */
830 1.7.2.2 gwr cmd[2] = (addr >> 8) & 0xFF; /* addr */
831 1.7.2.2 gwr cmd[3] = addr & 0xFF; /* LSB of addr */
832 1.7.2.2 gwr cmd[4] = len; /* Allocation length */
833 1.7.2.2 gwr cmd[5] = flags; /* Link/Flag */
834 1.7.2.2 gwr
835 1.7.2.2 gwr i = si_dorequest(regs, id, lun, cmd, 6, databuf, datalen, &sent, &ret);
836 1.7.2.2 gwr
837 1.7.2.2 gwr return i;
838 1.7.2.2 gwr }
839