si.c revision 1.28
1 /* $NetBSD: si.c,v 1.28 1996/10/11 00:46:50 christos Exp $ */ 2 3 /* 4 * Copyright (c) 1995 David Jones, Gordon W. Ross 5 * Copyright (c) 1994 Adam Glass 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. The name of the authors may not be used to endorse or promote products 17 * derived from this software without specific prior written permission. 18 * 4. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by 21 * Adam Glass, David Jones, and Gordon Ross 22 * 23 * THIS SOFTWARE IS PROVIDED BY THE AUTHORS ``AS IS'' AND ANY EXPRESS OR 24 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 25 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 26 * IN NO EVENT SHALL THE AUTHORS BE LIABLE FOR ANY DIRECT, INDIRECT, 27 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 28 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 29 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 30 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 32 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 33 */ 34 35 /* 36 * This file contains only the machine-dependent parts of the 37 * Sun3 SCSI driver. (Autoconfig stuff and DMA functions.) 38 * The machine-independent parts are in ncr5380sbc.c 39 * 40 * Supported hardware includes: 41 * Sun SCSI-3 on OBIO (Sun3/50,Sun3/60) 42 * Sun SCSI-3 on VME (Sun3/160,Sun3/260) 43 * 44 * Could be made to support the Sun3/E if someone wanted to. 45 * 46 * Note: Both supported variants of the Sun SCSI-3 adapter have 47 * some really unusual "features" for this driver to deal with, 48 * generally related to the DMA engine. The OBIO variant will 49 * ignore any attempt to write the FIFO count register while the 50 * SCSI bus is in DATA_IN or DATA_OUT phase. This is dealt with 51 * by setting the FIFO count early in COMMAND or MSG_IN phase. 52 * 53 * The VME variant has a bit to enable or disable the DMA engine, 54 * but that bit also gates the interrupt line from the NCR5380! 55 * Therefore, in order to get any interrupt from the 5380, (i.e. 56 * for reselect) one must clear the DMA engine transfer count and 57 * then enable DMA. This has the further complication that you 58 * CAN NOT touch the NCR5380 while the DMA enable bit is set, so 59 * we have to turn DMA back off before we even look at the 5380. 60 * 61 * What wonderfully whacky hardware this is! 62 * 63 * Credits, history: 64 * 65 * David Jones wrote the initial version of this module, which 66 * included support for the VME adapter only. (no reselection). 67 * 68 * Gordon Ross added support for the OBIO adapter, and re-worked 69 * both the VME and OBIO code to support disconnect/reselect. 70 * (Required figuring out the hardware "features" noted above.) 71 * 72 * The autoconfiguration boilerplate came from Adam Glass. 73 */ 74 75 #include <sys/param.h> 76 #include <sys/systm.h> 77 #include <sys/errno.h> 78 #include <sys/kernel.h> 79 #include <sys/malloc.h> 80 #include <sys/device.h> 81 #include <sys/buf.h> 82 #include <sys/proc.h> 83 #include <sys/user.h> 84 85 #include <scsi/scsi_all.h> 86 #include <scsi/scsi_debug.h> 87 #include <scsi/scsiconf.h> 88 89 #include <machine/autoconf.h> 90 #include <machine/isr.h> 91 #include <machine/obio.h> 92 #include <machine/dvma.h> 93 94 #define DEBUG XXX 95 96 #include <dev/ic/ncr5380reg.h> 97 #include <dev/ic/ncr5380var.h> 98 99 #include "sireg.h" 100 #include "sivar.h" 101 102 int si_debug = 0; 103 #ifdef DEBUG 104 static int si_link_flags = 0 /* | SDEV_DB2 */ ; 105 #endif 106 107 /* How long to wait for DMA before declaring an error. */ 108 int si_dma_intr_timo = 500; /* ticks (sec. X 100) */ 109 110 static void si_minphys __P((struct buf *)); 111 112 static struct scsi_adapter si_ops = { 113 ncr5380_scsi_cmd, /* scsi_cmd() */ 114 si_minphys, /* scsi_minphys() */ 115 NULL, /* open_target_lu() */ 116 NULL, /* close_target_lu() */ 117 }; 118 119 /* This is copied from julian's bt driver */ 120 /* "so we have a default dev struct for our link struct." */ 121 static struct scsi_device si_dev = { 122 NULL, /* Use default error handler. */ 123 NULL, /* Use default start handler. */ 124 NULL, /* Use default async handler. */ 125 NULL, /* Use default "done" routine. */ 126 }; 127 128 /* 129 * New-style autoconfig attachment. The cfattach 130 * structures are in si_obio.c and si_vme.c 131 */ 132 133 struct cfdriver si_cd = { 134 NULL, "si", DV_DULL 135 }; 136 137 138 void 139 si_attach(sc) 140 struct si_softc *sc; 141 { 142 struct ncr5380_softc *ncr_sc = (void *)sc; 143 volatile struct si_regs *regs = sc->sc_regs; 144 int i; 145 146 /* 147 * Fill in the prototype scsi_link. 148 */ 149 ncr_sc->sc_link.channel = SCSI_CHANNEL_ONLY_ONE; 150 ncr_sc->sc_link.adapter_softc = sc; 151 ncr_sc->sc_link.adapter_target = 7; 152 ncr_sc->sc_link.adapter = &si_ops; 153 ncr_sc->sc_link.device = &si_dev; 154 155 #ifdef DEBUG 156 if (si_debug) 157 kprintf("si: Set TheSoftC=%x TheRegs=%x\n", sc, regs); 158 ncr_sc->sc_link.flags |= si_link_flags; 159 #endif 160 161 /* 162 * Initialize fields used by the MI code 163 */ 164 ncr_sc->sci_r0 = ®s->sci.sci_r0; 165 ncr_sc->sci_r1 = ®s->sci.sci_r1; 166 ncr_sc->sci_r2 = ®s->sci.sci_r2; 167 ncr_sc->sci_r3 = ®s->sci.sci_r3; 168 ncr_sc->sci_r4 = ®s->sci.sci_r4; 169 ncr_sc->sci_r5 = ®s->sci.sci_r5; 170 ncr_sc->sci_r6 = ®s->sci.sci_r6; 171 ncr_sc->sci_r7 = ®s->sci.sci_r7; 172 173 /* 174 * Allocate DMA handles. 175 */ 176 i = SCI_OPENINGS * sizeof(struct si_dma_handle); 177 sc->sc_dma = (struct si_dma_handle *) 178 malloc(i, M_DEVBUF, M_WAITOK); 179 if (sc->sc_dma == NULL) 180 panic("si: dvma_malloc failed\n"); 181 for (i = 0; i < SCI_OPENINGS; i++) 182 sc->sc_dma[i].dh_flags = 0; 183 184 /* 185 * Initialize si board itself. 186 */ 187 si_reset_adapter(ncr_sc); 188 ncr5380_init(ncr_sc); 189 ncr5380_reset_scsibus(ncr_sc); 190 config_found(&(ncr_sc->sc_dev), &(ncr_sc->sc_link), scsiprint); 191 } 192 193 static void 194 si_minphys(struct buf *bp) 195 { 196 if (bp->b_bcount > MAX_DMA_LEN) { 197 #ifdef DEBUG 198 if (si_debug) { 199 kprintf("si_minphys len = 0x%x.\n", bp->b_bcount); 200 Debugger(); 201 } 202 #endif 203 bp->b_bcount = MAX_DMA_LEN; 204 } 205 return (minphys(bp)); 206 } 207 208 209 #define CSR_WANT (SI_CSR_SBC_IP | SI_CSR_DMA_IP | \ 210 SI_CSR_DMA_CONFLICT | SI_CSR_DMA_BUS_ERR ) 211 212 int 213 si_intr(void *arg) 214 { 215 struct si_softc *sc = arg; 216 volatile struct si_regs *si = sc->sc_regs; 217 int dma_error, claimed; 218 u_short csr; 219 220 claimed = 0; 221 dma_error = 0; 222 223 /* SBC interrupt? DMA interrupt? */ 224 csr = si->si_csr; 225 NCR_TRACE("si_intr: csr=0x%x\n", csr); 226 227 if (csr & SI_CSR_DMA_CONFLICT) { 228 dma_error |= SI_CSR_DMA_CONFLICT; 229 kprintf("si_intr: DMA conflict\n"); 230 } 231 if (csr & SI_CSR_DMA_BUS_ERR) { 232 dma_error |= SI_CSR_DMA_BUS_ERR; 233 kprintf("si_intr: DMA bus error\n"); 234 } 235 if (dma_error) { 236 if (sc->ncr_sc.sc_state & NCR_DOINGDMA) 237 sc->ncr_sc.sc_state |= NCR_ABORTING; 238 /* Make sure we will call the main isr. */ 239 csr |= SI_CSR_DMA_IP; 240 } 241 242 if (csr & (SI_CSR_SBC_IP | SI_CSR_DMA_IP)) { 243 claimed = ncr5380_intr(&sc->ncr_sc); 244 #ifdef DEBUG 245 if (!claimed) { 246 kprintf("si_intr: spurious from SBC\n"); 247 if (si_debug & 4) { 248 Debugger(); /* XXX */ 249 } 250 } 251 #endif 252 } 253 254 return (claimed); 255 } 256 257 258 void 259 si_reset_adapter(struct ncr5380_softc *ncr_sc) 260 { 261 struct si_softc *sc = (struct si_softc *)ncr_sc; 262 volatile struct si_regs *si = sc->sc_regs; 263 264 #ifdef DEBUG 265 if (si_debug) { 266 kprintf("si_reset_adapter\n"); 267 } 268 #endif 269 270 /* 271 * The SCSI3 controller has an 8K FIFO to buffer data between the 272 * 5380 and the DMA. Make sure it starts out empty. 273 * 274 * The reset bits in the CSR are active low. 275 */ 276 si->si_csr = 0; 277 delay(10); 278 si->si_csr = SI_CSR_FIFO_RES | SI_CSR_SCSI_RES | SI_CSR_INTR_EN; 279 delay(10); 280 si->fifo_count = 0; 281 282 if (sc->sc_adapter_type == BUS_VME16) { 283 si->dma_addrh = 0; 284 si->dma_addrl = 0; 285 si->dma_counth = 0; 286 si->dma_countl = 0; 287 si->si_iv_am = sc->sc_adapter_iv_am; 288 si->fifo_cnt_hi = 0; 289 } 290 291 SCI_CLR_INTR(ncr_sc); 292 } 293 294 295 /***************************************************************** 296 * Common functions for DMA 297 ****************************************************************/ 298 299 /* 300 * Allocate a DMA handle and put it in sc->sc_dma. Prepare 301 * for DMA transfer. On the Sun3, this means mapping the buffer 302 * into DVMA space. dvma_mapin() flushes the cache for us. 303 */ 304 void 305 si_dma_alloc(ncr_sc) 306 struct ncr5380_softc *ncr_sc; 307 { 308 struct si_softc *sc = (struct si_softc *)ncr_sc; 309 struct sci_req *sr = ncr_sc->sc_current; 310 struct scsi_xfer *xs = sr->sr_xs; 311 struct si_dma_handle *dh; 312 int i, xlen; 313 u_long addr; 314 315 #ifdef DIAGNOSTIC 316 if (sr->sr_dma_hand != NULL) 317 panic("si_dma_alloc: already have DMA handle"); 318 #endif 319 320 addr = (u_long) ncr_sc->sc_dataptr; 321 xlen = ncr_sc->sc_datalen; 322 323 /* If the DMA start addr is misaligned then do PIO */ 324 if ((addr & 1) || (xlen & 1)) { 325 kprintf("si_dma_alloc: misaligned.\n"); 326 return; 327 } 328 329 /* Make sure our caller checked sc_min_dma_len. */ 330 if (xlen < MIN_DMA_LEN) 331 panic("si_dma_alloc: xlen=0x%x\n", xlen); 332 333 /* 334 * Never attempt single transfers of more than 63k, because 335 * our count register may be only 16 bits (an OBIO adapter). 336 * This should never happen since already bounded by minphys(). 337 * XXX - Should just segment these... 338 */ 339 if (xlen > MAX_DMA_LEN) { 340 kprintf("si_dma_alloc: excessive xlen=0x%x\n", xlen); 341 Debugger(); 342 ncr_sc->sc_datalen = xlen = MAX_DMA_LEN; 343 } 344 345 /* Find free DMA handle. Guaranteed to find one since we have 346 as many DMA handles as the driver has processes. */ 347 for (i = 0; i < SCI_OPENINGS; i++) { 348 if ((sc->sc_dma[i].dh_flags & SIDH_BUSY) == 0) 349 goto found; 350 } 351 panic("si: no free DMA handles."); 352 found: 353 354 dh = &sc->sc_dma[i]; 355 dh->dh_flags = SIDH_BUSY; 356 dh->dh_addr = (u_char*) addr; 357 dh->dh_maplen = xlen; 358 dh->dh_dvma = 0; 359 360 /* Copy the "write" flag for convenience. */ 361 if (xs->flags & SCSI_DATA_OUT) 362 dh->dh_flags |= SIDH_OUT; 363 364 #if 0 365 /* 366 * Some machines might not need to remap B_PHYS buffers. 367 * The sun3 does not map B_PHYS buffers into DVMA space, 368 * (they are mapped into normal KV space) so on the sun3 369 * we must always remap to a DVMA address here. Re-map is 370 * cheap anyway, because it's done by segments, not pages. 371 */ 372 if (xs->bp && (xs->bp->b_flags & B_PHYS)) 373 dh->dh_flags |= SIDH_PHYS; 374 #endif 375 376 dh->dh_dvma = (u_long) dvma_mapin((char *)addr, xlen); 377 if (!dh->dh_dvma) { 378 /* Can't remap segment */ 379 kprintf("si_dma_alloc: can't remap %x/%x\n", 380 dh->dh_addr, dh->dh_maplen); 381 dh->dh_flags = 0; 382 return; 383 } 384 385 /* success */ 386 sr->sr_dma_hand = dh; 387 388 return; 389 } 390 391 392 void 393 si_dma_free(ncr_sc) 394 struct ncr5380_softc *ncr_sc; 395 { 396 struct sci_req *sr = ncr_sc->sc_current; 397 struct si_dma_handle *dh = sr->sr_dma_hand; 398 399 #ifdef DIAGNOSTIC 400 if (dh == NULL) 401 panic("si_dma_free: no DMA handle"); 402 #endif 403 404 if (ncr_sc->sc_state & NCR_DOINGDMA) 405 panic("si_dma_free: free while in progress"); 406 407 if (dh->dh_flags & SIDH_BUSY) { 408 /* XXX - Should separate allocation and mapping. */ 409 /* Give back the DVMA space. */ 410 dvma_mapout((caddr_t)dh->dh_dvma, dh->dh_maplen); 411 dh->dh_dvma = 0; 412 dh->dh_flags = 0; 413 } 414 sr->sr_dma_hand = NULL; 415 } 416 417 418 #define CSR_MASK (SI_CSR_SBC_IP | SI_CSR_DMA_IP | \ 419 SI_CSR_DMA_CONFLICT | SI_CSR_DMA_BUS_ERR) 420 #define POLL_TIMO 50000 /* X100 = 5 sec. */ 421 422 /* 423 * Poll (spin-wait) for DMA completion. 424 * Called right after xx_dma_start(), and 425 * xx_dma_stop() will be called next. 426 * Same for either VME or OBIO. 427 */ 428 void 429 si_dma_poll(ncr_sc) 430 struct ncr5380_softc *ncr_sc; 431 { 432 struct si_softc *sc = (struct si_softc *)ncr_sc; 433 struct sci_req *sr = ncr_sc->sc_current; 434 struct si_dma_handle *dh = sr->sr_dma_hand; 435 volatile struct si_regs *si = sc->sc_regs; 436 int tmo; 437 438 /* Make sure DMA started successfully. */ 439 if (ncr_sc->sc_state & NCR_ABORTING) 440 return; 441 442 /* 443 * XXX: The Sun driver waits for ~SI_CSR_DMA_ACTIVE here 444 * XXX: (on obio) or even worse (on vme) a 10mS. delay! 445 * XXX: I really doubt that is necessary... 446 */ 447 448 /* Wait for any "dma complete" or error bits. */ 449 tmo = POLL_TIMO; 450 for (;;) { 451 if (si->si_csr & CSR_MASK) 452 break; 453 if (--tmo <= 0) { 454 kprintf("si: DMA timeout (while polling)\n"); 455 /* Indicate timeout as MI code would. */ 456 sr->sr_flags |= SR_OVERDUE; 457 break; 458 } 459 delay(100); 460 } 461 NCR_TRACE("si_dma_poll: waited %d\n", 462 POLL_TIMO - tmo); 463 464 #ifdef DEBUG 465 if (si_debug & 2) { 466 kprintf("si_dma_poll: done, csr=0x%x\n", si->si_csr); 467 } 468 #endif 469 } 470 471
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