si.c revision 1.35.2.1
1 /* $NetBSD: si.c,v 1.35.2.1 1997/07/01 17:34:35 bouyer Exp $ */ 2 3 /*- 4 * Copyright (c) 1996 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Adam Glass, David Jones, and Gordon W. Ross. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 /* 40 * This file contains only the machine-dependent parts of the 41 * Sun3 SCSI driver. (Autoconfig stuff and DMA functions.) 42 * The machine-independent parts are in ncr5380sbc.c 43 * 44 * Supported hardware includes: 45 * Sun SCSI-3 on OBIO (Sun3/50,Sun3/60) 46 * Sun SCSI-3 on VME (Sun3/160,Sun3/260) 47 * 48 * Could be made to support the Sun3/E if someone wanted to. 49 * 50 * Note: Both supported variants of the Sun SCSI-3 adapter have 51 * some really unusual "features" for this driver to deal with, 52 * generally related to the DMA engine. The OBIO variant will 53 * ignore any attempt to write the FIFO count register while the 54 * SCSI bus is in DATA_IN or DATA_OUT phase. This is dealt with 55 * by setting the FIFO count early in COMMAND or MSG_IN phase. 56 * 57 * The VME variant has a bit to enable or disable the DMA engine, 58 * but that bit also gates the interrupt line from the NCR5380! 59 * Therefore, in order to get any interrupt from the 5380, (i.e. 60 * for reselect) one must clear the DMA engine transfer count and 61 * then enable DMA. This has the further complication that you 62 * CAN NOT touch the NCR5380 while the DMA enable bit is set, so 63 * we have to turn DMA back off before we even look at the 5380. 64 * 65 * What wonderfully whacky hardware this is! 66 * 67 * Credits, history: 68 * 69 * David Jones wrote the initial version of this module, which 70 * included support for the VME adapter only. (no reselection). 71 * 72 * Gordon Ross added support for the OBIO adapter, and re-worked 73 * both the VME and OBIO code to support disconnect/reselect. 74 * (Required figuring out the hardware "features" noted above.) 75 * 76 * The autoconfiguration boilerplate came from Adam Glass. 77 */ 78 79 #include <sys/param.h> 80 #include <sys/systm.h> 81 #include <sys/errno.h> 82 #include <sys/kernel.h> 83 #include <sys/malloc.h> 84 #include <sys/device.h> 85 #include <sys/buf.h> 86 #include <sys/proc.h> 87 #include <sys/user.h> 88 89 #include <dev/scsipi/scsi_all.h> 90 #include <dev/scsipi/scsipi_all.h> 91 #include <dev/scsipi/scsipi_debug.h> 92 #include <dev/scsipi/scsiconf.h> 93 94 #include <machine/autoconf.h> 95 #include <machine/dvma.h> 96 97 #define DEBUG XXX 98 99 #include <dev/ic/ncr5380reg.h> 100 #include <dev/ic/ncr5380var.h> 101 102 #include "sireg.h" 103 #include "sivar.h" 104 105 /* 106 * Transfers smaller than this are done using PIO 107 * (on assumption they're not worth DMA overhead) 108 */ 109 #define MIN_DMA_LEN 128 110 111 int si_debug = 0; 112 #ifdef DEBUG 113 static int si_link_flags = 0 /* | SDEV_DB2 */ ; 114 #endif 115 116 /* How long to wait for DMA before declaring an error. */ 117 int si_dma_intr_timo = 500; /* ticks (sec. X 100) */ 118 119 static void si_minphys __P((struct buf *)); 120 121 static struct scsipi_adapter si_ops = { 122 ncr5380_scsi_cmd, /* scsi_cmd() */ 123 si_minphys, /* scsi_minphys() */ 124 NULL, /* open_target_lu() */ 125 NULL, /* close_target_lu() */ 126 }; 127 128 /* This is copied from julian's bt driver */ 129 /* "so we have a default dev struct for our link struct." */ 130 static struct scsipi_device si_dev = { 131 NULL, /* Use default error handler. */ 132 NULL, /* Use default start handler. */ 133 NULL, /* Use default async handler. */ 134 NULL, /* Use default "done" routine. */ 135 }; 136 137 /* 138 * New-style autoconfig attachment. The cfattach 139 * structures are in si_obio.c and si_vme.c 140 */ 141 142 struct cfdriver si_cd = { 143 NULL, "si", DV_DULL 144 }; 145 146 147 void 148 si_attach(sc) 149 struct si_softc *sc; 150 { 151 struct ncr5380_softc *ncr_sc = (void *)sc; 152 volatile struct si_regs *regs = sc->sc_regs; 153 int i; 154 155 /* 156 * Support the "options" (config file flags). 157 * Disconnect/reselect is a per-target mask. 158 * Interrupts and DMA are per-controller. 159 */ 160 ncr_sc->sc_no_disconnect = 161 (sc->sc_options & SI_NO_DISCONNECT); 162 ncr_sc->sc_parity_disable = 163 (sc->sc_options & SI_NO_PARITY_CHK) >> 8; 164 if (sc->sc_options & SI_FORCE_POLLING) 165 ncr_sc->sc_flags |= NCR5380_FORCE_POLLING; 166 167 #if 1 /* XXX - Temporary */ 168 /* XXX - In case we think DMA is completely broken... */ 169 if (sc->sc_options & SI_DISABLE_DMA) { 170 /* Override this function pointer. */ 171 ncr_sc->sc_dma_alloc = NULL; 172 } 173 #endif 174 ncr_sc->sc_min_dma_len = MIN_DMA_LEN; 175 176 /* 177 * Fill in the prototype scsi_link. 178 */ 179 ncr_sc->sc_link.scsipi_scsi.channel = SCSI_CHANNEL_ONLY_ONE; 180 ncr_sc->sc_link.adapter_softc = sc; 181 ncr_sc->sc_link.scsipi_scsi.adapter_target = 7; 182 ncr_sc->sc_link.adapter = &si_ops; 183 ncr_sc->sc_link.device = &si_dev; 184 ncr_sc->sc_link.type = BUS_SCSI; 185 186 #ifdef DEBUG 187 if (si_debug) 188 printf("si: Set TheSoftC=%p TheRegs=%p\n", sc, regs); 189 ncr_sc->sc_link.flags |= si_link_flags; 190 #endif 191 192 /* 193 * Initialize fields used by the MI code 194 */ 195 ncr_sc->sci_r0 = ®s->sci.sci_r0; 196 ncr_sc->sci_r1 = ®s->sci.sci_r1; 197 ncr_sc->sci_r2 = ®s->sci.sci_r2; 198 ncr_sc->sci_r3 = ®s->sci.sci_r3; 199 ncr_sc->sci_r4 = ®s->sci.sci_r4; 200 ncr_sc->sci_r5 = ®s->sci.sci_r5; 201 ncr_sc->sci_r6 = ®s->sci.sci_r6; 202 ncr_sc->sci_r7 = ®s->sci.sci_r7; 203 204 /* 205 * Allocate DMA handles. 206 */ 207 i = SCI_OPENINGS * sizeof(struct si_dma_handle); 208 sc->sc_dma = (struct si_dma_handle *) 209 malloc(i, M_DEVBUF, M_WAITOK); 210 if (sc->sc_dma == NULL) 211 panic("si: dvma_malloc failed\n"); 212 for (i = 0; i < SCI_OPENINGS; i++) 213 sc->sc_dma[i].dh_flags = 0; 214 215 /* 216 * Initialize si board itself. 217 */ 218 si_reset_adapter(ncr_sc); 219 ncr5380_init(ncr_sc); 220 ncr5380_reset_scsibus(ncr_sc); 221 config_found(&(ncr_sc->sc_dev), &(ncr_sc->sc_link), scsiprint); 222 } 223 224 static void 225 si_minphys(struct buf *bp) 226 { 227 if (bp->b_bcount > MAX_DMA_LEN) { 228 #ifdef DEBUG 229 if (si_debug) { 230 printf("si_minphys len = 0x%x.\n", bp->b_bcount); 231 Debugger(); 232 } 233 #endif 234 bp->b_bcount = MAX_DMA_LEN; 235 } 236 return (minphys(bp)); 237 } 238 239 240 #define CSR_WANT (SI_CSR_SBC_IP | SI_CSR_DMA_IP | \ 241 SI_CSR_DMA_CONFLICT | SI_CSR_DMA_BUS_ERR ) 242 243 int 244 si_intr(void *arg) 245 { 246 struct si_softc *sc = arg; 247 volatile struct si_regs *si = sc->sc_regs; 248 int dma_error, claimed; 249 u_short csr; 250 251 claimed = 0; 252 dma_error = 0; 253 254 /* SBC interrupt? DMA interrupt? */ 255 csr = si->si_csr; 256 NCR_TRACE("si_intr: csr=0x%x\n", csr); 257 258 if (csr & SI_CSR_DMA_CONFLICT) { 259 dma_error |= SI_CSR_DMA_CONFLICT; 260 printf("si_intr: DMA conflict\n"); 261 } 262 if (csr & SI_CSR_DMA_BUS_ERR) { 263 dma_error |= SI_CSR_DMA_BUS_ERR; 264 printf("si_intr: DMA bus error\n"); 265 } 266 if (dma_error) { 267 if (sc->ncr_sc.sc_state & NCR_DOINGDMA) 268 sc->ncr_sc.sc_state |= NCR_ABORTING; 269 /* Make sure we will call the main isr. */ 270 csr |= SI_CSR_DMA_IP; 271 } 272 273 if (csr & (SI_CSR_SBC_IP | SI_CSR_DMA_IP)) { 274 claimed = ncr5380_intr(&sc->ncr_sc); 275 #ifdef DEBUG 276 if (!claimed) { 277 printf("si_intr: spurious from SBC\n"); 278 if (si_debug & 4) { 279 Debugger(); /* XXX */ 280 } 281 } 282 #endif 283 /* Yes, we DID cause this interrupt. */ 284 claimed = 1; 285 } 286 287 return (claimed); 288 } 289 290 291 void 292 si_reset_adapter(struct ncr5380_softc *ncr_sc) 293 { 294 struct si_softc *sc = (struct si_softc *)ncr_sc; 295 volatile struct si_regs *si = sc->sc_regs; 296 297 #ifdef DEBUG 298 if (si_debug) { 299 printf("si_reset_adapter\n"); 300 } 301 #endif 302 303 /* 304 * The SCSI3 controller has an 8K FIFO to buffer data between the 305 * 5380 and the DMA. Make sure it starts out empty. 306 * 307 * The reset bits in the CSR are active low. 308 */ 309 si->si_csr = 0; 310 delay(10); 311 si->si_csr = SI_CSR_FIFO_RES | SI_CSR_SCSI_RES | SI_CSR_INTR_EN; 312 delay(10); 313 si->fifo_count = 0; 314 315 if (sc->sc_adapter_type == BUS_VME16) { 316 si->dma_addrh = 0; 317 si->dma_addrl = 0; 318 si->dma_counth = 0; 319 si->dma_countl = 0; 320 si->si_iv_am = sc->sc_adapter_iv_am; 321 si->fifo_cnt_hi = 0; 322 } 323 324 SCI_CLR_INTR(ncr_sc); 325 } 326 327 328 /***************************************************************** 329 * Common functions for DMA 330 ****************************************************************/ 331 332 /* 333 * Allocate a DMA handle and put it in sc->sc_dma. Prepare 334 * for DMA transfer. On the Sun3, this means mapping the buffer 335 * into DVMA space. dvma_mapin() flushes the cache for us. 336 */ 337 void 338 si_dma_alloc(ncr_sc) 339 struct ncr5380_softc *ncr_sc; 340 { 341 struct si_softc *sc = (struct si_softc *)ncr_sc; 342 struct sci_req *sr = ncr_sc->sc_current; 343 struct scsipi_xfer *xs = sr->sr_xs; 344 struct si_dma_handle *dh; 345 int i, xlen; 346 u_long addr; 347 348 #ifdef DIAGNOSTIC 349 if (sr->sr_dma_hand != NULL) 350 panic("si_dma_alloc: already have DMA handle"); 351 #endif 352 353 addr = (u_long) ncr_sc->sc_dataptr; 354 xlen = ncr_sc->sc_datalen; 355 356 /* If the DMA start addr is misaligned then do PIO */ 357 if ((addr & 1) || (xlen & 1)) { 358 printf("si_dma_alloc: misaligned.\n"); 359 return; 360 } 361 362 /* Make sure our caller checked sc_min_dma_len. */ 363 if (xlen < MIN_DMA_LEN) 364 panic("si_dma_alloc: xlen=0x%x\n", xlen); 365 366 /* 367 * Never attempt single transfers of more than 63k, because 368 * our count register may be only 16 bits (an OBIO adapter). 369 * This should never happen since already bounded by minphys(). 370 * XXX - Should just segment these... 371 */ 372 if (xlen > MAX_DMA_LEN) { 373 printf("si_dma_alloc: excessive xlen=0x%x\n", xlen); 374 Debugger(); 375 ncr_sc->sc_datalen = xlen = MAX_DMA_LEN; 376 } 377 378 /* Find free DMA handle. Guaranteed to find one since we have 379 as many DMA handles as the driver has processes. */ 380 for (i = 0; i < SCI_OPENINGS; i++) { 381 if ((sc->sc_dma[i].dh_flags & SIDH_BUSY) == 0) 382 goto found; 383 } 384 panic("si: no free DMA handles."); 385 found: 386 387 dh = &sc->sc_dma[i]; 388 dh->dh_flags = SIDH_BUSY; 389 dh->dh_addr = (u_char*) addr; 390 dh->dh_maplen = xlen; 391 dh->dh_dvma = 0; 392 393 /* Copy the "write" flag for convenience. */ 394 if (xs->flags & SCSI_DATA_OUT) 395 dh->dh_flags |= SIDH_OUT; 396 397 #if 0 398 /* 399 * Some machines might not need to remap B_PHYS buffers. 400 * The sun3 does not map B_PHYS buffers into DVMA space, 401 * (they are mapped into normal KV space) so on the sun3 402 * we must always remap to a DVMA address here. Re-map is 403 * cheap anyway, because it's done by segments, not pages. 404 */ 405 if (xs->bp && (xs->bp->b_flags & B_PHYS)) 406 dh->dh_flags |= SIDH_PHYS; 407 #endif 408 409 dh->dh_dvma = (u_long) dvma_mapin((char *)addr, xlen); 410 if (!dh->dh_dvma) { 411 /* Can't remap segment */ 412 printf("si_dma_alloc: can't remap %p/0x%x\n", 413 dh->dh_addr, dh->dh_maplen); 414 dh->dh_flags = 0; 415 return; 416 } 417 418 /* success */ 419 sr->sr_dma_hand = dh; 420 421 return; 422 } 423 424 425 void 426 si_dma_free(ncr_sc) 427 struct ncr5380_softc *ncr_sc; 428 { 429 struct sci_req *sr = ncr_sc->sc_current; 430 struct si_dma_handle *dh = sr->sr_dma_hand; 431 432 #ifdef DIAGNOSTIC 433 if (dh == NULL) 434 panic("si_dma_free: no DMA handle"); 435 #endif 436 437 if (ncr_sc->sc_state & NCR_DOINGDMA) 438 panic("si_dma_free: free while in progress"); 439 440 if (dh->dh_flags & SIDH_BUSY) { 441 /* XXX - Should separate allocation and mapping. */ 442 /* Give back the DVMA space. */ 443 dvma_mapout((caddr_t)dh->dh_dvma, dh->dh_maplen); 444 dh->dh_dvma = 0; 445 dh->dh_flags = 0; 446 } 447 sr->sr_dma_hand = NULL; 448 } 449 450 451 #define CSR_MASK (SI_CSR_SBC_IP | SI_CSR_DMA_IP | \ 452 SI_CSR_DMA_CONFLICT | SI_CSR_DMA_BUS_ERR) 453 #define POLL_TIMO 50000 /* X100 = 5 sec. */ 454 455 /* 456 * Poll (spin-wait) for DMA completion. 457 * Called right after xx_dma_start(), and 458 * xx_dma_stop() will be called next. 459 * Same for either VME or OBIO. 460 */ 461 void 462 si_dma_poll(ncr_sc) 463 struct ncr5380_softc *ncr_sc; 464 { 465 struct si_softc *sc = (struct si_softc *)ncr_sc; 466 struct sci_req *sr = ncr_sc->sc_current; 467 volatile struct si_regs *si = sc->sc_regs; 468 int tmo; 469 470 /* Make sure DMA started successfully. */ 471 if (ncr_sc->sc_state & NCR_ABORTING) 472 return; 473 474 /* 475 * XXX: The Sun driver waits for ~SI_CSR_DMA_ACTIVE here 476 * XXX: (on obio) or even worse (on vme) a 10mS. delay! 477 * XXX: I really doubt that is necessary... 478 */ 479 480 /* Wait for any "dma complete" or error bits. */ 481 tmo = POLL_TIMO; 482 for (;;) { 483 if (si->si_csr & CSR_MASK) 484 break; 485 if (--tmo <= 0) { 486 printf("si: DMA timeout (while polling)\n"); 487 /* Indicate timeout as MI code would. */ 488 sr->sr_flags |= SR_OVERDUE; 489 break; 490 } 491 delay(100); 492 } 493 NCR_TRACE("si_dma_poll: waited %d\n", 494 POLL_TIMO - tmo); 495 496 #ifdef DEBUG 497 if (si_debug & 2) { 498 printf("si_dma_poll: done, csr=0x%x\n", si->si_csr); 499 } 500 #endif 501 } 502 503
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