si.c revision 1.45
1 /* $NetBSD: si.c,v 1.45 1999/11/03 14:12:19 jdolecek Exp $ */ 2 3 /*- 4 * Copyright (c) 1996 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Adam Glass, David Jones, and Gordon W. Ross. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 /* 40 * This file contains only the machine-dependent parts of the 41 * Sun3 SCSI driver. (Autoconfig stuff and DMA functions.) 42 * The machine-independent parts are in ncr5380sbc.c 43 * 44 * Supported hardware includes: 45 * Sun SCSI-3 on OBIO (Sun3/50,Sun3/60) 46 * Sun SCSI-3 on VME (Sun3/160,Sun3/260) 47 * 48 * Could be made to support the Sun3/E if someone wanted to. 49 * 50 * Note: Both supported variants of the Sun SCSI-3 adapter have 51 * some really unusual "features" for this driver to deal with, 52 * generally related to the DMA engine. The OBIO variant will 53 * ignore any attempt to write the FIFO count register while the 54 * SCSI bus is in DATA_IN or DATA_OUT phase. This is dealt with 55 * by setting the FIFO count early in COMMAND or MSG_IN phase. 56 * 57 * The VME variant has a bit to enable or disable the DMA engine, 58 * but that bit also gates the interrupt line from the NCR5380! 59 * Therefore, in order to get any interrupt from the 5380, (i.e. 60 * for reselect) one must clear the DMA engine transfer count and 61 * then enable DMA. This has the further complication that you 62 * CAN NOT touch the NCR5380 while the DMA enable bit is set, so 63 * we have to turn DMA back off before we even look at the 5380. 64 * 65 * What wonderfully whacky hardware this is! 66 * 67 * Credits, history: 68 * 69 * David Jones wrote the initial version of this module, which 70 * included support for the VME adapter only. (no reselection). 71 * 72 * Gordon Ross added support for the OBIO adapter, and re-worked 73 * both the VME and OBIO code to support disconnect/reselect. 74 * (Required figuring out the hardware "features" noted above.) 75 * 76 * The autoconfiguration boilerplate came from Adam Glass. 77 */ 78 79 #include "opt_ddb.h" 80 81 #include <sys/param.h> 82 #include <sys/systm.h> 83 #include <sys/errno.h> 84 #include <sys/kernel.h> 85 #include <sys/malloc.h> 86 #include <sys/device.h> 87 #include <sys/buf.h> 88 #include <sys/proc.h> 89 #include <sys/user.h> 90 91 #include <dev/scsipi/scsi_all.h> 92 #include <dev/scsipi/scsipi_all.h> 93 #include <dev/scsipi/scsipi_debug.h> 94 #include <dev/scsipi/scsiconf.h> 95 96 #include <machine/autoconf.h> 97 #include <machine/dvma.h> 98 99 /* #define DEBUG XXX */ 100 101 #include <dev/ic/ncr5380reg.h> 102 #include <dev/ic/ncr5380var.h> 103 104 #include "sireg.h" 105 #include "sivar.h" 106 107 /* 108 * Transfers smaller than this are done using PIO 109 * (on assumption they're not worth DMA overhead) 110 */ 111 #define MIN_DMA_LEN 128 112 113 int si_debug = 0; 114 #ifdef DEBUG 115 static int si_link_flags = 0 /* | SDEV_DB2 */ ; 116 #endif 117 118 /* How long to wait for DMA before declaring an error. */ 119 int si_dma_intr_timo = 500; /* ticks (sec. X 100) */ 120 121 static void si_minphys __P((struct buf *)); 122 123 /* This is copied from julian's bt driver */ 124 /* "so we have a default dev struct for our link struct." */ 125 static struct scsipi_device si_dev = { 126 NULL, /* Use default error handler. */ 127 NULL, /* Use default start handler. */ 128 NULL, /* Use default async handler. */ 129 NULL, /* Use default "done" routine. */ 130 }; 131 132 /* 133 * New-style autoconfig attachment. The cfattach 134 * structures are in si_obio.c and si_vme.c 135 */ 136 137 void 138 si_attach(sc) 139 struct si_softc *sc; 140 { 141 struct ncr5380_softc *ncr_sc = (void *)sc; 142 volatile struct si_regs *regs = sc->sc_regs; 143 int i; 144 145 /* 146 * Support the "options" (config file flags). 147 * Disconnect/reselect is a per-target mask. 148 * Interrupts and DMA are per-controller. 149 */ 150 ncr_sc->sc_no_disconnect = 151 (sc->sc_options & SI_NO_DISCONNECT); 152 ncr_sc->sc_parity_disable = 153 (sc->sc_options & SI_NO_PARITY_CHK) >> 8; 154 if (sc->sc_options & SI_FORCE_POLLING) 155 ncr_sc->sc_flags |= NCR5380_FORCE_POLLING; 156 157 #if 1 /* XXX - Temporary */ 158 /* XXX - In case we think DMA is completely broken... */ 159 if (sc->sc_options & SI_DISABLE_DMA) { 160 /* Override this function pointer. */ 161 ncr_sc->sc_dma_alloc = NULL; 162 } 163 #endif 164 ncr_sc->sc_min_dma_len = MIN_DMA_LEN; 165 166 /* 167 * Fill in the adapter. 168 */ 169 ncr_sc->sc_adapter.scsipi_cmd = ncr5380_scsi_cmd; 170 ncr_sc->sc_adapter.scsipi_minphys = si_minphys; 171 172 /* 173 * Fill in the prototype scsi_link. 174 */ 175 ncr_sc->sc_link.scsipi_scsi.channel = SCSI_CHANNEL_ONLY_ONE; 176 ncr_sc->sc_link.adapter_softc = sc; 177 ncr_sc->sc_link.scsipi_scsi.adapter_target = 7; 178 ncr_sc->sc_link.adapter = &ncr_sc->sc_adapter; 179 ncr_sc->sc_link.device = &si_dev; 180 ncr_sc->sc_link.type = BUS_SCSI; 181 182 #ifdef DEBUG 183 if (si_debug) 184 printf("si: Set TheSoftC=%p TheRegs=%p\n", sc, regs); 185 ncr_sc->sc_link.flags |= si_link_flags; 186 #endif 187 188 /* 189 * Initialize fields used by the MI code 190 */ 191 ncr_sc->sci_r0 = ®s->sci.sci_r0; 192 ncr_sc->sci_r1 = ®s->sci.sci_r1; 193 ncr_sc->sci_r2 = ®s->sci.sci_r2; 194 ncr_sc->sci_r3 = ®s->sci.sci_r3; 195 ncr_sc->sci_r4 = ®s->sci.sci_r4; 196 ncr_sc->sci_r5 = ®s->sci.sci_r5; 197 ncr_sc->sci_r6 = ®s->sci.sci_r6; 198 ncr_sc->sci_r7 = ®s->sci.sci_r7; 199 200 /* 201 * Allocate DMA handles. 202 */ 203 i = SCI_OPENINGS * sizeof(struct si_dma_handle); 204 sc->sc_dma = (struct si_dma_handle *) 205 malloc(i, M_DEVBUF, M_WAITOK); 206 if (sc->sc_dma == NULL) 207 panic("si: dvma_malloc failed\n"); 208 for (i = 0; i < SCI_OPENINGS; i++) 209 sc->sc_dma[i].dh_flags = 0; 210 211 /* 212 * Initialize si board itself. 213 */ 214 ncr5380_init(ncr_sc); 215 ncr5380_reset_scsibus(ncr_sc); 216 config_found(&(ncr_sc->sc_dev), &(ncr_sc->sc_link), scsiprint); 217 } 218 219 static void 220 si_minphys(struct buf *bp) 221 { 222 if (bp->b_bcount > MAX_DMA_LEN) { 223 #ifdef DEBUG 224 if (si_debug) { 225 printf("si_minphys len = 0x%lx.\n", bp->b_bcount); 226 #ifdef DDB 227 Debugger(); 228 #endif 229 } 230 #endif 231 bp->b_bcount = MAX_DMA_LEN; 232 } 233 return (minphys(bp)); 234 } 235 236 237 #define CSR_WANT (SI_CSR_SBC_IP | SI_CSR_DMA_IP | \ 238 SI_CSR_DMA_CONFLICT | SI_CSR_DMA_BUS_ERR ) 239 240 int 241 si_intr(void *arg) 242 { 243 struct si_softc *sc = arg; 244 volatile struct si_regs *si = sc->sc_regs; 245 int dma_error, claimed; 246 u_short csr; 247 248 claimed = 0; 249 dma_error = 0; 250 251 /* SBC interrupt? DMA interrupt? */ 252 csr = si->si_csr; 253 NCR_TRACE("si_intr: csr=0x%x\n", csr); 254 255 if (csr & SI_CSR_DMA_CONFLICT) { 256 dma_error |= SI_CSR_DMA_CONFLICT; 257 printf("si_intr: DMA conflict\n"); 258 } 259 if (csr & SI_CSR_DMA_BUS_ERR) { 260 dma_error |= SI_CSR_DMA_BUS_ERR; 261 printf("si_intr: DMA bus error\n"); 262 } 263 if (dma_error) { 264 if (sc->ncr_sc.sc_state & NCR_DOINGDMA) 265 sc->ncr_sc.sc_state |= NCR_ABORTING; 266 /* Make sure we will call the main isr. */ 267 csr |= SI_CSR_DMA_IP; 268 } 269 270 if (csr & (SI_CSR_SBC_IP | SI_CSR_DMA_IP)) { 271 claimed = ncr5380_intr(&sc->ncr_sc); 272 #ifdef DEBUG 273 if (!claimed) { 274 printf("si_intr: spurious from SBC\n"); 275 #ifdef DDB 276 if (si_debug & 4) 277 Debugger(); /* XXX */ 278 #endif 279 } 280 #endif 281 /* Yes, we DID cause this interrupt. */ 282 claimed = 1; 283 } 284 285 return (claimed); 286 } 287 288 289 /***************************************************************** 290 * Common functions for DMA 291 ****************************************************************/ 292 293 /* 294 * Allocate a DMA handle and put it in sc->sc_dma. Prepare 295 * for DMA transfer. On the Sun3, this means mapping the buffer 296 * into DVMA space. dvma_mapin() flushes the cache for us. 297 */ 298 void 299 si_dma_alloc(ncr_sc) 300 struct ncr5380_softc *ncr_sc; 301 { 302 struct si_softc *sc = (struct si_softc *)ncr_sc; 303 struct sci_req *sr = ncr_sc->sc_current; 304 struct scsipi_xfer *xs = sr->sr_xs; 305 struct si_dma_handle *dh; 306 int i, xlen; 307 u_long addr; 308 309 #ifdef DIAGNOSTIC 310 if (sr->sr_dma_hand != NULL) 311 panic("si_dma_alloc: already have DMA handle"); 312 #endif 313 314 addr = (u_long) ncr_sc->sc_dataptr; 315 xlen = ncr_sc->sc_datalen; 316 317 /* If the DMA start addr is misaligned then do PIO */ 318 if ((addr & 1) || (xlen & 1)) { 319 printf("si_dma_alloc: misaligned.\n"); 320 return; 321 } 322 323 /* Make sure our caller checked sc_min_dma_len. */ 324 if (xlen < MIN_DMA_LEN) 325 panic("si_dma_alloc: xlen=0x%x\n", xlen); 326 327 /* 328 * Never attempt single transfers of more than 63k, because 329 * our count register may be only 16 bits (an OBIO adapter). 330 * This should never happen since already bounded by minphys(). 331 * XXX - Should just segment these... 332 */ 333 if (xlen > MAX_DMA_LEN) { 334 printf("si_dma_alloc: excessive xlen=0x%x\n", xlen); 335 #ifdef DDB 336 Debugger(); 337 #endif 338 ncr_sc->sc_datalen = xlen = MAX_DMA_LEN; 339 } 340 341 /* Find free DMA handle. Guaranteed to find one since we have 342 as many DMA handles as the driver has processes. */ 343 for (i = 0; i < SCI_OPENINGS; i++) { 344 if ((sc->sc_dma[i].dh_flags & SIDH_BUSY) == 0) 345 goto found; 346 } 347 panic("si: no free DMA handles."); 348 found: 349 350 dh = &sc->sc_dma[i]; 351 dh->dh_flags = SIDH_BUSY; 352 dh->dh_addr = (u_char*) addr; 353 dh->dh_maplen = xlen; 354 dh->dh_dvma = 0; 355 356 /* Copy the "write" flag for convenience. */ 357 if (xs->xs_control & XS_CTL_DATA_OUT) 358 dh->dh_flags |= SIDH_OUT; 359 360 #if 0 361 /* 362 * Some machines might not need to remap B_PHYS buffers. 363 * The sun3 does not map B_PHYS buffers into DVMA space, 364 * (they are mapped into normal KV space) so on the sun3 365 * we must always remap to a DVMA address here. Re-map is 366 * cheap anyway, because it's done by segments, not pages. 367 */ 368 if (xs->bp && (xs->bp->b_flags & B_PHYS)) 369 dh->dh_flags |= SIDH_PHYS; 370 #endif 371 372 dh->dh_dvma = dvma_mapin((char *)addr, xlen, 0); 373 if (!dh->dh_dvma) { 374 /* Can't remap segment */ 375 printf("si_dma_alloc: can't remap %p/0x%x\n", 376 dh->dh_addr, dh->dh_maplen); 377 dh->dh_flags = 0; 378 return; 379 } 380 381 /* success */ 382 sr->sr_dma_hand = dh; 383 384 return; 385 } 386 387 388 void 389 si_dma_free(ncr_sc) 390 struct ncr5380_softc *ncr_sc; 391 { 392 struct sci_req *sr = ncr_sc->sc_current; 393 struct si_dma_handle *dh = sr->sr_dma_hand; 394 395 #ifdef DIAGNOSTIC 396 if (dh == NULL) 397 panic("si_dma_free: no DMA handle"); 398 #endif 399 400 if (ncr_sc->sc_state & NCR_DOINGDMA) 401 panic("si_dma_free: free while in progress"); 402 403 if (dh->dh_flags & SIDH_BUSY) { 404 /* XXX - Should separate allocation and mapping. */ 405 /* Give back the DVMA space. */ 406 dvma_mapout(dh->dh_dvma, dh->dh_maplen); 407 dh->dh_dvma = 0; 408 dh->dh_flags = 0; 409 } 410 sr->sr_dma_hand = NULL; 411 } 412 413 414 #define CSR_MASK (SI_CSR_SBC_IP | SI_CSR_DMA_IP | \ 415 SI_CSR_DMA_CONFLICT | SI_CSR_DMA_BUS_ERR) 416 #define POLL_TIMO 50000 /* X100 = 5 sec. */ 417 418 /* 419 * Poll (spin-wait) for DMA completion. 420 * Called right after xx_dma_start(), and 421 * xx_dma_stop() will be called next. 422 * Same for either VME or OBIO. 423 */ 424 void 425 si_dma_poll(ncr_sc) 426 struct ncr5380_softc *ncr_sc; 427 { 428 struct si_softc *sc = (struct si_softc *)ncr_sc; 429 struct sci_req *sr = ncr_sc->sc_current; 430 volatile struct si_regs *si = sc->sc_regs; 431 int tmo; 432 433 /* Make sure DMA started successfully. */ 434 if (ncr_sc->sc_state & NCR_ABORTING) 435 return; 436 437 /* 438 * XXX: The Sun driver waits for ~SI_CSR_DMA_ACTIVE here 439 * XXX: (on obio) or even worse (on vme) a 10mS. delay! 440 * XXX: I really doubt that is necessary... 441 */ 442 443 /* Wait for any "dma complete" or error bits. */ 444 tmo = POLL_TIMO; 445 for (;;) { 446 if (si->si_csr & CSR_MASK) 447 break; 448 if (--tmo <= 0) { 449 printf("si: DMA timeout (while polling)\n"); 450 /* Indicate timeout as MI code would. */ 451 sr->sr_flags |= SR_OVERDUE; 452 break; 453 } 454 delay(100); 455 } 456 NCR_TRACE("si_dma_poll: waited %d\n", 457 POLL_TIMO - tmo); 458 459 #ifdef DEBUG 460 if (si_debug & 2) { 461 printf("si_dma_poll: done, csr=0x%x\n", si->si_csr); 462 } 463 #endif 464 } 465
Indexes created Mon Oct 13 16:09:52 GMT 2025