si.c revision 1.46
1 /* $NetBSD: si.c,v 1.46 1999/11/22 18:34:00 jdolecek Exp $ */ 2 3 /*- 4 * Copyright (c) 1996 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Adam Glass, David Jones, and Gordon W. Ross. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 /* 40 * This file contains only the machine-dependent parts of the 41 * Sun3 SCSI driver. (Autoconfig stuff and DMA functions.) 42 * The machine-independent parts are in ncr5380sbc.c 43 * 44 * Supported hardware includes: 45 * Sun SCSI-3 on OBIO (Sun3/50,Sun3/60) 46 * Sun SCSI-3 on VME (Sun3/160,Sun3/260) 47 * 48 * Could be made to support the Sun3/E if someone wanted to. 49 * 50 * Note: Both supported variants of the Sun SCSI-3 adapter have 51 * some really unusual "features" for this driver to deal with, 52 * generally related to the DMA engine. The OBIO variant will 53 * ignore any attempt to write the FIFO count register while the 54 * SCSI bus is in DATA_IN or DATA_OUT phase. This is dealt with 55 * by setting the FIFO count early in COMMAND or MSG_IN phase. 56 * 57 * The VME variant has a bit to enable or disable the DMA engine, 58 * but that bit also gates the interrupt line from the NCR5380! 59 * Therefore, in order to get any interrupt from the 5380, (i.e. 60 * for reselect) one must clear the DMA engine transfer count and 61 * then enable DMA. This has the further complication that you 62 * CAN NOT touch the NCR5380 while the DMA enable bit is set, so 63 * we have to turn DMA back off before we even look at the 5380. 64 * 65 * What wonderfully whacky hardware this is! 66 * 67 * Credits, history: 68 * 69 * David Jones wrote the initial version of this module, which 70 * included support for the VME adapter only. (no reselection). 71 * 72 * Gordon Ross added support for the OBIO adapter, and re-worked 73 * both the VME and OBIO code to support disconnect/reselect. 74 * (Required figuring out the hardware "features" noted above.) 75 * 76 * The autoconfiguration boilerplate came from Adam Glass. 77 */ 78 79 #include <sys/param.h> 80 #include <sys/systm.h> 81 #include <sys/errno.h> 82 #include <sys/kernel.h> 83 #include <sys/malloc.h> 84 #include <sys/device.h> 85 #include <sys/buf.h> 86 #include <sys/proc.h> 87 #include <sys/user.h> 88 89 #include <dev/scsipi/scsi_all.h> 90 #include <dev/scsipi/scsipi_all.h> 91 #include <dev/scsipi/scsipi_debug.h> 92 #include <dev/scsipi/scsiconf.h> 93 94 #include <machine/autoconf.h> 95 #include <machine/dvma.h> 96 97 /* #define DEBUG XXX */ 98 99 #include <dev/ic/ncr5380reg.h> 100 #include <dev/ic/ncr5380var.h> 101 102 #include "sireg.h" 103 #include "sivar.h" 104 105 /* 106 * Transfers smaller than this are done using PIO 107 * (on assumption they're not worth DMA overhead) 108 */ 109 #define MIN_DMA_LEN 128 110 111 int si_debug = 0; 112 #ifdef DEBUG 113 static int si_link_flags = 0 /* | SDEV_DB2 */ ; 114 #endif 115 116 /* How long to wait for DMA before declaring an error. */ 117 int si_dma_intr_timo = 500; /* ticks (sec. X 100) */ 118 119 static void si_minphys __P((struct buf *)); 120 121 /* This is copied from julian's bt driver */ 122 /* "so we have a default dev struct for our link struct." */ 123 static struct scsipi_device si_dev = { 124 NULL, /* Use default error handler. */ 125 NULL, /* Use default start handler. */ 126 NULL, /* Use default async handler. */ 127 NULL, /* Use default "done" routine. */ 128 }; 129 130 /* 131 * New-style autoconfig attachment. The cfattach 132 * structures are in si_obio.c and si_vme.c 133 */ 134 135 void 136 si_attach(sc) 137 struct si_softc *sc; 138 { 139 struct ncr5380_softc *ncr_sc = (void *)sc; 140 volatile struct si_regs *regs = sc->sc_regs; 141 int i; 142 143 /* 144 * Support the "options" (config file flags). 145 * Disconnect/reselect is a per-target mask. 146 * Interrupts and DMA are per-controller. 147 */ 148 ncr_sc->sc_no_disconnect = 149 (sc->sc_options & SI_NO_DISCONNECT); 150 ncr_sc->sc_parity_disable = 151 (sc->sc_options & SI_NO_PARITY_CHK) >> 8; 152 if (sc->sc_options & SI_FORCE_POLLING) 153 ncr_sc->sc_flags |= NCR5380_FORCE_POLLING; 154 155 #if 1 /* XXX - Temporary */ 156 /* XXX - In case we think DMA is completely broken... */ 157 if (sc->sc_options & SI_DISABLE_DMA) { 158 /* Override this function pointer. */ 159 ncr_sc->sc_dma_alloc = NULL; 160 } 161 #endif 162 ncr_sc->sc_min_dma_len = MIN_DMA_LEN; 163 164 /* 165 * Fill in the adapter. 166 */ 167 ncr_sc->sc_adapter.scsipi_cmd = ncr5380_scsi_cmd; 168 ncr_sc->sc_adapter.scsipi_minphys = si_minphys; 169 170 /* 171 * Fill in the prototype scsi_link. 172 */ 173 ncr_sc->sc_link.scsipi_scsi.channel = SCSI_CHANNEL_ONLY_ONE; 174 ncr_sc->sc_link.adapter_softc = sc; 175 ncr_sc->sc_link.scsipi_scsi.adapter_target = 7; 176 ncr_sc->sc_link.adapter = &ncr_sc->sc_adapter; 177 ncr_sc->sc_link.device = &si_dev; 178 ncr_sc->sc_link.type = BUS_SCSI; 179 180 #ifdef DEBUG 181 if (si_debug) 182 printf("si: Set TheSoftC=%p TheRegs=%p\n", sc, regs); 183 ncr_sc->sc_link.flags |= si_link_flags; 184 #endif 185 186 /* 187 * Initialize fields used by the MI code 188 */ 189 ncr_sc->sci_r0 = ®s->sci.sci_r0; 190 ncr_sc->sci_r1 = ®s->sci.sci_r1; 191 ncr_sc->sci_r2 = ®s->sci.sci_r2; 192 ncr_sc->sci_r3 = ®s->sci.sci_r3; 193 ncr_sc->sci_r4 = ®s->sci.sci_r4; 194 ncr_sc->sci_r5 = ®s->sci.sci_r5; 195 ncr_sc->sci_r6 = ®s->sci.sci_r6; 196 ncr_sc->sci_r7 = ®s->sci.sci_r7; 197 198 /* 199 * Allocate DMA handles. 200 */ 201 i = SCI_OPENINGS * sizeof(struct si_dma_handle); 202 sc->sc_dma = (struct si_dma_handle *) 203 malloc(i, M_DEVBUF, M_WAITOK); 204 if (sc->sc_dma == NULL) 205 panic("si: dvma_malloc failed\n"); 206 for (i = 0; i < SCI_OPENINGS; i++) 207 sc->sc_dma[i].dh_flags = 0; 208 209 /* 210 * Initialize si board itself. 211 */ 212 ncr5380_init(ncr_sc); 213 ncr5380_reset_scsibus(ncr_sc); 214 config_found(&(ncr_sc->sc_dev), &(ncr_sc->sc_link), scsiprint); 215 } 216 217 static void 218 si_minphys(struct buf *bp) 219 { 220 if (bp->b_bcount > MAX_DMA_LEN) { 221 #ifdef DEBUG 222 if (si_debug) { 223 printf("si_minphys len = 0x%lx.\n", bp->b_bcount); 224 Debugger(); 225 } 226 #endif 227 bp->b_bcount = MAX_DMA_LEN; 228 } 229 return (minphys(bp)); 230 } 231 232 233 #define CSR_WANT (SI_CSR_SBC_IP | SI_CSR_DMA_IP | \ 234 SI_CSR_DMA_CONFLICT | SI_CSR_DMA_BUS_ERR ) 235 236 int 237 si_intr(void *arg) 238 { 239 struct si_softc *sc = arg; 240 volatile struct si_regs *si = sc->sc_regs; 241 int dma_error, claimed; 242 u_short csr; 243 244 claimed = 0; 245 dma_error = 0; 246 247 /* SBC interrupt? DMA interrupt? */ 248 csr = si->si_csr; 249 NCR_TRACE("si_intr: csr=0x%x\n", csr); 250 251 if (csr & SI_CSR_DMA_CONFLICT) { 252 dma_error |= SI_CSR_DMA_CONFLICT; 253 printf("si_intr: DMA conflict\n"); 254 } 255 if (csr & SI_CSR_DMA_BUS_ERR) { 256 dma_error |= SI_CSR_DMA_BUS_ERR; 257 printf("si_intr: DMA bus error\n"); 258 } 259 if (dma_error) { 260 if (sc->ncr_sc.sc_state & NCR_DOINGDMA) 261 sc->ncr_sc.sc_state |= NCR_ABORTING; 262 /* Make sure we will call the main isr. */ 263 csr |= SI_CSR_DMA_IP; 264 } 265 266 if (csr & (SI_CSR_SBC_IP | SI_CSR_DMA_IP)) { 267 claimed = ncr5380_intr(&sc->ncr_sc); 268 #ifdef DEBUG 269 if (!claimed) { 270 printf("si_intr: spurious from SBC\n"); 271 if (si_debug & 4) 272 Debugger(); /* XXX */ 273 } 274 #endif 275 /* Yes, we DID cause this interrupt. */ 276 claimed = 1; 277 } 278 279 return (claimed); 280 } 281 282 283 /***************************************************************** 284 * Common functions for DMA 285 ****************************************************************/ 286 287 /* 288 * Allocate a DMA handle and put it in sc->sc_dma. Prepare 289 * for DMA transfer. On the Sun3, this means mapping the buffer 290 * into DVMA space. dvma_mapin() flushes the cache for us. 291 */ 292 void 293 si_dma_alloc(ncr_sc) 294 struct ncr5380_softc *ncr_sc; 295 { 296 struct si_softc *sc = (struct si_softc *)ncr_sc; 297 struct sci_req *sr = ncr_sc->sc_current; 298 struct scsipi_xfer *xs = sr->sr_xs; 299 struct si_dma_handle *dh; 300 int i, xlen; 301 u_long addr; 302 303 #ifdef DIAGNOSTIC 304 if (sr->sr_dma_hand != NULL) 305 panic("si_dma_alloc: already have DMA handle"); 306 #endif 307 308 addr = (u_long) ncr_sc->sc_dataptr; 309 xlen = ncr_sc->sc_datalen; 310 311 /* If the DMA start addr is misaligned then do PIO */ 312 if ((addr & 1) || (xlen & 1)) { 313 printf("si_dma_alloc: misaligned.\n"); 314 return; 315 } 316 317 /* Make sure our caller checked sc_min_dma_len. */ 318 if (xlen < MIN_DMA_LEN) 319 panic("si_dma_alloc: xlen=0x%x\n", xlen); 320 321 /* 322 * Never attempt single transfers of more than 63k, because 323 * our count register may be only 16 bits (an OBIO adapter). 324 * This should never happen since already bounded by minphys(). 325 * XXX - Should just segment these... 326 */ 327 if (xlen > MAX_DMA_LEN) { 328 printf("si_dma_alloc: excessive xlen=0x%x\n", xlen); 329 Debugger(); 330 ncr_sc->sc_datalen = xlen = MAX_DMA_LEN; 331 } 332 333 /* Find free DMA handle. Guaranteed to find one since we have 334 as many DMA handles as the driver has processes. */ 335 for (i = 0; i < SCI_OPENINGS; i++) { 336 if ((sc->sc_dma[i].dh_flags & SIDH_BUSY) == 0) 337 goto found; 338 } 339 panic("si: no free DMA handles."); 340 found: 341 342 dh = &sc->sc_dma[i]; 343 dh->dh_flags = SIDH_BUSY; 344 dh->dh_addr = (u_char*) addr; 345 dh->dh_maplen = xlen; 346 dh->dh_dvma = 0; 347 348 /* Copy the "write" flag for convenience. */ 349 if (xs->xs_control & XS_CTL_DATA_OUT) 350 dh->dh_flags |= SIDH_OUT; 351 352 #if 0 353 /* 354 * Some machines might not need to remap B_PHYS buffers. 355 * The sun3 does not map B_PHYS buffers into DVMA space, 356 * (they are mapped into normal KV space) so on the sun3 357 * we must always remap to a DVMA address here. Re-map is 358 * cheap anyway, because it's done by segments, not pages. 359 */ 360 if (xs->bp && (xs->bp->b_flags & B_PHYS)) 361 dh->dh_flags |= SIDH_PHYS; 362 #endif 363 364 dh->dh_dvma = dvma_mapin((char *)addr, xlen, 0); 365 if (!dh->dh_dvma) { 366 /* Can't remap segment */ 367 printf("si_dma_alloc: can't remap %p/0x%x\n", 368 dh->dh_addr, dh->dh_maplen); 369 dh->dh_flags = 0; 370 return; 371 } 372 373 /* success */ 374 sr->sr_dma_hand = dh; 375 376 return; 377 } 378 379 380 void 381 si_dma_free(ncr_sc) 382 struct ncr5380_softc *ncr_sc; 383 { 384 struct sci_req *sr = ncr_sc->sc_current; 385 struct si_dma_handle *dh = sr->sr_dma_hand; 386 387 #ifdef DIAGNOSTIC 388 if (dh == NULL) 389 panic("si_dma_free: no DMA handle"); 390 #endif 391 392 if (ncr_sc->sc_state & NCR_DOINGDMA) 393 panic("si_dma_free: free while in progress"); 394 395 if (dh->dh_flags & SIDH_BUSY) { 396 /* XXX - Should separate allocation and mapping. */ 397 /* Give back the DVMA space. */ 398 dvma_mapout(dh->dh_dvma, dh->dh_maplen); 399 dh->dh_dvma = 0; 400 dh->dh_flags = 0; 401 } 402 sr->sr_dma_hand = NULL; 403 } 404 405 406 #define CSR_MASK (SI_CSR_SBC_IP | SI_CSR_DMA_IP | \ 407 SI_CSR_DMA_CONFLICT | SI_CSR_DMA_BUS_ERR) 408 #define POLL_TIMO 50000 /* X100 = 5 sec. */ 409 410 /* 411 * Poll (spin-wait) for DMA completion. 412 * Called right after xx_dma_start(), and 413 * xx_dma_stop() will be called next. 414 * Same for either VME or OBIO. 415 */ 416 void 417 si_dma_poll(ncr_sc) 418 struct ncr5380_softc *ncr_sc; 419 { 420 struct si_softc *sc = (struct si_softc *)ncr_sc; 421 struct sci_req *sr = ncr_sc->sc_current; 422 volatile struct si_regs *si = sc->sc_regs; 423 int tmo; 424 425 /* Make sure DMA started successfully. */ 426 if (ncr_sc->sc_state & NCR_ABORTING) 427 return; 428 429 /* 430 * XXX: The Sun driver waits for ~SI_CSR_DMA_ACTIVE here 431 * XXX: (on obio) or even worse (on vme) a 10mS. delay! 432 * XXX: I really doubt that is necessary... 433 */ 434 435 /* Wait for any "dma complete" or error bits. */ 436 tmo = POLL_TIMO; 437 for (;;) { 438 if (si->si_csr & CSR_MASK) 439 break; 440 if (--tmo <= 0) { 441 printf("si: DMA timeout (while polling)\n"); 442 /* Indicate timeout as MI code would. */ 443 sr->sr_flags |= SR_OVERDUE; 444 break; 445 } 446 delay(100); 447 } 448 NCR_TRACE("si_dma_poll: waited %d\n", 449 POLL_TIMO - tmo); 450 451 #ifdef DEBUG 452 if (si_debug & 2) { 453 printf("si_dma_poll: done, csr=0x%x\n", si->si_csr); 454 } 455 #endif 456 } 457
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