si.c revision 1.49
1 /* $NetBSD: si.c,v 1.49 2000/04/01 14:38:42 tsutsui Exp $ */ 2 3 /*- 4 * Copyright (c) 1996 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Adam Glass, David Jones, and Gordon W. Ross. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 /* 40 * This file contains only the machine-dependent parts of the 41 * Sun3 SCSI driver. (Autoconfig stuff and DMA functions.) 42 * The machine-independent parts are in ncr5380sbc.c 43 * 44 * Supported hardware includes: 45 * Sun SCSI-3 on OBIO (Sun3/50,Sun3/60) 46 * Sun SCSI-3 on VME (Sun3/160,Sun3/260) 47 * 48 * Could be made to support the Sun3/E if someone wanted to. 49 * 50 * Note: Both supported variants of the Sun SCSI-3 adapter have 51 * some really unusual "features" for this driver to deal with, 52 * generally related to the DMA engine. The OBIO variant will 53 * ignore any attempt to write the FIFO count register while the 54 * SCSI bus is in DATA_IN or DATA_OUT phase. This is dealt with 55 * by setting the FIFO count early in COMMAND or MSG_IN phase. 56 * 57 * The VME variant has a bit to enable or disable the DMA engine, 58 * but that bit also gates the interrupt line from the NCR5380! 59 * Therefore, in order to get any interrupt from the 5380, (i.e. 60 * for reselect) one must clear the DMA engine transfer count and 61 * then enable DMA. This has the further complication that you 62 * CAN NOT touch the NCR5380 while the DMA enable bit is set, so 63 * we have to turn DMA back off before we even look at the 5380. 64 * 65 * What wonderfully whacky hardware this is! 66 * 67 * Credits, history: 68 * 69 * David Jones wrote the initial version of this module, which 70 * included support for the VME adapter only. (no reselection). 71 * 72 * Gordon Ross added support for the OBIO adapter, and re-worked 73 * both the VME and OBIO code to support disconnect/reselect. 74 * (Required figuring out the hardware "features" noted above.) 75 * 76 * The autoconfiguration boilerplate came from Adam Glass. 77 */ 78 79 #include <sys/param.h> 80 #include <sys/systm.h> 81 #include <sys/errno.h> 82 #include <sys/kernel.h> 83 #include <sys/malloc.h> 84 #include <sys/device.h> 85 #include <sys/buf.h> 86 #include <sys/proc.h> 87 #include <sys/user.h> 88 89 #include <dev/scsipi/scsi_all.h> 90 #include <dev/scsipi/scsipi_all.h> 91 #include <dev/scsipi/scsipi_debug.h> 92 #include <dev/scsipi/scsiconf.h> 93 94 #include <machine/autoconf.h> 95 #include <machine/dvma.h> 96 97 /* #define DEBUG XXX */ 98 99 #include <dev/ic/ncr5380reg.h> 100 #include <dev/ic/ncr5380var.h> 101 102 #include "sireg.h" 103 #include "sivar.h" 104 105 /* 106 * Transfers smaller than this are done using PIO 107 * (on assumption they're not worth DMA overhead) 108 */ 109 #define MIN_DMA_LEN 128 110 111 int si_debug = 0; 112 #ifdef DEBUG 113 static int si_link_flags = 0 /* | SDEV_DB2 */ ; 114 #endif 115 116 /* How long to wait for DMA before declaring an error. */ 117 int si_dma_intr_timo = 500; /* ticks (sec. X 100) */ 118 119 static void si_minphys __P((struct buf *)); 120 121 /* 122 * New-style autoconfig attachment. The cfattach 123 * structures are in si_obio.c and si_vme.c 124 */ 125 126 void 127 si_attach(sc) 128 struct si_softc *sc; 129 { 130 struct ncr5380_softc *ncr_sc = (void *)sc; 131 volatile struct si_regs *regs = sc->sc_regs; 132 int i; 133 134 /* 135 * Support the "options" (config file flags). 136 * Disconnect/reselect is a per-target mask. 137 * Interrupts and DMA are per-controller. 138 */ 139 ncr_sc->sc_no_disconnect = 140 (sc->sc_options & SI_NO_DISCONNECT); 141 ncr_sc->sc_parity_disable = 142 (sc->sc_options & SI_NO_PARITY_CHK) >> 8; 143 if (sc->sc_options & SI_FORCE_POLLING) 144 ncr_sc->sc_flags |= NCR5380_FORCE_POLLING; 145 146 #if 1 /* XXX - Temporary */ 147 /* XXX - In case we think DMA is completely broken... */ 148 if (sc->sc_options & SI_DISABLE_DMA) { 149 /* Override this function pointer. */ 150 ncr_sc->sc_dma_alloc = NULL; 151 } 152 #endif 153 ncr_sc->sc_min_dma_len = MIN_DMA_LEN; 154 155 #ifdef DEBUG 156 if (si_debug) 157 printf("si: Set TheSoftC=%p TheRegs=%p\n", sc, regs); 158 ncr_sc->sc_link.flags |= si_link_flags; 159 #endif 160 161 /* 162 * Initialize fields used by the MI code 163 */ 164 ncr_sc->sci_r0 = ®s->sci.sci_r0; 165 ncr_sc->sci_r1 = ®s->sci.sci_r1; 166 ncr_sc->sci_r2 = ®s->sci.sci_r2; 167 ncr_sc->sci_r3 = ®s->sci.sci_r3; 168 ncr_sc->sci_r4 = ®s->sci.sci_r4; 169 ncr_sc->sci_r5 = ®s->sci.sci_r5; 170 ncr_sc->sci_r6 = ®s->sci.sci_r6; 171 ncr_sc->sci_r7 = ®s->sci.sci_r7; 172 173 ncr_sc->sc_rev = NCR_VARIANT_NCR5380; 174 175 /* 176 * Allocate DMA handles. 177 */ 178 i = SCI_OPENINGS * sizeof(struct si_dma_handle); 179 sc->sc_dma = (struct si_dma_handle *) 180 malloc(i, M_DEVBUF, M_WAITOK); 181 if (sc->sc_dma == NULL) 182 panic("si: dvma_malloc failed\n"); 183 for (i = 0; i < SCI_OPENINGS; i++) 184 sc->sc_dma[i].dh_flags = 0; 185 186 ncr_sc->sc_link.scsipi_scsi.adapter_target = 7; 187 ncr_sc->sc_adapter.scsipi_minphys = si_minphys; 188 189 /* 190 * Initialize si board itself. 191 */ 192 ncr5380_attach(ncr_sc); 193 194 } 195 196 static void 197 si_minphys(struct buf *bp) 198 { 199 if (bp->b_bcount > MAX_DMA_LEN) { 200 #ifdef DEBUG 201 if (si_debug) { 202 printf("si_minphys len = 0x%lx.\n", bp->b_bcount); 203 Debugger(); 204 } 205 #endif 206 bp->b_bcount = MAX_DMA_LEN; 207 } 208 return (minphys(bp)); 209 } 210 211 212 #define CSR_WANT (SI_CSR_SBC_IP | SI_CSR_DMA_IP | \ 213 SI_CSR_DMA_CONFLICT | SI_CSR_DMA_BUS_ERR ) 214 215 int 216 si_intr(void *arg) 217 { 218 struct si_softc *sc = arg; 219 volatile struct si_regs *si = sc->sc_regs; 220 int dma_error, claimed; 221 u_short csr; 222 223 claimed = 0; 224 dma_error = 0; 225 226 /* SBC interrupt? DMA interrupt? */ 227 csr = si->si_csr; 228 NCR_TRACE("si_intr: csr=0x%x\n", csr); 229 230 if (csr & SI_CSR_DMA_CONFLICT) { 231 dma_error |= SI_CSR_DMA_CONFLICT; 232 printf("si_intr: DMA conflict\n"); 233 } 234 if (csr & SI_CSR_DMA_BUS_ERR) { 235 dma_error |= SI_CSR_DMA_BUS_ERR; 236 printf("si_intr: DMA bus error\n"); 237 } 238 if (dma_error) { 239 if (sc->ncr_sc.sc_state & NCR_DOINGDMA) 240 sc->ncr_sc.sc_state |= NCR_ABORTING; 241 /* Make sure we will call the main isr. */ 242 csr |= SI_CSR_DMA_IP; 243 } 244 245 if (csr & (SI_CSR_SBC_IP | SI_CSR_DMA_IP)) { 246 claimed = ncr5380_intr(&sc->ncr_sc); 247 #ifdef DEBUG 248 if (!claimed) { 249 printf("si_intr: spurious from SBC\n"); 250 if (si_debug & 4) 251 Debugger(); /* XXX */ 252 } 253 #endif 254 /* Yes, we DID cause this interrupt. */ 255 claimed = 1; 256 } 257 258 return (claimed); 259 } 260 261 262 /***************************************************************** 263 * Common functions for DMA 264 ****************************************************************/ 265 266 /* 267 * Allocate a DMA handle and put it in sc->sc_dma. Prepare 268 * for DMA transfer. On the Sun3, this means mapping the buffer 269 * into DVMA space. dvma_mapin() flushes the cache for us. 270 */ 271 void 272 si_dma_alloc(ncr_sc) 273 struct ncr5380_softc *ncr_sc; 274 { 275 struct si_softc *sc = (struct si_softc *)ncr_sc; 276 struct sci_req *sr = ncr_sc->sc_current; 277 struct scsipi_xfer *xs = sr->sr_xs; 278 struct si_dma_handle *dh; 279 int i, xlen; 280 u_long addr; 281 282 #ifdef DIAGNOSTIC 283 if (sr->sr_dma_hand != NULL) 284 panic("si_dma_alloc: already have DMA handle"); 285 #endif 286 287 addr = (u_long) ncr_sc->sc_dataptr; 288 xlen = ncr_sc->sc_datalen; 289 290 /* If the DMA start addr is misaligned then do PIO */ 291 if ((addr & 1) || (xlen & 1)) { 292 printf("si_dma_alloc: misaligned.\n"); 293 return; 294 } 295 296 /* Make sure our caller checked sc_min_dma_len. */ 297 if (xlen < MIN_DMA_LEN) 298 panic("si_dma_alloc: xlen=0x%x\n", xlen); 299 300 /* 301 * Never attempt single transfers of more than 63k, because 302 * our count register may be only 16 bits (an OBIO adapter). 303 * This should never happen since already bounded by minphys(). 304 * XXX - Should just segment these... 305 */ 306 if (xlen > MAX_DMA_LEN) { 307 printf("si_dma_alloc: excessive xlen=0x%x\n", xlen); 308 Debugger(); 309 ncr_sc->sc_datalen = xlen = MAX_DMA_LEN; 310 } 311 312 /* Find free DMA handle. Guaranteed to find one since we have 313 as many DMA handles as the driver has processes. */ 314 for (i = 0; i < SCI_OPENINGS; i++) { 315 if ((sc->sc_dma[i].dh_flags & SIDH_BUSY) == 0) 316 goto found; 317 } 318 panic("si: no free DMA handles."); 319 found: 320 321 dh = &sc->sc_dma[i]; 322 dh->dh_flags = SIDH_BUSY; 323 dh->dh_addr = (u_char*) addr; 324 dh->dh_maplen = xlen; 325 dh->dh_dvma = 0; 326 327 /* Copy the "write" flag for convenience. */ 328 if (xs->xs_control & XS_CTL_DATA_OUT) 329 dh->dh_flags |= SIDH_OUT; 330 331 #if 0 332 /* 333 * Some machines might not need to remap B_PHYS buffers. 334 * The sun3 does not map B_PHYS buffers into DVMA space, 335 * (they are mapped into normal KV space) so on the sun3 336 * we must always remap to a DVMA address here. Re-map is 337 * cheap anyway, because it's done by segments, not pages. 338 */ 339 if (xs->bp && (xs->bp->b_flags & B_PHYS)) 340 dh->dh_flags |= SIDH_PHYS; 341 #endif 342 343 dh->dh_dvma = dvma_mapin((char *)addr, xlen, 0); 344 if (!dh->dh_dvma) { 345 /* Can't remap segment */ 346 printf("si_dma_alloc: can't remap %p/0x%x\n", 347 dh->dh_addr, dh->dh_maplen); 348 dh->dh_flags = 0; 349 return; 350 } 351 352 /* success */ 353 sr->sr_dma_hand = dh; 354 355 return; 356 } 357 358 359 void 360 si_dma_free(ncr_sc) 361 struct ncr5380_softc *ncr_sc; 362 { 363 struct sci_req *sr = ncr_sc->sc_current; 364 struct si_dma_handle *dh = sr->sr_dma_hand; 365 366 #ifdef DIAGNOSTIC 367 if (dh == NULL) 368 panic("si_dma_free: no DMA handle"); 369 #endif 370 371 if (ncr_sc->sc_state & NCR_DOINGDMA) 372 panic("si_dma_free: free while in progress"); 373 374 if (dh->dh_flags & SIDH_BUSY) { 375 /* XXX - Should separate allocation and mapping. */ 376 /* Give back the DVMA space. */ 377 dvma_mapout(dh->dh_dvma, dh->dh_maplen); 378 dh->dh_dvma = 0; 379 dh->dh_flags = 0; 380 } 381 sr->sr_dma_hand = NULL; 382 } 383 384 385 #define CSR_MASK (SI_CSR_SBC_IP | SI_CSR_DMA_IP | \ 386 SI_CSR_DMA_CONFLICT | SI_CSR_DMA_BUS_ERR) 387 #define POLL_TIMO 50000 /* X100 = 5 sec. */ 388 389 /* 390 * Poll (spin-wait) for DMA completion. 391 * Called right after xx_dma_start(), and 392 * xx_dma_stop() will be called next. 393 * Same for either VME or OBIO. 394 */ 395 void 396 si_dma_poll(ncr_sc) 397 struct ncr5380_softc *ncr_sc; 398 { 399 struct si_softc *sc = (struct si_softc *)ncr_sc; 400 struct sci_req *sr = ncr_sc->sc_current; 401 volatile struct si_regs *si = sc->sc_regs; 402 int tmo; 403 404 /* Make sure DMA started successfully. */ 405 if (ncr_sc->sc_state & NCR_ABORTING) 406 return; 407 408 /* 409 * XXX: The Sun driver waits for ~SI_CSR_DMA_ACTIVE here 410 * XXX: (on obio) or even worse (on vme) a 10mS. delay! 411 * XXX: I really doubt that is necessary... 412 */ 413 414 /* Wait for any "dma complete" or error bits. */ 415 tmo = POLL_TIMO; 416 for (;;) { 417 if (si->si_csr & CSR_MASK) 418 break; 419 if (--tmo <= 0) { 420 printf("si: DMA timeout (while polling)\n"); 421 /* Indicate timeout as MI code would. */ 422 sr->sr_flags |= SR_OVERDUE; 423 break; 424 } 425 delay(100); 426 } 427 NCR_TRACE("si_dma_poll: waited %d\n", 428 POLL_TIMO - tmo); 429 430 #ifdef DEBUG 431 if (si_debug & 2) { 432 printf("si_dma_poll: done, csr=0x%x\n", si->si_csr); 433 } 434 #endif 435 } 436
Indexes created Tue Oct 14 00:09:49 GMT 2025