si.c revision 1.49.6.1
1 /* $NetBSD: si.c,v 1.49.6.1 2001/06/21 19:37:01 nathanw Exp $ */ 2 3 /*- 4 * Copyright (c) 1996 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Adam Glass, David Jones, and Gordon W. Ross. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 /* 40 * This file contains only the machine-dependent parts of the 41 * Sun3 SCSI driver. (Autoconfig stuff and DMA functions.) 42 * The machine-independent parts are in ncr5380sbc.c 43 * 44 * Supported hardware includes: 45 * Sun SCSI-3 on OBIO (Sun3/50,Sun3/60) 46 * Sun SCSI-3 on VME (Sun3/160,Sun3/260) 47 * 48 * Could be made to support the Sun3/E if someone wanted to. 49 * 50 * Note: Both supported variants of the Sun SCSI-3 adapter have 51 * some really unusual "features" for this driver to deal with, 52 * generally related to the DMA engine. The OBIO variant will 53 * ignore any attempt to write the FIFO count register while the 54 * SCSI bus is in DATA_IN or DATA_OUT phase. This is dealt with 55 * by setting the FIFO count early in COMMAND or MSG_IN phase. 56 * 57 * The VME variant has a bit to enable or disable the DMA engine, 58 * but that bit also gates the interrupt line from the NCR5380! 59 * Therefore, in order to get any interrupt from the 5380, (i.e. 60 * for reselect) one must clear the DMA engine transfer count and 61 * then enable DMA. This has the further complication that you 62 * CAN NOT touch the NCR5380 while the DMA enable bit is set, so 63 * we have to turn DMA back off before we even look at the 5380. 64 * 65 * What wonderfully whacky hardware this is! 66 * 67 * Credits, history: 68 * 69 * David Jones wrote the initial version of this module, which 70 * included support for the VME adapter only. (no reselection). 71 * 72 * Gordon Ross added support for the OBIO adapter, and re-worked 73 * both the VME and OBIO code to support disconnect/reselect. 74 * (Required figuring out the hardware "features" noted above.) 75 * 76 * The autoconfiguration boilerplate came from Adam Glass. 77 */ 78 79 #include <sys/param.h> 80 #include <sys/systm.h> 81 #include <sys/errno.h> 82 #include <sys/kernel.h> 83 #include <sys/malloc.h> 84 #include <sys/device.h> 85 #include <sys/buf.h> 86 #include <sys/proc.h> 87 #include <sys/user.h> 88 89 #include <dev/scsipi/scsi_all.h> 90 #include <dev/scsipi/scsipi_all.h> 91 #include <dev/scsipi/scsipi_debug.h> 92 #include <dev/scsipi/scsiconf.h> 93 94 #include <machine/autoconf.h> 95 #include <machine/dvma.h> 96 97 /* #define DEBUG XXX */ 98 99 #include <dev/ic/ncr5380reg.h> 100 #include <dev/ic/ncr5380var.h> 101 102 #include "sireg.h" 103 #include "sivar.h" 104 105 /* 106 * Transfers smaller than this are done using PIO 107 * (on assumption they're not worth DMA overhead) 108 */ 109 #define MIN_DMA_LEN 128 110 111 int si_debug = 0; 112 #ifdef DEBUG 113 #endif 114 115 /* How long to wait for DMA before declaring an error. */ 116 int si_dma_intr_timo = 500; /* ticks (sec. X 100) */ 117 118 static void si_minphys __P((struct buf *)); 119 120 /* 121 * New-style autoconfig attachment. The cfattach 122 * structures are in si_obio.c and si_vme.c 123 */ 124 125 void 126 si_attach(sc) 127 struct si_softc *sc; 128 { 129 struct ncr5380_softc *ncr_sc = (void *)sc; 130 volatile struct si_regs *regs = sc->sc_regs; 131 int i; 132 133 /* 134 * Support the "options" (config file flags). 135 * Disconnect/reselect is a per-target mask. 136 * Interrupts and DMA are per-controller. 137 */ 138 ncr_sc->sc_no_disconnect = 139 (sc->sc_options & SI_NO_DISCONNECT); 140 ncr_sc->sc_parity_disable = 141 (sc->sc_options & SI_NO_PARITY_CHK) >> 8; 142 if (sc->sc_options & SI_FORCE_POLLING) 143 ncr_sc->sc_flags |= NCR5380_FORCE_POLLING; 144 145 #if 1 /* XXX - Temporary */ 146 /* XXX - In case we think DMA is completely broken... */ 147 if (sc->sc_options & SI_DISABLE_DMA) { 148 /* Override this function pointer. */ 149 ncr_sc->sc_dma_alloc = NULL; 150 } 151 #endif 152 ncr_sc->sc_min_dma_len = MIN_DMA_LEN; 153 154 /* 155 * Initialize fields used by the MI code 156 */ 157 ncr_sc->sci_r0 = ®s->sci.sci_r0; 158 ncr_sc->sci_r1 = ®s->sci.sci_r1; 159 ncr_sc->sci_r2 = ®s->sci.sci_r2; 160 ncr_sc->sci_r3 = ®s->sci.sci_r3; 161 ncr_sc->sci_r4 = ®s->sci.sci_r4; 162 ncr_sc->sci_r5 = ®s->sci.sci_r5; 163 ncr_sc->sci_r6 = ®s->sci.sci_r6; 164 ncr_sc->sci_r7 = ®s->sci.sci_r7; 165 166 ncr_sc->sc_rev = NCR_VARIANT_NCR5380; 167 168 /* 169 * Allocate DMA handles. 170 */ 171 i = SCI_OPENINGS * sizeof(struct si_dma_handle); 172 sc->sc_dma = (struct si_dma_handle *) 173 malloc(i, M_DEVBUF, M_WAITOK); 174 if (sc->sc_dma == NULL) 175 panic("si: dvma_malloc failed\n"); 176 for (i = 0; i < SCI_OPENINGS; i++) 177 sc->sc_dma[i].dh_flags = 0; 178 179 ncr_sc->sc_channel.chan_id = 7; 180 ncr_sc->sc_adapter.adapt_minphys = si_minphys; 181 182 /* 183 * Initialize si board itself. 184 */ 185 ncr5380_attach(ncr_sc); 186 187 } 188 189 static void 190 si_minphys(struct buf *bp) 191 { 192 if (bp->b_bcount > MAX_DMA_LEN) { 193 #ifdef DEBUG 194 if (si_debug) { 195 printf("si_minphys len = 0x%lx.\n", bp->b_bcount); 196 Debugger(); 197 } 198 #endif 199 bp->b_bcount = MAX_DMA_LEN; 200 } 201 return (minphys(bp)); 202 } 203 204 205 #define CSR_WANT (SI_CSR_SBC_IP | SI_CSR_DMA_IP | \ 206 SI_CSR_DMA_CONFLICT | SI_CSR_DMA_BUS_ERR ) 207 208 int 209 si_intr(void *arg) 210 { 211 struct si_softc *sc = arg; 212 volatile struct si_regs *si = sc->sc_regs; 213 int dma_error, claimed; 214 u_short csr; 215 216 claimed = 0; 217 dma_error = 0; 218 219 /* SBC interrupt? DMA interrupt? */ 220 csr = si->si_csr; 221 NCR_TRACE("si_intr: csr=0x%x\n", csr); 222 223 if (csr & SI_CSR_DMA_CONFLICT) { 224 dma_error |= SI_CSR_DMA_CONFLICT; 225 printf("si_intr: DMA conflict\n"); 226 } 227 if (csr & SI_CSR_DMA_BUS_ERR) { 228 dma_error |= SI_CSR_DMA_BUS_ERR; 229 printf("si_intr: DMA bus error\n"); 230 } 231 if (dma_error) { 232 if (sc->ncr_sc.sc_state & NCR_DOINGDMA) 233 sc->ncr_sc.sc_state |= NCR_ABORTING; 234 /* Make sure we will call the main isr. */ 235 csr |= SI_CSR_DMA_IP; 236 } 237 238 if (csr & (SI_CSR_SBC_IP | SI_CSR_DMA_IP)) { 239 claimed = ncr5380_intr(&sc->ncr_sc); 240 #ifdef DEBUG 241 if (!claimed) { 242 printf("si_intr: spurious from SBC\n"); 243 if (si_debug & 4) 244 Debugger(); /* XXX */ 245 } 246 #endif 247 /* Yes, we DID cause this interrupt. */ 248 claimed = 1; 249 } 250 251 return (claimed); 252 } 253 254 255 /***************************************************************** 256 * Common functions for DMA 257 ****************************************************************/ 258 259 /* 260 * Allocate a DMA handle and put it in sc->sc_dma. Prepare 261 * for DMA transfer. On the Sun3, this means mapping the buffer 262 * into DVMA space. dvma_mapin() flushes the cache for us. 263 */ 264 void 265 si_dma_alloc(ncr_sc) 266 struct ncr5380_softc *ncr_sc; 267 { 268 struct si_softc *sc = (struct si_softc *)ncr_sc; 269 struct sci_req *sr = ncr_sc->sc_current; 270 struct scsipi_xfer *xs = sr->sr_xs; 271 struct si_dma_handle *dh; 272 int i, xlen; 273 u_long addr; 274 275 #ifdef DIAGNOSTIC 276 if (sr->sr_dma_hand != NULL) 277 panic("si_dma_alloc: already have DMA handle"); 278 #endif 279 280 addr = (u_long) ncr_sc->sc_dataptr; 281 xlen = ncr_sc->sc_datalen; 282 283 /* If the DMA start addr is misaligned then do PIO */ 284 if ((addr & 1) || (xlen & 1)) { 285 printf("si_dma_alloc: misaligned.\n"); 286 return; 287 } 288 289 /* Make sure our caller checked sc_min_dma_len. */ 290 if (xlen < MIN_DMA_LEN) 291 panic("si_dma_alloc: xlen=0x%x\n", xlen); 292 293 /* 294 * Never attempt single transfers of more than 63k, because 295 * our count register may be only 16 bits (an OBIO adapter). 296 * This should never happen since already bounded by minphys(). 297 * XXX - Should just segment these... 298 */ 299 if (xlen > MAX_DMA_LEN) { 300 printf("si_dma_alloc: excessive xlen=0x%x\n", xlen); 301 Debugger(); 302 ncr_sc->sc_datalen = xlen = MAX_DMA_LEN; 303 } 304 305 /* Find free DMA handle. Guaranteed to find one since we have 306 as many DMA handles as the driver has processes. */ 307 for (i = 0; i < SCI_OPENINGS; i++) { 308 if ((sc->sc_dma[i].dh_flags & SIDH_BUSY) == 0) 309 goto found; 310 } 311 panic("si: no free DMA handles."); 312 found: 313 314 dh = &sc->sc_dma[i]; 315 dh->dh_flags = SIDH_BUSY; 316 dh->dh_addr = (u_char*) addr; 317 dh->dh_maplen = xlen; 318 dh->dh_dvma = 0; 319 320 /* Copy the "write" flag for convenience. */ 321 if (xs->xs_control & XS_CTL_DATA_OUT) 322 dh->dh_flags |= SIDH_OUT; 323 324 #if 0 325 /* 326 * Some machines might not need to remap B_PHYS buffers. 327 * The sun3 does not map B_PHYS buffers into DVMA space, 328 * (they are mapped into normal KV space) so on the sun3 329 * we must always remap to a DVMA address here. Re-map is 330 * cheap anyway, because it's done by segments, not pages. 331 */ 332 if (xs->bp && (xs->bp->b_flags & B_PHYS)) 333 dh->dh_flags |= SIDH_PHYS; 334 #endif 335 336 dh->dh_dvma = dvma_mapin((char *)addr, xlen, 0); 337 if (!dh->dh_dvma) { 338 /* Can't remap segment */ 339 printf("si_dma_alloc: can't remap %p/0x%x\n", 340 dh->dh_addr, dh->dh_maplen); 341 dh->dh_flags = 0; 342 return; 343 } 344 345 /* success */ 346 sr->sr_dma_hand = dh; 347 348 return; 349 } 350 351 352 void 353 si_dma_free(ncr_sc) 354 struct ncr5380_softc *ncr_sc; 355 { 356 struct sci_req *sr = ncr_sc->sc_current; 357 struct si_dma_handle *dh = sr->sr_dma_hand; 358 359 #ifdef DIAGNOSTIC 360 if (dh == NULL) 361 panic("si_dma_free: no DMA handle"); 362 #endif 363 364 if (ncr_sc->sc_state & NCR_DOINGDMA) 365 panic("si_dma_free: free while in progress"); 366 367 if (dh->dh_flags & SIDH_BUSY) { 368 /* XXX - Should separate allocation and mapping. */ 369 /* Give back the DVMA space. */ 370 dvma_mapout(dh->dh_dvma, dh->dh_maplen); 371 dh->dh_dvma = 0; 372 dh->dh_flags = 0; 373 } 374 sr->sr_dma_hand = NULL; 375 } 376 377 378 #define CSR_MASK (SI_CSR_SBC_IP | SI_CSR_DMA_IP | \ 379 SI_CSR_DMA_CONFLICT | SI_CSR_DMA_BUS_ERR) 380 #define POLL_TIMO 50000 /* X100 = 5 sec. */ 381 382 /* 383 * Poll (spin-wait) for DMA completion. 384 * Called right after xx_dma_start(), and 385 * xx_dma_stop() will be called next. 386 * Same for either VME or OBIO. 387 */ 388 void 389 si_dma_poll(ncr_sc) 390 struct ncr5380_softc *ncr_sc; 391 { 392 struct si_softc *sc = (struct si_softc *)ncr_sc; 393 struct sci_req *sr = ncr_sc->sc_current; 394 volatile struct si_regs *si = sc->sc_regs; 395 int tmo; 396 397 /* Make sure DMA started successfully. */ 398 if (ncr_sc->sc_state & NCR_ABORTING) 399 return; 400 401 /* 402 * XXX: The Sun driver waits for ~SI_CSR_DMA_ACTIVE here 403 * XXX: (on obio) or even worse (on vme) a 10mS. delay! 404 * XXX: I really doubt that is necessary... 405 */ 406 407 /* Wait for any "dma complete" or error bits. */ 408 tmo = POLL_TIMO; 409 for (;;) { 410 if (si->si_csr & CSR_MASK) 411 break; 412 if (--tmo <= 0) { 413 printf("si: DMA timeout (while polling)\n"); 414 /* Indicate timeout as MI code would. */ 415 sr->sr_flags |= SR_OVERDUE; 416 break; 417 } 418 delay(100); 419 } 420 NCR_TRACE("si_dma_poll: waited %d\n", 421 POLL_TIMO - tmo); 422 423 #ifdef DEBUG 424 if (si_debug & 2) { 425 printf("si_dma_poll: done, csr=0x%x\n", si->si_csr); 426 } 427 #endif 428 } 429
Indexes created Mon Oct 13 16:09:52 GMT 2025