si.c revision 1.55
1 /* $NetBSD: si.c,v 1.55 2004/12/13 02:33:06 chs Exp $ */ 2 3 /*- 4 * Copyright (c) 1996 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Adam Glass, David Jones, and Gordon W. Ross. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 /* 40 * This file contains only the machine-dependent parts of the 41 * Sun3 SCSI driver. (Autoconfig stuff and DMA functions.) 42 * The machine-independent parts are in ncr5380sbc.c 43 * 44 * Supported hardware includes: 45 * Sun SCSI-3 on OBIO (Sun3/50,Sun3/60) 46 * Sun SCSI-3 on VME (Sun3/160,Sun3/260) 47 * 48 * Could be made to support the Sun3/E if someone wanted to. 49 * 50 * Note: Both supported variants of the Sun SCSI-3 adapter have 51 * some really unusual "features" for this driver to deal with, 52 * generally related to the DMA engine. The OBIO variant will 53 * ignore any attempt to write the FIFO count register while the 54 * SCSI bus is in DATA_IN or DATA_OUT phase. This is dealt with 55 * by setting the FIFO count early in COMMAND or MSG_IN phase. 56 * 57 * The VME variant has a bit to enable or disable the DMA engine, 58 * but that bit also gates the interrupt line from the NCR5380! 59 * Therefore, in order to get any interrupt from the 5380, (i.e. 60 * for reselect) one must clear the DMA engine transfer count and 61 * then enable DMA. This has the further complication that you 62 * CAN NOT touch the NCR5380 while the DMA enable bit is set, so 63 * we have to turn DMA back off before we even look at the 5380. 64 * 65 * What wonderfully whacky hardware this is! 66 * 67 * Credits, history: 68 * 69 * David Jones wrote the initial version of this module, which 70 * included support for the VME adapter only. (no reselection). 71 * 72 * Gordon Ross added support for the OBIO adapter, and re-worked 73 * both the VME and OBIO code to support disconnect/reselect. 74 * (Required figuring out the hardware "features" noted above.) 75 * 76 * The autoconfiguration boilerplate came from Adam Glass. 77 */ 78 79 #include <sys/cdefs.h> 80 __KERNEL_RCSID(0, "$NetBSD: si.c,v 1.55 2004/12/13 02:33:06 chs Exp $"); 81 82 #include <sys/param.h> 83 #include <sys/systm.h> 84 #include <sys/errno.h> 85 #include <sys/kernel.h> 86 #include <sys/malloc.h> 87 #include <sys/device.h> 88 #include <sys/buf.h> 89 #include <sys/proc.h> 90 #include <sys/user.h> 91 92 #include <dev/scsipi/scsi_all.h> 93 #include <dev/scsipi/scsipi_all.h> 94 #include <dev/scsipi/scsipi_debug.h> 95 #include <dev/scsipi/scsiconf.h> 96 97 #include <machine/autoconf.h> 98 #include <machine/dvma.h> 99 100 /* #define DEBUG XXX */ 101 102 #include <dev/ic/ncr5380reg.h> 103 #include <dev/ic/ncr5380var.h> 104 105 #include "sireg.h" 106 #include "sivar.h" 107 108 /* 109 * Transfers smaller than this are done using PIO 110 * (on assumption they're not worth DMA overhead) 111 */ 112 #define MIN_DMA_LEN 128 113 114 int si_debug = 0; 115 #ifdef DEBUG 116 #endif 117 118 /* How long to wait for DMA before declaring an error. */ 119 int si_dma_intr_timo = 500; /* ticks (sec. X 100) */ 120 121 static void si_minphys __P((struct buf *)); 122 123 /* 124 * New-style autoconfig attachment. The cfattach 125 * structures are in si_obio.c and si_vme.c 126 */ 127 128 void 129 si_attach(sc) 130 struct si_softc *sc; 131 { 132 struct ncr5380_softc *ncr_sc = (void *)sc; 133 volatile struct si_regs *regs = sc->sc_regs; 134 int i; 135 136 /* 137 * Support the "options" (config file flags). 138 * Disconnect/reselect is a per-target mask. 139 * Interrupts and DMA are per-controller. 140 */ 141 ncr_sc->sc_no_disconnect = 142 (sc->sc_options & SI_NO_DISCONNECT); 143 ncr_sc->sc_parity_disable = 144 (sc->sc_options & SI_NO_PARITY_CHK) >> 8; 145 if (sc->sc_options & SI_FORCE_POLLING) 146 ncr_sc->sc_flags |= NCR5380_FORCE_POLLING; 147 148 #if 1 /* XXX - Temporary */ 149 /* XXX - In case we think DMA is completely broken... */ 150 if (sc->sc_options & SI_DISABLE_DMA) { 151 /* Override this function pointer. */ 152 ncr_sc->sc_dma_alloc = NULL; 153 } 154 #endif 155 ncr_sc->sc_min_dma_len = MIN_DMA_LEN; 156 157 /* 158 * Initialize fields used by the MI code 159 */ 160 ncr_sc->sci_r0 = ®s->sci.sci_r0; 161 ncr_sc->sci_r1 = ®s->sci.sci_r1; 162 ncr_sc->sci_r2 = ®s->sci.sci_r2; 163 ncr_sc->sci_r3 = ®s->sci.sci_r3; 164 ncr_sc->sci_r4 = ®s->sci.sci_r4; 165 ncr_sc->sci_r5 = ®s->sci.sci_r5; 166 ncr_sc->sci_r6 = ®s->sci.sci_r6; 167 ncr_sc->sci_r7 = ®s->sci.sci_r7; 168 169 ncr_sc->sc_rev = NCR_VARIANT_NCR5380; 170 171 /* 172 * Allocate DMA handles. 173 */ 174 i = SCI_OPENINGS * sizeof(struct si_dma_handle); 175 sc->sc_dma = (struct si_dma_handle *) 176 malloc(i, M_DEVBUF, M_WAITOK); 177 if (sc->sc_dma == NULL) 178 panic("si: dvma_malloc failed"); 179 for (i = 0; i < SCI_OPENINGS; i++) 180 sc->sc_dma[i].dh_flags = 0; 181 182 ncr_sc->sc_channel.chan_id = 7; 183 ncr_sc->sc_adapter.adapt_minphys = si_minphys; 184 185 /* 186 * Initialize si board itself. 187 */ 188 ncr5380_attach(ncr_sc); 189 190 } 191 192 static void 193 si_minphys(struct buf *bp) 194 { 195 if (bp->b_bcount > MAX_DMA_LEN) { 196 #ifdef DEBUG 197 if (si_debug) { 198 printf("si_minphys len = 0x%x.\n", bp->b_bcount); 199 Debugger(); 200 } 201 #endif 202 bp->b_bcount = MAX_DMA_LEN; 203 } 204 minphys(bp); 205 } 206 207 208 #define CSR_WANT (SI_CSR_SBC_IP | SI_CSR_DMA_IP | \ 209 SI_CSR_DMA_CONFLICT | SI_CSR_DMA_BUS_ERR ) 210 211 int 212 si_intr(void *arg) 213 { 214 struct si_softc *sc = arg; 215 volatile struct si_regs *si = sc->sc_regs; 216 int dma_error, claimed; 217 u_short csr; 218 219 claimed = 0; 220 dma_error = 0; 221 222 /* SBC interrupt? DMA interrupt? */ 223 csr = si->si_csr; 224 NCR_TRACE("si_intr: csr=0x%x\n", csr); 225 226 if (csr & SI_CSR_DMA_CONFLICT) { 227 dma_error |= SI_CSR_DMA_CONFLICT; 228 printf("si_intr: DMA conflict\n"); 229 } 230 if (csr & SI_CSR_DMA_BUS_ERR) { 231 dma_error |= SI_CSR_DMA_BUS_ERR; 232 printf("si_intr: DMA bus error\n"); 233 } 234 if (dma_error) { 235 if (sc->ncr_sc.sc_state & NCR_DOINGDMA) 236 sc->ncr_sc.sc_state |= NCR_ABORTING; 237 /* Make sure we will call the main isr. */ 238 csr |= SI_CSR_DMA_IP; 239 } 240 241 if (csr & (SI_CSR_SBC_IP | SI_CSR_DMA_IP)) { 242 claimed = ncr5380_intr(&sc->ncr_sc); 243 #ifdef DEBUG 244 if (!claimed) { 245 printf("si_intr: spurious from SBC\n"); 246 if (si_debug & 4) 247 Debugger(); /* XXX */ 248 } 249 #endif 250 /* Yes, we DID cause this interrupt. */ 251 claimed = 1; 252 } 253 254 return (claimed); 255 } 256 257 258 /***************************************************************** 259 * Common functions for DMA 260 ****************************************************************/ 261 262 /* 263 * Allocate a DMA handle and put it in sc->sc_dma. Prepare 264 * for DMA transfer. On the Sun3, this means mapping the buffer 265 * into DVMA space. dvma_mapin() flushes the cache for us. 266 */ 267 void 268 si_dma_alloc(ncr_sc) 269 struct ncr5380_softc *ncr_sc; 270 { 271 struct si_softc *sc = (struct si_softc *)ncr_sc; 272 struct sci_req *sr = ncr_sc->sc_current; 273 struct scsipi_xfer *xs = sr->sr_xs; 274 struct si_dma_handle *dh; 275 int i, xlen; 276 u_long addr; 277 278 #ifdef DIAGNOSTIC 279 if (sr->sr_dma_hand != NULL) 280 panic("si_dma_alloc: already have DMA handle"); 281 #endif 282 283 addr = (u_long) ncr_sc->sc_dataptr; 284 xlen = ncr_sc->sc_datalen; 285 286 /* If the DMA start addr is misaligned then do PIO */ 287 if ((addr & 1) || (xlen & 1)) { 288 printf("si_dma_alloc: misaligned.\n"); 289 return; 290 } 291 292 /* Make sure our caller checked sc_min_dma_len. */ 293 if (xlen < MIN_DMA_LEN) 294 panic("si_dma_alloc: xlen=0x%x", xlen); 295 296 /* 297 * Never attempt single transfers of more than 63k, because 298 * our count register may be only 16 bits (an OBIO adapter). 299 * This should never happen since already bounded by minphys(). 300 * XXX - Should just segment these... 301 */ 302 if (xlen > MAX_DMA_LEN) { 303 printf("si_dma_alloc: excessive xlen=0x%x\n", xlen); 304 Debugger(); 305 ncr_sc->sc_datalen = xlen = MAX_DMA_LEN; 306 } 307 308 /* Find free DMA handle. Guaranteed to find one since we have 309 as many DMA handles as the driver has processes. */ 310 for (i = 0; i < SCI_OPENINGS; i++) { 311 if ((sc->sc_dma[i].dh_flags & SIDH_BUSY) == 0) 312 goto found; 313 } 314 panic("si: no free DMA handles."); 315 found: 316 317 dh = &sc->sc_dma[i]; 318 dh->dh_flags = SIDH_BUSY; 319 dh->dh_addr = (u_char*) addr; 320 dh->dh_maplen = xlen; 321 dh->dh_dvma = 0; 322 323 /* Copy the "write" flag for convenience. */ 324 if (xs->xs_control & XS_CTL_DATA_OUT) 325 dh->dh_flags |= SIDH_OUT; 326 327 #if 0 328 /* 329 * Some machines might not need to remap B_PHYS buffers. 330 * The sun3 does not map B_PHYS buffers into DVMA space, 331 * (they are mapped into normal KV space) so on the sun3 332 * we must always remap to a DVMA address here. Re-map is 333 * cheap anyway, because it's done by segments, not pages. 334 */ 335 if (xs->bp && (xs->bp->b_flags & B_PHYS)) 336 dh->dh_flags |= SIDH_PHYS; 337 #endif 338 339 dh->dh_dvma = dvma_mapin((char *)addr, xlen, 0); 340 if (!dh->dh_dvma) { 341 /* Can't remap segment */ 342 printf("si_dma_alloc: can't remap %p/0x%x\n", 343 dh->dh_addr, dh->dh_maplen); 344 dh->dh_flags = 0; 345 return; 346 } 347 348 /* success */ 349 sr->sr_dma_hand = dh; 350 351 return; 352 } 353 354 355 void 356 si_dma_free(ncr_sc) 357 struct ncr5380_softc *ncr_sc; 358 { 359 struct sci_req *sr = ncr_sc->sc_current; 360 struct si_dma_handle *dh = sr->sr_dma_hand; 361 362 #ifdef DIAGNOSTIC 363 if (dh == NULL) 364 panic("si_dma_free: no DMA handle"); 365 #endif 366 367 if (ncr_sc->sc_state & NCR_DOINGDMA) 368 panic("si_dma_free: free while in progress"); 369 370 if (dh->dh_flags & SIDH_BUSY) { 371 /* XXX - Should separate allocation and mapping. */ 372 /* Give back the DVMA space. */ 373 dvma_mapout(dh->dh_dvma, dh->dh_maplen); 374 dh->dh_dvma = 0; 375 dh->dh_flags = 0; 376 } 377 sr->sr_dma_hand = NULL; 378 } 379 380 381 #define CSR_MASK (SI_CSR_SBC_IP | SI_CSR_DMA_IP | \ 382 SI_CSR_DMA_CONFLICT | SI_CSR_DMA_BUS_ERR) 383 #define POLL_TIMO 50000 /* X100 = 5 sec. */ 384 385 /* 386 * Poll (spin-wait) for DMA completion. 387 * Called right after xx_dma_start(), and 388 * xx_dma_stop() will be called next. 389 * Same for either VME or OBIO. 390 */ 391 void 392 si_dma_poll(ncr_sc) 393 struct ncr5380_softc *ncr_sc; 394 { 395 struct si_softc *sc = (struct si_softc *)ncr_sc; 396 struct sci_req *sr = ncr_sc->sc_current; 397 volatile struct si_regs *si = sc->sc_regs; 398 int tmo; 399 400 /* Make sure DMA started successfully. */ 401 if (ncr_sc->sc_state & NCR_ABORTING) 402 return; 403 404 /* 405 * XXX: The Sun driver waits for ~SI_CSR_DMA_ACTIVE here 406 * XXX: (on obio) or even worse (on vme) a 10mS. delay! 407 * XXX: I really doubt that is necessary... 408 */ 409 410 /* Wait for any "DMA complete" or error bits. */ 411 tmo = POLL_TIMO; 412 for (;;) { 413 if (si->si_csr & CSR_MASK) 414 break; 415 if (--tmo <= 0) { 416 printf("si: DMA timeout (while polling)\n"); 417 /* Indicate timeout as MI code would. */ 418 sr->sr_flags |= SR_OVERDUE; 419 break; 420 } 421 delay(100); 422 } 423 NCR_TRACE("si_dma_poll: waited %d\n", 424 POLL_TIMO - tmo); 425 426 #ifdef DEBUG 427 if (si_debug & 2) { 428 printf("si_dma_poll: done, csr=0x%x\n", si->si_csr); 429 } 430 #endif 431 } 432
Indexes created Mon Oct 13 16:09:52 GMT 2025