si.c revision 1.55.2.1
1 /* $NetBSD: si.c,v 1.55.2.1 2005/04/29 11:28:26 kent Exp $ */ 2 3 /*- 4 * Copyright (c) 1996 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Adam Glass, David Jones, and Gordon W. Ross. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 /* 40 * This file contains only the machine-dependent parts of the 41 * Sun3 SCSI driver. (Autoconfig stuff and DMA functions.) 42 * The machine-independent parts are in ncr5380sbc.c 43 * 44 * Supported hardware includes: 45 * Sun SCSI-3 on OBIO (Sun3/50,Sun3/60) 46 * Sun SCSI-3 on VME (Sun3/160,Sun3/260) 47 * 48 * Could be made to support the Sun3/E if someone wanted to. 49 * 50 * Note: Both supported variants of the Sun SCSI-3 adapter have 51 * some really unusual "features" for this driver to deal with, 52 * generally related to the DMA engine. The OBIO variant will 53 * ignore any attempt to write the FIFO count register while the 54 * SCSI bus is in DATA_IN or DATA_OUT phase. This is dealt with 55 * by setting the FIFO count early in COMMAND or MSG_IN phase. 56 * 57 * The VME variant has a bit to enable or disable the DMA engine, 58 * but that bit also gates the interrupt line from the NCR5380! 59 * Therefore, in order to get any interrupt from the 5380, (i.e. 60 * for reselect) one must clear the DMA engine transfer count and 61 * then enable DMA. This has the further complication that you 62 * CAN NOT touch the NCR5380 while the DMA enable bit is set, so 63 * we have to turn DMA back off before we even look at the 5380. 64 * 65 * What wonderfully whacky hardware this is! 66 * 67 * Credits, history: 68 * 69 * David Jones wrote the initial version of this module, which 70 * included support for the VME adapter only. (no reselection). 71 * 72 * Gordon Ross added support for the OBIO adapter, and re-worked 73 * both the VME and OBIO code to support disconnect/reselect. 74 * (Required figuring out the hardware "features" noted above.) 75 * 76 * The autoconfiguration boilerplate came from Adam Glass. 77 */ 78 79 #include <sys/cdefs.h> 80 __KERNEL_RCSID(0, "$NetBSD: si.c,v 1.55.2.1 2005/04/29 11:28:26 kent Exp $"); 81 82 #include <sys/param.h> 83 #include <sys/systm.h> 84 #include <sys/errno.h> 85 #include <sys/kernel.h> 86 #include <sys/malloc.h> 87 #include <sys/device.h> 88 #include <sys/buf.h> 89 #include <sys/proc.h> 90 #include <sys/user.h> 91 92 #include <dev/scsipi/scsi_all.h> 93 #include <dev/scsipi/scsipi_all.h> 94 #include <dev/scsipi/scsipi_debug.h> 95 #include <dev/scsipi/scsiconf.h> 96 97 #include <machine/autoconf.h> 98 #include <machine/dvma.h> 99 100 /* #define DEBUG XXX */ 101 102 #include <dev/ic/ncr5380reg.h> 103 #include <dev/ic/ncr5380var.h> 104 105 #include "sireg.h" 106 #include "sivar.h" 107 108 /* 109 * Transfers smaller than this are done using PIO 110 * (on assumption they're not worth DMA overhead) 111 */ 112 #define MIN_DMA_LEN 128 113 114 int si_debug = 0; 115 #ifdef DEBUG 116 #endif 117 118 /* How long to wait for DMA before declaring an error. */ 119 int si_dma_intr_timo = 500; /* ticks (sec. X 100) */ 120 121 static void si_minphys(struct buf *); 122 123 /* 124 * New-style autoconfig attachment. The cfattach 125 * structures are in si_obio.c and si_vme.c 126 */ 127 128 void 129 si_attach(struct si_softc *sc) 130 { 131 struct ncr5380_softc *ncr_sc = (void *)sc; 132 volatile struct si_regs *regs = sc->sc_regs; 133 int i; 134 135 /* 136 * Support the "options" (config file flags). 137 * Disconnect/reselect is a per-target mask. 138 * Interrupts and DMA are per-controller. 139 */ 140 ncr_sc->sc_no_disconnect = 141 (sc->sc_options & SI_NO_DISCONNECT); 142 ncr_sc->sc_parity_disable = 143 (sc->sc_options & SI_NO_PARITY_CHK) >> 8; 144 if (sc->sc_options & SI_FORCE_POLLING) 145 ncr_sc->sc_flags |= NCR5380_FORCE_POLLING; 146 147 #if 1 /* XXX - Temporary */ 148 /* XXX - In case we think DMA is completely broken... */ 149 if (sc->sc_options & SI_DISABLE_DMA) { 150 /* Override this function pointer. */ 151 ncr_sc->sc_dma_alloc = NULL; 152 } 153 #endif 154 ncr_sc->sc_min_dma_len = MIN_DMA_LEN; 155 156 /* 157 * Initialize fields used by the MI code 158 */ 159 ncr_sc->sci_r0 = ®s->sci.sci_r0; 160 ncr_sc->sci_r1 = ®s->sci.sci_r1; 161 ncr_sc->sci_r2 = ®s->sci.sci_r2; 162 ncr_sc->sci_r3 = ®s->sci.sci_r3; 163 ncr_sc->sci_r4 = ®s->sci.sci_r4; 164 ncr_sc->sci_r5 = ®s->sci.sci_r5; 165 ncr_sc->sci_r6 = ®s->sci.sci_r6; 166 ncr_sc->sci_r7 = ®s->sci.sci_r7; 167 168 ncr_sc->sc_rev = NCR_VARIANT_NCR5380; 169 170 /* 171 * Allocate DMA handles. 172 */ 173 i = SCI_OPENINGS * sizeof(struct si_dma_handle); 174 sc->sc_dma = (struct si_dma_handle *) 175 malloc(i, M_DEVBUF, M_WAITOK); 176 if (sc->sc_dma == NULL) 177 panic("si: dvma_malloc failed"); 178 for (i = 0; i < SCI_OPENINGS; i++) 179 sc->sc_dma[i].dh_flags = 0; 180 181 ncr_sc->sc_channel.chan_id = 7; 182 ncr_sc->sc_adapter.adapt_minphys = si_minphys; 183 184 /* 185 * Initialize si board itself. 186 */ 187 ncr5380_attach(ncr_sc); 188 189 } 190 191 static void 192 si_minphys(struct buf *bp) 193 { 194 if (bp->b_bcount > MAX_DMA_LEN) { 195 #ifdef DEBUG 196 if (si_debug) { 197 printf("si_minphys len = 0x%x.\n", bp->b_bcount); 198 Debugger(); 199 } 200 #endif 201 bp->b_bcount = MAX_DMA_LEN; 202 } 203 minphys(bp); 204 } 205 206 207 #define CSR_WANT (SI_CSR_SBC_IP | SI_CSR_DMA_IP | \ 208 SI_CSR_DMA_CONFLICT | SI_CSR_DMA_BUS_ERR ) 209 210 int 211 si_intr(void *arg) 212 { 213 struct si_softc *sc = arg; 214 volatile struct si_regs *si = sc->sc_regs; 215 int dma_error, claimed; 216 u_short csr; 217 218 claimed = 0; 219 dma_error = 0; 220 221 /* SBC interrupt? DMA interrupt? */ 222 csr = si->si_csr; 223 NCR_TRACE("si_intr: csr=0x%x\n", csr); 224 225 if (csr & SI_CSR_DMA_CONFLICT) { 226 dma_error |= SI_CSR_DMA_CONFLICT; 227 printf("si_intr: DMA conflict\n"); 228 } 229 if (csr & SI_CSR_DMA_BUS_ERR) { 230 dma_error |= SI_CSR_DMA_BUS_ERR; 231 printf("si_intr: DMA bus error\n"); 232 } 233 if (dma_error) { 234 if (sc->ncr_sc.sc_state & NCR_DOINGDMA) 235 sc->ncr_sc.sc_state |= NCR_ABORTING; 236 /* Make sure we will call the main isr. */ 237 csr |= SI_CSR_DMA_IP; 238 } 239 240 if (csr & (SI_CSR_SBC_IP | SI_CSR_DMA_IP)) { 241 claimed = ncr5380_intr(&sc->ncr_sc); 242 #ifdef DEBUG 243 if (!claimed) { 244 printf("si_intr: spurious from SBC\n"); 245 if (si_debug & 4) 246 Debugger(); /* XXX */ 247 } 248 #endif 249 /* Yes, we DID cause this interrupt. */ 250 claimed = 1; 251 } 252 253 return (claimed); 254 } 255 256 257 /***************************************************************** 258 * Common functions for DMA 259 ****************************************************************/ 260 261 /* 262 * Allocate a DMA handle and put it in sc->sc_dma. Prepare 263 * for DMA transfer. On the Sun3, this means mapping the buffer 264 * into DVMA space. dvma_mapin() flushes the cache for us. 265 */ 266 void 267 si_dma_alloc(struct ncr5380_softc *ncr_sc) 268 { 269 struct si_softc *sc = (struct si_softc *)ncr_sc; 270 struct sci_req *sr = ncr_sc->sc_current; 271 struct scsipi_xfer *xs = sr->sr_xs; 272 struct si_dma_handle *dh; 273 int i, xlen; 274 u_long addr; 275 276 #ifdef DIAGNOSTIC 277 if (sr->sr_dma_hand != NULL) 278 panic("si_dma_alloc: already have DMA handle"); 279 #endif 280 281 addr = (u_long) ncr_sc->sc_dataptr; 282 xlen = ncr_sc->sc_datalen; 283 284 /* If the DMA start addr is misaligned then do PIO */ 285 if ((addr & 1) || (xlen & 1)) { 286 printf("si_dma_alloc: misaligned.\n"); 287 return; 288 } 289 290 /* Make sure our caller checked sc_min_dma_len. */ 291 if (xlen < MIN_DMA_LEN) 292 panic("si_dma_alloc: xlen=0x%x", xlen); 293 294 /* 295 * Never attempt single transfers of more than 63k, because 296 * our count register may be only 16 bits (an OBIO adapter). 297 * This should never happen since already bounded by minphys(). 298 * XXX - Should just segment these... 299 */ 300 if (xlen > MAX_DMA_LEN) { 301 printf("si_dma_alloc: excessive xlen=0x%x\n", xlen); 302 Debugger(); 303 ncr_sc->sc_datalen = xlen = MAX_DMA_LEN; 304 } 305 306 /* Find free DMA handle. Guaranteed to find one since we have 307 as many DMA handles as the driver has processes. */ 308 for (i = 0; i < SCI_OPENINGS; i++) { 309 if ((sc->sc_dma[i].dh_flags & SIDH_BUSY) == 0) 310 goto found; 311 } 312 panic("si: no free DMA handles."); 313 found: 314 315 dh = &sc->sc_dma[i]; 316 dh->dh_flags = SIDH_BUSY; 317 dh->dh_addr = (u_char*) addr; 318 dh->dh_maplen = xlen; 319 dh->dh_dvma = 0; 320 321 /* Copy the "write" flag for convenience. */ 322 if (xs->xs_control & XS_CTL_DATA_OUT) 323 dh->dh_flags |= SIDH_OUT; 324 325 #if 0 326 /* 327 * Some machines might not need to remap B_PHYS buffers. 328 * The sun3 does not map B_PHYS buffers into DVMA space, 329 * (they are mapped into normal KV space) so on the sun3 330 * we must always remap to a DVMA address here. Re-map is 331 * cheap anyway, because it's done by segments, not pages. 332 */ 333 if (xs->bp && (xs->bp->b_flags & B_PHYS)) 334 dh->dh_flags |= SIDH_PHYS; 335 #endif 336 337 dh->dh_dvma = dvma_mapin((char *)addr, xlen, 0); 338 if (!dh->dh_dvma) { 339 /* Can't remap segment */ 340 printf("si_dma_alloc: can't remap %p/0x%x\n", 341 dh->dh_addr, dh->dh_maplen); 342 dh->dh_flags = 0; 343 return; 344 } 345 346 /* success */ 347 sr->sr_dma_hand = dh; 348 349 return; 350 } 351 352 353 void 354 si_dma_free(struct ncr5380_softc *ncr_sc) 355 { 356 struct sci_req *sr = ncr_sc->sc_current; 357 struct si_dma_handle *dh = sr->sr_dma_hand; 358 359 #ifdef DIAGNOSTIC 360 if (dh == NULL) 361 panic("si_dma_free: no DMA handle"); 362 #endif 363 364 if (ncr_sc->sc_state & NCR_DOINGDMA) 365 panic("si_dma_free: free while in progress"); 366 367 if (dh->dh_flags & SIDH_BUSY) { 368 /* XXX - Should separate allocation and mapping. */ 369 /* Give back the DVMA space. */ 370 dvma_mapout(dh->dh_dvma, dh->dh_maplen); 371 dh->dh_dvma = 0; 372 dh->dh_flags = 0; 373 } 374 sr->sr_dma_hand = NULL; 375 } 376 377 378 #define CSR_MASK (SI_CSR_SBC_IP | SI_CSR_DMA_IP | \ 379 SI_CSR_DMA_CONFLICT | SI_CSR_DMA_BUS_ERR) 380 #define POLL_TIMO 50000 /* X100 = 5 sec. */ 381 382 /* 383 * Poll (spin-wait) for DMA completion. 384 * Called right after xx_dma_start(), and 385 * xx_dma_stop() will be called next. 386 * Same for either VME or OBIO. 387 */ 388 void 389 si_dma_poll(struct ncr5380_softc *ncr_sc) 390 { 391 struct si_softc *sc = (struct si_softc *)ncr_sc; 392 struct sci_req *sr = ncr_sc->sc_current; 393 volatile struct si_regs *si = sc->sc_regs; 394 int tmo; 395 396 /* Make sure DMA started successfully. */ 397 if (ncr_sc->sc_state & NCR_ABORTING) 398 return; 399 400 /* 401 * XXX: The Sun driver waits for ~SI_CSR_DMA_ACTIVE here 402 * XXX: (on obio) or even worse (on vme) a 10mS. delay! 403 * XXX: I really doubt that is necessary... 404 */ 405 406 /* Wait for any "DMA complete" or error bits. */ 407 tmo = POLL_TIMO; 408 for (;;) { 409 if (si->si_csr & CSR_MASK) 410 break; 411 if (--tmo <= 0) { 412 printf("si: DMA timeout (while polling)\n"); 413 /* Indicate timeout as MI code would. */ 414 sr->sr_flags |= SR_OVERDUE; 415 break; 416 } 417 delay(100); 418 } 419 NCR_TRACE("si_dma_poll: waited %d\n", 420 POLL_TIMO - tmo); 421 422 #ifdef DEBUG 423 if (si_debug & 2) { 424 printf("si_dma_poll: done, csr=0x%x\n", si->si_csr); 425 } 426 #endif 427 } 428
Indexes created Mon Oct 13 16:09:52 GMT 2025