si.c revision 1.57.20.1
1 /* $NetBSD: si.c,v 1.57.20.1 2007/02/09 21:03:50 ad Exp $ */ 2 3 /*- 4 * Copyright (c) 1996 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Adam Glass, David Jones, and Gordon W. Ross. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 /* 40 * This file contains only the machine-dependent parts of the 41 * Sun3 SCSI driver. (Autoconfig stuff and DMA functions.) 42 * The machine-independent parts are in ncr5380sbc.c 43 * 44 * Supported hardware includes: 45 * Sun SCSI-3 on OBIO (Sun3/50,Sun3/60) 46 * Sun SCSI-3 on VME (Sun3/160,Sun3/260) 47 * 48 * Could be made to support the Sun3/E if someone wanted to. 49 * 50 * Note: Both supported variants of the Sun SCSI-3 adapter have 51 * some really unusual "features" for this driver to deal with, 52 * generally related to the DMA engine. The OBIO variant will 53 * ignore any attempt to write the FIFO count register while the 54 * SCSI bus is in DATA_IN or DATA_OUT phase. This is dealt with 55 * by setting the FIFO count early in COMMAND or MSG_IN phase. 56 * 57 * The VME variant has a bit to enable or disable the DMA engine, 58 * but that bit also gates the interrupt line from the NCR5380! 59 * Therefore, in order to get any interrupt from the 5380, (i.e. 60 * for reselect) one must clear the DMA engine transfer count and 61 * then enable DMA. This has the further complication that you 62 * CAN NOT touch the NCR5380 while the DMA enable bit is set, so 63 * we have to turn DMA back off before we even look at the 5380. 64 * 65 * What wonderfully whacky hardware this is! 66 * 67 * Credits, history: 68 * 69 * David Jones wrote the initial version of this module, which 70 * included support for the VME adapter only. (no reselection). 71 * 72 * Gordon Ross added support for the OBIO adapter, and re-worked 73 * both the VME and OBIO code to support disconnect/reselect. 74 * (Required figuring out the hardware "features" noted above.) 75 * 76 * The autoconfiguration boilerplate came from Adam Glass. 77 */ 78 79 #include <sys/cdefs.h> 80 __KERNEL_RCSID(0, "$NetBSD: si.c,v 1.57.20.1 2007/02/09 21:03:50 ad Exp $"); 81 82 #include <sys/param.h> 83 #include <sys/systm.h> 84 #include <sys/errno.h> 85 #include <sys/kernel.h> 86 #include <sys/malloc.h> 87 #include <sys/device.h> 88 #include <sys/buf.h> 89 #include <sys/proc.h> 90 #include <sys/user.h> 91 92 #include <dev/scsipi/scsi_all.h> 93 #include <dev/scsipi/scsipi_all.h> 94 #include <dev/scsipi/scsipi_debug.h> 95 #include <dev/scsipi/scsiconf.h> 96 97 #include <machine/autoconf.h> 98 #include <machine/bus.h> 99 #include <machine/dvma.h> 100 101 /* #define DEBUG XXX */ 102 103 #include <dev/ic/ncr5380reg.h> 104 #include <dev/ic/ncr5380var.h> 105 106 #include "sireg.h" 107 #include "sivar.h" 108 109 /* 110 * Transfers smaller than this are done using PIO 111 * (on assumption they're not worth DMA overhead) 112 */ 113 #define MIN_DMA_LEN 128 114 115 int si_debug = 0; 116 #ifdef DEBUG 117 #endif 118 119 /* How long to wait for DMA before declaring an error. */ 120 int si_dma_intr_timo = 500; /* ticks (sec. X 100) */ 121 122 static void si_minphys(struct buf *); 123 124 /* 125 * New-style autoconfig attachment. The cfattach 126 * structures are in si_obio.c and si_vme.c 127 */ 128 129 void 130 si_attach(struct si_softc *sc) 131 { 132 struct ncr5380_softc *ncr_sc = (void *)sc; 133 volatile struct si_regs *regs = sc->sc_regs; 134 int i; 135 136 /* 137 * Support the "options" (config file flags). 138 * Disconnect/reselect is a per-target mask. 139 * Interrupts and DMA are per-controller. 140 */ 141 ncr_sc->sc_no_disconnect = 142 (sc->sc_options & SI_NO_DISCONNECT); 143 ncr_sc->sc_parity_disable = 144 (sc->sc_options & SI_NO_PARITY_CHK) >> 8; 145 if (sc->sc_options & SI_FORCE_POLLING) 146 ncr_sc->sc_flags |= NCR5380_FORCE_POLLING; 147 148 #if 1 /* XXX - Temporary */ 149 /* XXX - In case we think DMA is completely broken... */ 150 if (sc->sc_options & SI_DISABLE_DMA) { 151 /* Override this function pointer. */ 152 ncr_sc->sc_dma_alloc = NULL; 153 } 154 #endif 155 ncr_sc->sc_min_dma_len = MIN_DMA_LEN; 156 157 /* 158 * Initialize fields used by the MI code 159 */ 160 ncr_sc->sci_r0 = ®s->sci.sci_r0; 161 ncr_sc->sci_r1 = ®s->sci.sci_r1; 162 ncr_sc->sci_r2 = ®s->sci.sci_r2; 163 ncr_sc->sci_r3 = ®s->sci.sci_r3; 164 ncr_sc->sci_r4 = ®s->sci.sci_r4; 165 ncr_sc->sci_r5 = ®s->sci.sci_r5; 166 ncr_sc->sci_r6 = ®s->sci.sci_r6; 167 ncr_sc->sci_r7 = ®s->sci.sci_r7; 168 169 ncr_sc->sc_rev = NCR_VARIANT_NCR5380; 170 171 /* 172 * Allocate DMA handles. 173 */ 174 i = SCI_OPENINGS * sizeof(struct si_dma_handle); 175 sc->sc_dma = (struct si_dma_handle *) 176 malloc(i, M_DEVBUF, M_WAITOK); 177 if (sc->sc_dma == NULL) 178 panic("si: dvma_malloc failed"); 179 for (i = 0; i < SCI_OPENINGS; i++) 180 sc->sc_dma[i].dh_flags = 0; 181 182 ncr_sc->sc_channel.chan_id = 7; 183 ncr_sc->sc_adapter.adapt_minphys = si_minphys; 184 185 /* 186 * Initialize si board itself. 187 */ 188 ncr5380_attach(ncr_sc); 189 190 } 191 192 static void 193 si_minphys(struct buf *bp) 194 { 195 if (bp->b_bcount > MAX_DMA_LEN) { 196 #ifdef DEBUG 197 if (si_debug) { 198 printf("si_minphys len = 0x%x.\n", bp->b_bcount); 199 Debugger(); 200 } 201 #endif 202 bp->b_bcount = MAX_DMA_LEN; 203 } 204 minphys(bp); 205 } 206 207 208 #define CSR_WANT (SI_CSR_SBC_IP | SI_CSR_DMA_IP | \ 209 SI_CSR_DMA_CONFLICT | SI_CSR_DMA_BUS_ERR ) 210 211 int 212 si_intr(void *arg) 213 { 214 struct si_softc *sc = arg; 215 volatile struct si_regs *si = sc->sc_regs; 216 int dma_error, claimed; 217 u_short csr; 218 219 claimed = 0; 220 dma_error = 0; 221 222 /* SBC interrupt? DMA interrupt? */ 223 csr = si->si_csr; 224 NCR_TRACE("si_intr: csr=0x%x\n", csr); 225 226 if (csr & SI_CSR_DMA_CONFLICT) { 227 dma_error |= SI_CSR_DMA_CONFLICT; 228 printf("si_intr: DMA conflict\n"); 229 } 230 if (csr & SI_CSR_DMA_BUS_ERR) { 231 dma_error |= SI_CSR_DMA_BUS_ERR; 232 printf("si_intr: DMA bus error\n"); 233 } 234 if (dma_error) { 235 if (sc->ncr_sc.sc_state & NCR_DOINGDMA) 236 sc->ncr_sc.sc_state |= NCR_ABORTING; 237 /* Make sure we will call the main isr. */ 238 csr |= SI_CSR_DMA_IP; 239 } 240 241 if (csr & (SI_CSR_SBC_IP | SI_CSR_DMA_IP)) { 242 claimed = ncr5380_intr(&sc->ncr_sc); 243 #ifdef DEBUG 244 if (!claimed) { 245 printf("si_intr: spurious from SBC\n"); 246 if (si_debug & 4) 247 Debugger(); /* XXX */ 248 } 249 #endif 250 /* Yes, we DID cause this interrupt. */ 251 claimed = 1; 252 } 253 254 return (claimed); 255 } 256 257 258 /***************************************************************** 259 * Common functions for DMA 260 ****************************************************************/ 261 262 /* 263 * Allocate a DMA handle and put it in sc->sc_dma. Prepare 264 * for DMA transfer. On the Sun3, this means mapping the buffer 265 * into DVMA space. dvma_mapin() flushes the cache for us. 266 */ 267 void 268 si_dma_alloc(struct ncr5380_softc *ncr_sc) 269 { 270 struct si_softc *sc = (struct si_softc *)ncr_sc; 271 struct sci_req *sr = ncr_sc->sc_current; 272 struct scsipi_xfer *xs = sr->sr_xs; 273 struct si_dma_handle *dh; 274 int i, xlen; 275 void *addr; 276 277 #ifdef DIAGNOSTIC 278 if (sr->sr_dma_hand != NULL) 279 panic("si_dma_alloc: already have DMA handle"); 280 #endif 281 282 addr = ncr_sc->sc_dataptr; 283 xlen = ncr_sc->sc_datalen; 284 285 /* If the DMA start addr is misaligned then do PIO */ 286 if (((vaddr_t)addr & 1) || (xlen & 1)) { 287 printf("si_dma_alloc: misaligned.\n"); 288 return; 289 } 290 291 /* Make sure our caller checked sc_min_dma_len. */ 292 if (xlen < MIN_DMA_LEN) 293 panic("si_dma_alloc: xlen=0x%x", xlen); 294 295 /* 296 * Never attempt single transfers of more than 63k, because 297 * our count register may be only 16 bits (an OBIO adapter). 298 * This should never happen since already bounded by minphys(). 299 * XXX - Should just segment these... 300 */ 301 if (xlen > MAX_DMA_LEN) { 302 printf("si_dma_alloc: excessive xlen=0x%x\n", xlen); 303 Debugger(); 304 ncr_sc->sc_datalen = xlen = MAX_DMA_LEN; 305 } 306 307 /* Find free DMA handle. Guaranteed to find one since we have 308 as many DMA handles as the driver has processes. */ 309 for (i = 0; i < SCI_OPENINGS; i++) { 310 if ((sc->sc_dma[i].dh_flags & SIDH_BUSY) == 0) 311 goto found; 312 } 313 panic("si: no free DMA handles."); 314 found: 315 316 dh = &sc->sc_dma[i]; 317 dh->dh_flags = SIDH_BUSY; 318 319 if (bus_dmamap_load(sc->sc_dmat, sc->sc_dmap, addr, xlen, NULL, 320 BUS_DMA_NOWAIT) != 0) 321 panic("%s: can't load dmamap", ncr_sc->sc_dev.dv_xname); 322 dh->dh_dmaaddr = sc->sc_dmap->dm_segs[0].ds_addr; 323 dh->dh_dmalen = xlen; 324 325 /* Copy the "write" flag for convenience. */ 326 if (xs->xs_control & XS_CTL_DATA_OUT) 327 dh->dh_flags |= SIDH_OUT; 328 329 bus_dmamap_sync(sc->sc_dmat, sc->sc_dmap, 0, dh->dh_dmalen, 330 (dh->dh_flags & SIDH_OUT) == 0 ? 331 BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE); 332 333 #if 0 334 /* 335 * Some machines might not need to remap B_PHYS buffers. 336 * The sun3 does not map B_PHYS buffers into DVMA space, 337 * (they are mapped into normal KV space) so on the sun3 338 * we must always remap to a DVMA address here. Re-map is 339 * cheap anyway, because it's done by segments, not pages. 340 */ 341 if (xs->bp && (xs->bp->b_flags & B_PHYS)) 342 dh->dh_flags |= SIDH_PHYS; 343 #endif 344 345 /* success */ 346 sr->sr_dma_hand = dh; 347 348 return; 349 } 350 351 352 void 353 si_dma_free(struct ncr5380_softc *ncr_sc) 354 { 355 struct si_softc *sc = (struct si_softc *)ncr_sc; 356 struct sci_req *sr = ncr_sc->sc_current; 357 struct si_dma_handle *dh = sr->sr_dma_hand; 358 359 #ifdef DIAGNOSTIC 360 if (dh == NULL) 361 panic("si_dma_free: no DMA handle"); 362 #endif 363 364 if (ncr_sc->sc_state & NCR_DOINGDMA) 365 panic("si_dma_free: free while in progress"); 366 367 if (dh->dh_flags & SIDH_BUSY) { 368 bus_dmamap_sync(sc->sc_dmat, sc->sc_dmap, 0, dh->dh_dmalen, 369 (dh->dh_flags & SIDH_OUT) == 0 ? 370 BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 371 bus_dmamap_unload(sc->sc_dmat, sc->sc_dmap); 372 dh->dh_dmaaddr = 0; 373 dh->dh_flags = 0; 374 } 375 sr->sr_dma_hand = NULL; 376 } 377 378 379 #define CSR_MASK (SI_CSR_SBC_IP | SI_CSR_DMA_IP | \ 380 SI_CSR_DMA_CONFLICT | SI_CSR_DMA_BUS_ERR) 381 #define POLL_TIMO 50000 /* X100 = 5 sec. */ 382 383 /* 384 * Poll (spin-wait) for DMA completion. 385 * Called right after xx_dma_start(), and 386 * xx_dma_stop() will be called next. 387 * Same for either VME or OBIO. 388 */ 389 void 390 si_dma_poll(struct ncr5380_softc *ncr_sc) 391 { 392 struct si_softc *sc = (struct si_softc *)ncr_sc; 393 struct sci_req *sr = ncr_sc->sc_current; 394 volatile struct si_regs *si = sc->sc_regs; 395 int tmo; 396 397 /* Make sure DMA started successfully. */ 398 if (ncr_sc->sc_state & NCR_ABORTING) 399 return; 400 401 /* 402 * XXX: The Sun driver waits for ~SI_CSR_DMA_ACTIVE here 403 * XXX: (on obio) or even worse (on vme) a 10mS. delay! 404 * XXX: I really doubt that is necessary... 405 */ 406 407 /* Wait for any "DMA complete" or error bits. */ 408 tmo = POLL_TIMO; 409 for (;;) { 410 if (si->si_csr & CSR_MASK) 411 break; 412 if (--tmo <= 0) { 413 printf("si: DMA timeout (while polling)\n"); 414 /* Indicate timeout as MI code would. */ 415 sr->sr_flags |= SR_OVERDUE; 416 break; 417 } 418 delay(100); 419 } 420 NCR_TRACE("si_dma_poll: waited %d\n", 421 POLL_TIMO - tmo); 422 423 #ifdef DEBUG 424 if (si_debug & 2) { 425 printf("si_dma_poll: done, csr=0x%x\n", si->si_csr); 426 } 427 #endif 428 } 429
Indexes created Mon Oct 13 08:09:50 GMT 2025