si.c revision 1.61.2.1
1 /* $NetBSD: si.c,v 1.61.2.1 2008/05/18 12:32:54 yamt Exp $ */ 2 3 /*- 4 * Copyright (c) 1996 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Adam Glass, David Jones, and Gordon W. Ross. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 /* 33 * This file contains only the machine-dependent parts of the 34 * Sun3 SCSI driver. (Autoconfig stuff and DMA functions.) 35 * The machine-independent parts are in ncr5380sbc.c 36 * 37 * Supported hardware includes: 38 * Sun SCSI-3 on OBIO (Sun3/50,Sun3/60) 39 * Sun SCSI-3 on VME (Sun3/160,Sun3/260) 40 * 41 * Could be made to support the Sun3/E if someone wanted to. 42 * 43 * Note: Both supported variants of the Sun SCSI-3 adapter have 44 * some really unusual "features" for this driver to deal with, 45 * generally related to the DMA engine. The OBIO variant will 46 * ignore any attempt to write the FIFO count register while the 47 * SCSI bus is in DATA_IN or DATA_OUT phase. This is dealt with 48 * by setting the FIFO count early in COMMAND or MSG_IN phase. 49 * 50 * The VME variant has a bit to enable or disable the DMA engine, 51 * but that bit also gates the interrupt line from the NCR5380! 52 * Therefore, in order to get any interrupt from the 5380, (i.e. 53 * for reselect) one must clear the DMA engine transfer count and 54 * then enable DMA. This has the further complication that you 55 * CAN NOT touch the NCR5380 while the DMA enable bit is set, so 56 * we have to turn DMA back off before we even look at the 5380. 57 * 58 * What wonderfully whacky hardware this is! 59 * 60 * Credits, history: 61 * 62 * David Jones wrote the initial version of this module, which 63 * included support for the VME adapter only. (no reselection). 64 * 65 * Gordon Ross added support for the OBIO adapter, and re-worked 66 * both the VME and OBIO code to support disconnect/reselect. 67 * (Required figuring out the hardware "features" noted above.) 68 * 69 * The autoconfiguration boilerplate came from Adam Glass. 70 */ 71 72 #include <sys/cdefs.h> 73 __KERNEL_RCSID(0, "$NetBSD: si.c,v 1.61.2.1 2008/05/18 12:32:54 yamt Exp $"); 74 75 #include <sys/param.h> 76 #include <sys/systm.h> 77 #include <sys/errno.h> 78 #include <sys/kernel.h> 79 #include <sys/malloc.h> 80 #include <sys/device.h> 81 #include <sys/buf.h> 82 #include <sys/proc.h> 83 #include <sys/user.h> 84 85 #include <dev/scsipi/scsi_all.h> 86 #include <dev/scsipi/scsipi_all.h> 87 #include <dev/scsipi/scsipi_debug.h> 88 #include <dev/scsipi/scsiconf.h> 89 90 #include <machine/autoconf.h> 91 #include <machine/bus.h> 92 #include <machine/dvma.h> 93 94 /* #define DEBUG XXX */ 95 96 #include <dev/ic/ncr5380reg.h> 97 #include <dev/ic/ncr5380var.h> 98 99 #include "sireg.h" 100 #include "sivar.h" 101 102 /* 103 * Transfers smaller than this are done using PIO 104 * (on assumption they're not worth DMA overhead) 105 */ 106 #define MIN_DMA_LEN 128 107 108 int si_debug = 0; 109 #ifdef DEBUG 110 #endif 111 112 /* How long to wait for DMA before declaring an error. */ 113 int si_dma_intr_timo = 500; /* ticks (sec. X 100) */ 114 115 static void si_minphys(struct buf *); 116 117 /* 118 * New-style autoconfig attachment. The cfattach 119 * structures are in si_obio.c and si_vme.c 120 */ 121 122 void 123 si_attach(struct si_softc *sc) 124 { 125 struct ncr5380_softc *ncr_sc = &sc->ncr_sc; 126 volatile struct si_regs *regs = sc->sc_regs; 127 int i; 128 129 /* 130 * Support the "options" (config file flags). 131 * Disconnect/reselect is a per-target mask. 132 * Interrupts and DMA are per-controller. 133 */ 134 ncr_sc->sc_no_disconnect = 135 (sc->sc_options & SI_NO_DISCONNECT); 136 ncr_sc->sc_parity_disable = 137 (sc->sc_options & SI_NO_PARITY_CHK) >> 8; 138 if (sc->sc_options & SI_FORCE_POLLING) 139 ncr_sc->sc_flags |= NCR5380_FORCE_POLLING; 140 141 #if 1 /* XXX - Temporary */ 142 /* XXX - In case we think DMA is completely broken... */ 143 if (sc->sc_options & SI_DISABLE_DMA) { 144 /* Override this function pointer. */ 145 ncr_sc->sc_dma_alloc = NULL; 146 } 147 #endif 148 ncr_sc->sc_min_dma_len = MIN_DMA_LEN; 149 150 /* 151 * Initialize fields used by the MI code 152 */ 153 ncr_sc->sci_r0 = ®s->sci.sci_r0; 154 ncr_sc->sci_r1 = ®s->sci.sci_r1; 155 ncr_sc->sci_r2 = ®s->sci.sci_r2; 156 ncr_sc->sci_r3 = ®s->sci.sci_r3; 157 ncr_sc->sci_r4 = ®s->sci.sci_r4; 158 ncr_sc->sci_r5 = ®s->sci.sci_r5; 159 ncr_sc->sci_r6 = ®s->sci.sci_r6; 160 ncr_sc->sci_r7 = ®s->sci.sci_r7; 161 162 ncr_sc->sc_rev = NCR_VARIANT_NCR5380; 163 164 /* 165 * Allocate DMA handles. 166 */ 167 i = SCI_OPENINGS * sizeof(struct si_dma_handle); 168 sc->sc_dma = (struct si_dma_handle *) 169 malloc(i, M_DEVBUF, M_WAITOK); 170 if (sc->sc_dma == NULL) 171 panic("si: dvma_malloc failed"); 172 for (i = 0; i < SCI_OPENINGS; i++) 173 sc->sc_dma[i].dh_flags = 0; 174 175 ncr_sc->sc_channel.chan_id = 7; 176 ncr_sc->sc_adapter.adapt_minphys = si_minphys; 177 178 /* 179 * Initialize si board itself. 180 */ 181 ncr5380_attach(ncr_sc); 182 } 183 184 static void 185 si_minphys(struct buf *bp) 186 { 187 188 if (bp->b_bcount > MAX_DMA_LEN) { 189 #ifdef DEBUG 190 if (si_debug) { 191 printf("%s len = 0x%x.\n", __func__, bp->b_bcount); 192 Debugger(); 193 } 194 #endif 195 bp->b_bcount = MAX_DMA_LEN; 196 } 197 minphys(bp); 198 } 199 200 201 #define CSR_WANT (SI_CSR_SBC_IP | SI_CSR_DMA_IP | \ 202 SI_CSR_DMA_CONFLICT | SI_CSR_DMA_BUS_ERR ) 203 204 int 205 si_intr(void *arg) 206 { 207 struct si_softc *sc = arg; 208 volatile struct si_regs *si = sc->sc_regs; 209 int dma_error, claimed; 210 u_short csr; 211 212 claimed = 0; 213 dma_error = 0; 214 215 /* SBC interrupt? DMA interrupt? */ 216 csr = si->si_csr; 217 NCR_TRACE("si_intr: csr=0x%x\n", csr); 218 219 if (csr & SI_CSR_DMA_CONFLICT) { 220 dma_error |= SI_CSR_DMA_CONFLICT; 221 printf("%s: DMA conflict\n", __func__); 222 } 223 if (csr & SI_CSR_DMA_BUS_ERR) { 224 dma_error |= SI_CSR_DMA_BUS_ERR; 225 printf("%s: DMA bus error\n", __func__); 226 } 227 if (dma_error) { 228 if (sc->ncr_sc.sc_state & NCR_DOINGDMA) 229 sc->ncr_sc.sc_state |= NCR_ABORTING; 230 /* Make sure we will call the main isr. */ 231 csr |= SI_CSR_DMA_IP; 232 } 233 234 if (csr & (SI_CSR_SBC_IP | SI_CSR_DMA_IP)) { 235 claimed = ncr5380_intr(&sc->ncr_sc); 236 #ifdef DEBUG 237 if (!claimed) { 238 printf("%s: spurious from SBC\n", __func__); 239 if (si_debug & 4) 240 Debugger(); /* XXX */ 241 } 242 #endif 243 /* Yes, we DID cause this interrupt. */ 244 claimed = 1; 245 } 246 247 return claimed; 248 } 249 250 251 /***************************************************************** 252 * Common functions for DMA 253 ****************************************************************/ 254 255 /* 256 * Allocate a DMA handle and put it in sc->sc_dma. Prepare 257 * for DMA transfer. On the Sun3, this means mapping the buffer 258 * into DVMA space. dvma_mapin() flushes the cache for us. 259 */ 260 void 261 si_dma_alloc(struct ncr5380_softc *ncr_sc) 262 { 263 struct si_softc *sc = (struct si_softc *)ncr_sc; 264 struct sci_req *sr = ncr_sc->sc_current; 265 struct scsipi_xfer *xs = sr->sr_xs; 266 struct si_dma_handle *dh; 267 int i, xlen; 268 void *addr; 269 270 #ifdef DIAGNOSTIC 271 if (sr->sr_dma_hand != NULL) 272 panic("%s: already have DMA handle", __func__); 273 #endif 274 275 addr = ncr_sc->sc_dataptr; 276 xlen = ncr_sc->sc_datalen; 277 278 /* If the DMA start addr is misaligned then do PIO */ 279 if (((vaddr_t)addr & 1) || (xlen & 1)) { 280 printf("%s: misaligned.\n", __func__); 281 return; 282 } 283 284 /* Make sure our caller checked sc_min_dma_len. */ 285 if (xlen < MIN_DMA_LEN) 286 panic("%s: xlen=0x%x", __func__, xlen); 287 288 /* 289 * Never attempt single transfers of more than 63k, because 290 * our count register may be only 16 bits (an OBIO adapter). 291 * This should never happen since already bounded by minphys(). 292 * XXX - Should just segment these... 293 */ 294 if (xlen > MAX_DMA_LEN) { 295 printf("%s: excessive xlen=0x%x\n", __func__, xlen); 296 Debugger(); 297 ncr_sc->sc_datalen = xlen = MAX_DMA_LEN; 298 } 299 300 /* Find free DMA handle. Guaranteed to find one since we have 301 as many DMA handles as the driver has processes. */ 302 for (i = 0; i < SCI_OPENINGS; i++) { 303 if ((sc->sc_dma[i].dh_flags & SIDH_BUSY) == 0) 304 goto found; 305 } 306 panic("si: no free DMA handles."); 307 found: 308 309 dh = &sc->sc_dma[i]; 310 dh->dh_flags = SIDH_BUSY; 311 312 if (bus_dmamap_load(sc->sc_dmat, sc->sc_dmap, addr, xlen, NULL, 313 BUS_DMA_NOWAIT) != 0) 314 panic("%s: can't load dmamap", device_xname(ncr_sc->sc_dev)); 315 dh->dh_dmaaddr = sc->sc_dmap->dm_segs[0].ds_addr; 316 dh->dh_dmalen = xlen; 317 318 /* Copy the "write" flag for convenience. */ 319 if (xs->xs_control & XS_CTL_DATA_OUT) 320 dh->dh_flags |= SIDH_OUT; 321 322 bus_dmamap_sync(sc->sc_dmat, sc->sc_dmap, 0, dh->dh_dmalen, 323 (dh->dh_flags & SIDH_OUT) == 0 ? 324 BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE); 325 326 #if 0 327 /* 328 * Some machines might not need to remap B_PHYS buffers. 329 * The sun3 does not map B_PHYS buffers into DVMA space, 330 * (they are mapped into normal KV space) so on the sun3 331 * we must always remap to a DVMA address here. Re-map is 332 * cheap anyway, because it's done by segments, not pages. 333 */ 334 if (xs->bp && (xs->bp->b_flags & B_PHYS)) 335 dh->dh_flags |= SIDH_PHYS; 336 #endif 337 338 /* success */ 339 sr->sr_dma_hand = dh; 340 341 return; 342 } 343 344 345 void 346 si_dma_free(struct ncr5380_softc *ncr_sc) 347 { 348 struct si_softc *sc = (struct si_softc *)ncr_sc; 349 struct sci_req *sr = ncr_sc->sc_current; 350 struct si_dma_handle *dh = sr->sr_dma_hand; 351 352 #ifdef DIAGNOSTIC 353 if (dh == NULL) 354 panic("%s: no DMA handle", __func__); 355 #endif 356 357 if (ncr_sc->sc_state & NCR_DOINGDMA) 358 panic("%s: free while in progress", __func__); 359 360 if (dh->dh_flags & SIDH_BUSY) { 361 bus_dmamap_sync(sc->sc_dmat, sc->sc_dmap, 0, dh->dh_dmalen, 362 (dh->dh_flags & SIDH_OUT) == 0 ? 363 BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 364 bus_dmamap_unload(sc->sc_dmat, sc->sc_dmap); 365 dh->dh_dmaaddr = 0; 366 dh->dh_flags = 0; 367 } 368 sr->sr_dma_hand = NULL; 369 } 370 371 372 #define CSR_MASK (SI_CSR_SBC_IP | SI_CSR_DMA_IP | \ 373 SI_CSR_DMA_CONFLICT | SI_CSR_DMA_BUS_ERR) 374 #define POLL_TIMO 50000 /* X100 = 5 sec. */ 375 376 /* 377 * Poll (spin-wait) for DMA completion. 378 * Called right after xx_dma_start(), and 379 * xx_dma_stop() will be called next. 380 * Same for either VME or OBIO. 381 */ 382 void 383 si_dma_poll(struct ncr5380_softc *ncr_sc) 384 { 385 struct si_softc *sc = (struct si_softc *)ncr_sc; 386 struct sci_req *sr = ncr_sc->sc_current; 387 volatile struct si_regs *si = sc->sc_regs; 388 int tmo; 389 390 /* Make sure DMA started successfully. */ 391 if (ncr_sc->sc_state & NCR_ABORTING) 392 return; 393 394 /* 395 * XXX: The Sun driver waits for ~SI_CSR_DMA_ACTIVE here 396 * XXX: (on obio) or even worse (on vme) a 10mS. delay! 397 * XXX: I really doubt that is necessary... 398 */ 399 400 /* Wait for any "DMA complete" or error bits. */ 401 tmo = POLL_TIMO; 402 for (;;) { 403 if (si->si_csr & CSR_MASK) 404 break; 405 if (--tmo <= 0) { 406 printf("si: DMA timeout (while polling)\n"); 407 /* Indicate timeout as MI code would. */ 408 sr->sr_flags |= SR_OVERDUE; 409 break; 410 } 411 delay(100); 412 } 413 NCR_TRACE("si_dma_poll: waited %d\n", 414 POLL_TIMO - tmo); 415 416 #ifdef DEBUG 417 if (si_debug & 2) { 418 printf("%s: done, csr=0x%x\n", __func__, si->si_csr); 419 } 420 #endif 421 } 422
Indexes created Mon Oct 13 16:09:52 GMT 2025