si.c revision 1.61.4.2
1 /* $NetBSD: si.c,v 1.61.4.2 2010/03/11 15:03:03 yamt Exp $ */ 2 3 /*- 4 * Copyright (c) 1996 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Adam Glass, David Jones, and Gordon W. Ross. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 /* 33 * This file contains only the machine-dependent parts of the 34 * Sun3 SCSI driver. (Autoconfig stuff and DMA functions.) 35 * The machine-independent parts are in ncr5380sbc.c 36 * 37 * Supported hardware includes: 38 * Sun SCSI-3 on OBIO (Sun3/50,Sun3/60) 39 * Sun SCSI-3 on VME (Sun3/160,Sun3/260) 40 * 41 * Could be made to support the Sun3/E if someone wanted to. 42 * 43 * Note: Both supported variants of the Sun SCSI-3 adapter have 44 * some really unusual "features" for this driver to deal with, 45 * generally related to the DMA engine. The OBIO variant will 46 * ignore any attempt to write the FIFO count register while the 47 * SCSI bus is in DATA_IN or DATA_OUT phase. This is dealt with 48 * by setting the FIFO count early in COMMAND or MSG_IN phase. 49 * 50 * The VME variant has a bit to enable or disable the DMA engine, 51 * but that bit also gates the interrupt line from the NCR5380! 52 * Therefore, in order to get any interrupt from the 5380, (i.e. 53 * for reselect) one must clear the DMA engine transfer count and 54 * then enable DMA. This has the further complication that you 55 * CAN NOT touch the NCR5380 while the DMA enable bit is set, so 56 * we have to turn DMA back off before we even look at the 5380. 57 * 58 * What wonderfully whacky hardware this is! 59 * 60 * Credits, history: 61 * 62 * David Jones wrote the initial version of this module, which 63 * included support for the VME adapter only. (no reselection). 64 * 65 * Gordon Ross added support for the OBIO adapter, and re-worked 66 * both the VME and OBIO code to support disconnect/reselect. 67 * (Required figuring out the hardware "features" noted above.) 68 * 69 * The autoconfiguration boilerplate came from Adam Glass. 70 */ 71 72 #include <sys/cdefs.h> 73 __KERNEL_RCSID(0, "$NetBSD: si.c,v 1.61.4.2 2010/03/11 15:03:03 yamt Exp $"); 74 75 #include <sys/param.h> 76 #include <sys/systm.h> 77 #include <sys/errno.h> 78 #include <sys/kernel.h> 79 #include <sys/malloc.h> 80 #include <sys/device.h> 81 #include <sys/buf.h> 82 #include <sys/proc.h> 83 84 #include <dev/scsipi/scsi_all.h> 85 #include <dev/scsipi/scsipi_all.h> 86 #include <dev/scsipi/scsipi_debug.h> 87 #include <dev/scsipi/scsiconf.h> 88 89 #include <machine/autoconf.h> 90 #include <machine/bus.h> 91 #include <machine/dvma.h> 92 93 /* #define DEBUG XXX */ 94 95 #include <dev/ic/ncr5380reg.h> 96 #include <dev/ic/ncr5380var.h> 97 98 #include "sireg.h" 99 #include "sivar.h" 100 101 /* 102 * Transfers smaller than this are done using PIO 103 * (on assumption they're not worth DMA overhead) 104 */ 105 #define MIN_DMA_LEN 128 106 107 int si_debug = 0; 108 #ifdef DEBUG 109 #endif 110 111 /* How long to wait for DMA before declaring an error. */ 112 int si_dma_intr_timo = 500; /* ticks (sec. X 100) */ 113 114 static void si_minphys(struct buf *); 115 116 /* 117 * New-style autoconfig attachment. The cfattach 118 * structures are in si_obio.c and si_vme.c 119 */ 120 121 void 122 si_attach(struct si_softc *sc) 123 { 124 struct ncr5380_softc *ncr_sc = &sc->ncr_sc; 125 volatile struct si_regs *regs = sc->sc_regs; 126 int i; 127 128 /* 129 * Support the "options" (config file flags). 130 * Disconnect/reselect is a per-target mask. 131 * Interrupts and DMA are per-controller. 132 */ 133 ncr_sc->sc_no_disconnect = 134 (sc->sc_options & SI_NO_DISCONNECT); 135 ncr_sc->sc_parity_disable = 136 (sc->sc_options & SI_NO_PARITY_CHK) >> 8; 137 if (sc->sc_options & SI_FORCE_POLLING) 138 ncr_sc->sc_flags |= NCR5380_FORCE_POLLING; 139 140 #if 1 /* XXX - Temporary */ 141 /* XXX - In case we think DMA is completely broken... */ 142 if (sc->sc_options & SI_DISABLE_DMA) { 143 /* Override this function pointer. */ 144 ncr_sc->sc_dma_alloc = NULL; 145 } 146 #endif 147 ncr_sc->sc_min_dma_len = MIN_DMA_LEN; 148 149 /* 150 * Initialize fields used by the MI code 151 */ 152 ncr_sc->sci_r0 = ®s->sci.sci_r0; 153 ncr_sc->sci_r1 = ®s->sci.sci_r1; 154 ncr_sc->sci_r2 = ®s->sci.sci_r2; 155 ncr_sc->sci_r3 = ®s->sci.sci_r3; 156 ncr_sc->sci_r4 = ®s->sci.sci_r4; 157 ncr_sc->sci_r5 = ®s->sci.sci_r5; 158 ncr_sc->sci_r6 = ®s->sci.sci_r6; 159 ncr_sc->sci_r7 = ®s->sci.sci_r7; 160 161 ncr_sc->sc_rev = NCR_VARIANT_NCR5380; 162 163 /* 164 * Allocate DMA handles. 165 */ 166 i = SCI_OPENINGS * sizeof(struct si_dma_handle); 167 sc->sc_dma = (struct si_dma_handle *) 168 malloc(i, M_DEVBUF, M_WAITOK); 169 if (sc->sc_dma == NULL) 170 panic("si: dvma_malloc failed"); 171 for (i = 0; i < SCI_OPENINGS; i++) 172 sc->sc_dma[i].dh_flags = 0; 173 174 ncr_sc->sc_channel.chan_id = 7; 175 ncr_sc->sc_adapter.adapt_minphys = si_minphys; 176 177 /* 178 * Initialize si board itself. 179 */ 180 ncr5380_attach(ncr_sc); 181 } 182 183 static void 184 si_minphys(struct buf *bp) 185 { 186 187 if (bp->b_bcount > MAX_DMA_LEN) { 188 #ifdef DEBUG 189 if (si_debug) { 190 printf("%s len = 0x%x.\n", __func__, bp->b_bcount); 191 Debugger(); 192 } 193 #endif 194 bp->b_bcount = MAX_DMA_LEN; 195 } 196 minphys(bp); 197 } 198 199 200 #define CSR_WANT (SI_CSR_SBC_IP | SI_CSR_DMA_IP | \ 201 SI_CSR_DMA_CONFLICT | SI_CSR_DMA_BUS_ERR ) 202 203 int 204 si_intr(void *arg) 205 { 206 struct si_softc *sc = arg; 207 volatile struct si_regs *si = sc->sc_regs; 208 int dma_error, claimed; 209 u_short csr; 210 211 claimed = 0; 212 dma_error = 0; 213 214 /* SBC interrupt? DMA interrupt? */ 215 csr = si->si_csr; 216 NCR_TRACE("si_intr: csr=0x%x\n", csr); 217 218 if (csr & SI_CSR_DMA_CONFLICT) { 219 dma_error |= SI_CSR_DMA_CONFLICT; 220 printf("%s: DMA conflict\n", __func__); 221 } 222 if (csr & SI_CSR_DMA_BUS_ERR) { 223 dma_error |= SI_CSR_DMA_BUS_ERR; 224 printf("%s: DMA bus error\n", __func__); 225 } 226 if (dma_error) { 227 if (sc->ncr_sc.sc_state & NCR_DOINGDMA) 228 sc->ncr_sc.sc_state |= NCR_ABORTING; 229 /* Make sure we will call the main isr. */ 230 csr |= SI_CSR_DMA_IP; 231 } 232 233 if (csr & (SI_CSR_SBC_IP | SI_CSR_DMA_IP)) { 234 claimed = ncr5380_intr(&sc->ncr_sc); 235 #ifdef DEBUG 236 if (!claimed) { 237 printf("%s: spurious from SBC\n", __func__); 238 if (si_debug & 4) 239 Debugger(); /* XXX */ 240 } 241 #endif 242 /* Yes, we DID cause this interrupt. */ 243 claimed = 1; 244 } 245 246 return claimed; 247 } 248 249 250 /***************************************************************** 251 * Common functions for DMA 252 ****************************************************************/ 253 254 /* 255 * Allocate a DMA handle and put it in sc->sc_dma. Prepare 256 * for DMA transfer. On the Sun3, this means mapping the buffer 257 * into DVMA space. dvma_mapin() flushes the cache for us. 258 */ 259 void 260 si_dma_alloc(struct ncr5380_softc *ncr_sc) 261 { 262 struct si_softc *sc = (struct si_softc *)ncr_sc; 263 struct sci_req *sr = ncr_sc->sc_current; 264 struct scsipi_xfer *xs = sr->sr_xs; 265 struct si_dma_handle *dh; 266 int i, xlen; 267 void *addr; 268 269 #ifdef DIAGNOSTIC 270 if (sr->sr_dma_hand != NULL) 271 panic("%s: already have DMA handle", __func__); 272 #endif 273 274 addr = ncr_sc->sc_dataptr; 275 xlen = ncr_sc->sc_datalen; 276 277 /* If the DMA start addr is misaligned then do PIO */ 278 if (((vaddr_t)addr & 1) || (xlen & 1)) { 279 printf("%s: misaligned.\n", __func__); 280 return; 281 } 282 283 /* Make sure our caller checked sc_min_dma_len. */ 284 if (xlen < MIN_DMA_LEN) 285 panic("%s: xlen=0x%x", __func__, xlen); 286 287 /* 288 * Never attempt single transfers of more than 63k, because 289 * our count register may be only 16 bits (an OBIO adapter). 290 * This should never happen since already bounded by minphys(). 291 * XXX - Should just segment these... 292 */ 293 if (xlen > MAX_DMA_LEN) { 294 printf("%s: excessive xlen=0x%x\n", __func__, xlen); 295 Debugger(); 296 ncr_sc->sc_datalen = xlen = MAX_DMA_LEN; 297 } 298 299 /* Find free DMA handle. Guaranteed to find one since we have 300 as many DMA handles as the driver has processes. */ 301 for (i = 0; i < SCI_OPENINGS; i++) { 302 if ((sc->sc_dma[i].dh_flags & SIDH_BUSY) == 0) 303 goto found; 304 } 305 panic("si: no free DMA handles."); 306 found: 307 308 dh = &sc->sc_dma[i]; 309 dh->dh_flags = SIDH_BUSY; 310 311 if (bus_dmamap_load(sc->sc_dmat, sc->sc_dmap, addr, xlen, NULL, 312 BUS_DMA_NOWAIT) != 0) 313 panic("%s: can't load dmamap", device_xname(ncr_sc->sc_dev)); 314 dh->dh_dmaaddr = sc->sc_dmap->dm_segs[0].ds_addr; 315 dh->dh_dmalen = xlen; 316 317 /* Copy the "write" flag for convenience. */ 318 if (xs->xs_control & XS_CTL_DATA_OUT) 319 dh->dh_flags |= SIDH_OUT; 320 321 bus_dmamap_sync(sc->sc_dmat, sc->sc_dmap, 0, dh->dh_dmalen, 322 (dh->dh_flags & SIDH_OUT) == 0 ? 323 BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE); 324 325 #if 0 326 /* 327 * Some machines might not need to remap B_PHYS buffers. 328 * The sun3 does not map B_PHYS buffers into DVMA space, 329 * (they are mapped into normal KV space) so on the sun3 330 * we must always remap to a DVMA address here. Re-map is 331 * cheap anyway, because it's done by segments, not pages. 332 */ 333 if (xs->bp && (xs->bp->b_flags & B_PHYS)) 334 dh->dh_flags |= SIDH_PHYS; 335 #endif 336 337 /* success */ 338 sr->sr_dma_hand = dh; 339 340 return; 341 } 342 343 344 void 345 si_dma_free(struct ncr5380_softc *ncr_sc) 346 { 347 struct si_softc *sc = (struct si_softc *)ncr_sc; 348 struct sci_req *sr = ncr_sc->sc_current; 349 struct si_dma_handle *dh = sr->sr_dma_hand; 350 351 #ifdef DIAGNOSTIC 352 if (dh == NULL) 353 panic("%s: no DMA handle", __func__); 354 #endif 355 356 if (ncr_sc->sc_state & NCR_DOINGDMA) 357 panic("%s: free while in progress", __func__); 358 359 if (dh->dh_flags & SIDH_BUSY) { 360 bus_dmamap_sync(sc->sc_dmat, sc->sc_dmap, 0, dh->dh_dmalen, 361 (dh->dh_flags & SIDH_OUT) == 0 ? 362 BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 363 bus_dmamap_unload(sc->sc_dmat, sc->sc_dmap); 364 dh->dh_dmaaddr = 0; 365 dh->dh_flags = 0; 366 } 367 sr->sr_dma_hand = NULL; 368 } 369 370 371 #define CSR_MASK (SI_CSR_SBC_IP | SI_CSR_DMA_IP | \ 372 SI_CSR_DMA_CONFLICT | SI_CSR_DMA_BUS_ERR) 373 #define POLL_TIMO 50000 /* X100 = 5 sec. */ 374 375 /* 376 * Poll (spin-wait) for DMA completion. 377 * Called right after xx_dma_start(), and 378 * xx_dma_stop() will be called next. 379 * Same for either VME or OBIO. 380 */ 381 void 382 si_dma_poll(struct ncr5380_softc *ncr_sc) 383 { 384 struct si_softc *sc = (struct si_softc *)ncr_sc; 385 struct sci_req *sr = ncr_sc->sc_current; 386 volatile struct si_regs *si = sc->sc_regs; 387 int tmo; 388 389 /* Make sure DMA started successfully. */ 390 if (ncr_sc->sc_state & NCR_ABORTING) 391 return; 392 393 /* 394 * XXX: The Sun driver waits for ~SI_CSR_DMA_ACTIVE here 395 * XXX: (on obio) or even worse (on vme) a 10mS. delay! 396 * XXX: I really doubt that is necessary... 397 */ 398 399 /* Wait for any "DMA complete" or error bits. */ 400 tmo = POLL_TIMO; 401 for (;;) { 402 if (si->si_csr & CSR_MASK) 403 break; 404 if (--tmo <= 0) { 405 printf("si: DMA timeout (while polling)\n"); 406 /* Indicate timeout as MI code would. */ 407 sr->sr_flags |= SR_OVERDUE; 408 break; 409 } 410 delay(100); 411 } 412 NCR_TRACE("si_dma_poll: waited %d\n", 413 POLL_TIMO - tmo); 414 415 #ifdef DEBUG 416 if (si_debug & 2) { 417 printf("%s: done, csr=0x%x\n", __func__, si->si_csr); 418 } 419 #endif 420 } 421
Indexes created Mon Oct 13 08:09:50 GMT 2025