si_obio.c revision 1.13
1 /* $NetBSD: si_obio.c,v 1.13 1997/07/29 06:43:53 fair Exp $ */ 2 3 /*- 4 * Copyright (c) 1996 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Adam Glass, David Jones, and Gordon W. Ross. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 /* 40 * This file contains only the machine-dependent parts of the 41 * Sun3 SCSI driver. (Autoconfig stuff and DMA functions.) 42 * The machine-independent parts are in ncr5380sbc.c 43 * 44 * Supported hardware includes: 45 * Sun SCSI-3 on OBIO (Sun3/50,Sun3/60) 46 * Sun SCSI-3 on VME (Sun3/160,Sun3/260) 47 * 48 * Could be made to support the Sun3/E if someone wanted to. 49 * 50 * Note: Both supported variants of the Sun SCSI-3 adapter have 51 * some really unusual "features" for this driver to deal with, 52 * generally related to the DMA engine. The OBIO variant will 53 * ignore any attempt to write the FIFO count register while the 54 * SCSI bus is in DATA_IN or DATA_OUT phase. This is dealt with 55 * by setting the FIFO count early in COMMAND or MSG_IN phase. 56 * 57 * The VME variant has a bit to enable or disable the DMA engine, 58 * but that bit also gates the interrupt line from the NCR5380! 59 * Therefore, in order to get any interrupt from the 5380, (i.e. 60 * for reselect) one must clear the DMA engine transfer count and 61 * then enable DMA. This has the further complication that you 62 * CAN NOT touch the NCR5380 while the DMA enable bit is set, so 63 * we have to turn DMA back off before we even look at the 5380. 64 * 65 * What wonderfully whacky hardware this is! 66 * 67 * Credits, history: 68 * 69 * David Jones wrote the initial version of this module, which 70 * included support for the VME adapter only. (no reselection). 71 * 72 * Gordon Ross added support for the OBIO adapter, and re-worked 73 * both the VME and OBIO code to support disconnect/reselect. 74 * (Required figuring out the hardware "features" noted above.) 75 * 76 * The autoconfiguration boilerplate came from Adam Glass. 77 */ 78 79 /***************************************************************** 80 * OBIO functions for DMA 81 ****************************************************************/ 82 83 #include <sys/param.h> 84 #include <sys/systm.h> 85 #include <sys/errno.h> 86 #include <sys/kernel.h> 87 #include <sys/malloc.h> 88 #include <sys/device.h> 89 #include <sys/buf.h> 90 #include <sys/proc.h> 91 #include <sys/user.h> 92 93 #include <scsi/scsi_all.h> 94 #include <scsi/scsi_debug.h> 95 #include <scsi/scsiconf.h> 96 97 #include <machine/autoconf.h> 98 #include <machine/obio.h> 99 #include <machine/dvma.h> 100 101 #define DEBUG XXX 102 103 #include <dev/ic/ncr5380reg.h> 104 #include <dev/ic/ncr5380var.h> 105 106 #include "sireg.h" 107 #include "sivar.h" 108 #include "am9516.h" 109 110 /* 111 * How many uS. to delay after touching the am9516 UDC. 112 */ 113 #define UDC_WAIT_USEC 5 114 115 void si_obio_dma_setup __P((struct ncr5380_softc *)); 116 void si_obio_dma_start __P((struct ncr5380_softc *)); 117 void si_obio_dma_eop __P((struct ncr5380_softc *)); 118 void si_obio_dma_stop __P((struct ncr5380_softc *)); 119 120 static __inline__ void si_obio_udc_write 121 __P((volatile struct si_regs *si, int regnum, int value)); 122 static __inline__ int si_obio_udc_read 123 __P((volatile struct si_regs *si, int regnum)); 124 125 126 /* 127 * New-style autoconfig attachment 128 */ 129 130 static int si_obio_match __P((struct device *, struct cfdata *, void *)); 131 static void si_obio_attach __P((struct device *, struct device *, void *)); 132 133 struct cfattach si_obio_ca = { 134 sizeof(struct si_softc), si_obio_match, si_obio_attach 135 }; 136 137 /* 138 * Options for disconnect/reselect, DMA, and interrupts. 139 * By default, allow disconnect/reselect on targets 4-6. 140 * Those are normally tapes that really need it enabled. 141 * 142 * XXX - Leave interrupts disabled for now, to avoid the 143 * not-yet-identified "everything dumps core" bug... 144 */ 145 int si_obio_options = SI_FORCE_POLLING | 0x0f; 146 147 148 static int 149 si_obio_match(parent, cf, args) 150 struct device *parent; 151 struct cfdata *cf; 152 void *args; 153 { 154 struct confargs *ca = args; 155 156 /* We use obio_mapin(), so require OBIO. */ 157 if (ca->ca_bustype != BUS_OBIO) 158 return (0); 159 160 /* Make sure there is something there... */ 161 if (bus_peek(ca->ca_bustype, ca->ca_paddr + 1, 1) == -1) 162 return (0); 163 164 /* Default interrupt priority. */ 165 if (ca->ca_intpri == -1) 166 ca->ca_intpri = 2; 167 168 return (1); 169 } 170 171 static void 172 si_obio_attach(parent, self, args) 173 struct device *parent, *self; 174 void *args; 175 { 176 struct si_softc *sc = (struct si_softc *) self; 177 struct ncr5380_softc *ncr_sc = &sc->ncr_sc; 178 struct cfdata *cf = self->dv_cfdata; 179 struct confargs *ca = args; 180 181 /* Get options from config flags if specified. */ 182 if (cf->cf_flags) 183 sc->sc_options = cf->cf_flags; 184 else 185 sc->sc_options = si_obio_options; 186 187 printf(": options=0x%x\n", sc->sc_options); 188 189 sc->sc_adapter_type = ca->ca_bustype; 190 sc->sc_regs = (struct si_regs *) 191 obio_mapin(ca->ca_paddr, sizeof(struct si_regs)); 192 193 /* 194 * MD function pointers used by the MI code. 195 */ 196 ncr_sc->sc_pio_out = ncr5380_pio_out; 197 ncr_sc->sc_pio_in = ncr5380_pio_in; 198 ncr_sc->sc_dma_alloc = si_dma_alloc; 199 ncr_sc->sc_dma_free = si_dma_free; 200 ncr_sc->sc_dma_setup = si_obio_dma_setup; 201 ncr_sc->sc_dma_start = si_obio_dma_start; 202 ncr_sc->sc_dma_poll = si_dma_poll; 203 ncr_sc->sc_dma_eop = si_obio_dma_eop; 204 ncr_sc->sc_dma_stop = si_obio_dma_stop; 205 ncr_sc->sc_intr_on = NULL; 206 ncr_sc->sc_intr_off = NULL; 207 208 /* Need DVMA-capable memory for the UDC command block. */ 209 sc->sc_dmacmd = dvma_malloc(sizeof (struct udc_table)); 210 211 /* Attach interrupt handler. */ 212 isr_add_autovect(si_intr, (void *)sc, ca->ca_intpri); 213 214 /* Do the common attach stuff. */ 215 si_attach(sc); 216 } 217 218 219 static __inline__ void 220 si_obio_udc_write(si, regnum, value) 221 volatile struct si_regs *si; 222 int regnum, value; 223 { 224 si->udc_addr = regnum; 225 delay(UDC_WAIT_USEC); 226 si->udc_data = value; 227 delay(UDC_WAIT_USEC); 228 } 229 230 static __inline__ int 231 si_obio_udc_read(si, regnum) 232 volatile struct si_regs *si; 233 int regnum; 234 { 235 int value; 236 237 si->udc_addr = regnum; 238 delay(UDC_WAIT_USEC); 239 value = si->udc_data; 240 delay(UDC_WAIT_USEC); 241 242 return (value); 243 } 244 245 246 /* 247 * This function is called during the COMMAND or MSG_IN phase 248 * that preceeds a DATA_IN or DATA_OUT phase, in case we need 249 * to setup the DMA engine before the bus enters a DATA phase. 250 * 251 * The OBIO "si" IGNORES any attempt to set the FIFO count 252 * register after the SCSI bus goes into any DATA phase, so 253 * this function has to setup the evil FIFO logic. 254 */ 255 void 256 si_obio_dma_setup(ncr_sc) 257 struct ncr5380_softc *ncr_sc; 258 { 259 struct si_softc *sc = (struct si_softc *)ncr_sc; 260 struct sci_req *sr = ncr_sc->sc_current; 261 struct si_dma_handle *dh = sr->sr_dma_hand; 262 volatile struct si_regs *si = sc->sc_regs; 263 struct udc_table *cmd; 264 long data_pa, cmd_pa; 265 int xlen; 266 267 /* 268 * Get the DVMA mapping for this segment. 269 * XXX - Should separate allocation and mapin. 270 */ 271 data_pa = dvma_kvtopa(dh->dh_dvma, sc->sc_adapter_type); 272 data_pa += (ncr_sc->sc_dataptr - dh->dh_addr); 273 if (data_pa & 1) 274 panic("si_dma_start: bad pa=0x%lx", data_pa); 275 xlen = ncr_sc->sc_datalen; 276 sc->sc_reqlen = xlen; /* XXX: or less? */ 277 278 #ifdef DEBUG 279 if (si_debug & 2) { 280 printf("si_dma_setup: dh=%p, pa=0x%lx, xlen=0x%x\n", 281 dh, data_pa, xlen); 282 } 283 #endif 284 285 /* Reset the UDC. (In case not already reset?) */ 286 si_obio_udc_write(si, UDC_ADR_COMMAND, UDC_CMD_RESET); 287 288 /* Reset the FIFO */ 289 si->si_csr &= ~SI_CSR_FIFO_RES; /* active low */ 290 si->si_csr |= SI_CSR_FIFO_RES; 291 292 /* Set direction (send/recv) */ 293 if (dh->dh_flags & SIDH_OUT) { 294 si->si_csr |= SI_CSR_SEND; 295 } else { 296 si->si_csr &= ~SI_CSR_SEND; 297 } 298 299 /* Set the FIFO counter. */ 300 si->fifo_count = xlen; 301 302 /* Reset the UDC. */ 303 si_obio_udc_write(si, UDC_ADR_COMMAND, UDC_CMD_RESET); 304 305 /* 306 * XXX: Reset the FIFO again! Comment from Sprite: 307 * Go through reset again becuase of the bug on the 3/50 308 * where bytes occasionally linger in the DMA fifo. 309 */ 310 si->si_csr &= ~SI_CSR_FIFO_RES; /* active low */ 311 si->si_csr |= SI_CSR_FIFO_RES; 312 313 #ifdef DEBUG 314 /* Make sure the extra FIFO reset did not hit the count. */ 315 if (si->fifo_count != xlen) { 316 printf("si_dma_setup: fifo_count=0x%x, xlen=0x%x\n", 317 si->fifo_count, xlen); 318 Debugger(); 319 } 320 #endif 321 322 /* 323 * Set up the DMA controller. The DMA controller on 324 * OBIO needs a command block in DVMA space. 325 */ 326 cmd = sc->sc_dmacmd; 327 cmd->addrh = ((data_pa & 0xFF0000) >> 8) | UDC_ADDR_INFO; 328 cmd->addrl = data_pa & 0xFFFF; 329 cmd->count = xlen / 2; /* bytes -> words */ 330 cmd->cmrh = UDC_CMR_HIGH; 331 if (dh->dh_flags & SIDH_OUT) { 332 if (xlen & 1) 333 cmd->count++; 334 cmd->cmrl = UDC_CMR_LSEND; 335 cmd->rsel = UDC_RSEL_SEND; 336 } else { 337 cmd->cmrl = UDC_CMR_LRECV; 338 cmd->rsel = UDC_RSEL_RECV; 339 } 340 341 /* Tell the DMA chip where the control block is. */ 342 cmd_pa = dvma_kvtopa((long)cmd, BUS_OBIO); 343 si_obio_udc_write(si, UDC_ADR_CAR_HIGH, 344 (cmd_pa & 0xff0000) >> 8); 345 si_obio_udc_write(si, UDC_ADR_CAR_LOW, 346 (cmd_pa & 0xffff)); 347 348 /* Tell the chip to be a DMA master. */ 349 si_obio_udc_write(si, UDC_ADR_MODE, UDC_MODE); 350 351 /* Tell the chip to interrupt on error. */ 352 si_obio_udc_write(si, UDC_ADR_COMMAND, UDC_CMD_CIE); 353 354 /* Will do "start chain" command in _dma_start. */ 355 } 356 357 358 void 359 si_obio_dma_start(ncr_sc) 360 struct ncr5380_softc *ncr_sc; 361 { 362 struct si_softc *sc = (struct si_softc *)ncr_sc; 363 struct sci_req *sr = ncr_sc->sc_current; 364 struct si_dma_handle *dh = sr->sr_dma_hand; 365 volatile struct si_regs *si = sc->sc_regs; 366 int s; 367 368 #ifdef DEBUG 369 if (si_debug & 2) { 370 printf("si_dma_start: sr=%p\n", sr); 371 } 372 #endif 373 374 /* This MAY be time critical (not sure). */ 375 s = splhigh(); 376 377 /* Finally, give the UDC a "start chain" command. */ 378 si_obio_udc_write(si, UDC_ADR_COMMAND, UDC_CMD_STRT_CHN); 379 380 /* 381 * Acknowledge the phase change. (After DMA setup!) 382 * Put the SBIC into DMA mode, and start the transfer. 383 */ 384 if (dh->dh_flags & SIDH_OUT) { 385 *ncr_sc->sci_tcmd = PHASE_DATA_OUT; 386 SCI_CLR_INTR(ncr_sc); 387 *ncr_sc->sci_icmd = SCI_ICMD_DATA; 388 *ncr_sc->sci_mode |= (SCI_MODE_DMA | SCI_MODE_DMA_IE); 389 *ncr_sc->sci_dma_send = 0; /* start it */ 390 } else { 391 *ncr_sc->sci_tcmd = PHASE_DATA_IN; 392 SCI_CLR_INTR(ncr_sc); 393 *ncr_sc->sci_icmd = 0; 394 *ncr_sc->sci_mode |= (SCI_MODE_DMA | SCI_MODE_DMA_IE); 395 *ncr_sc->sci_irecv = 0; /* start it */ 396 } 397 398 splx(s); 399 ncr_sc->sc_state |= NCR_DOINGDMA; 400 401 #ifdef DEBUG 402 if (si_debug & 2) { 403 printf("si_dma_start: started, flags=0x%x\n", 404 ncr_sc->sc_state); 405 } 406 #endif 407 } 408 409 410 void 411 si_obio_dma_eop(ncr_sc) 412 struct ncr5380_softc *ncr_sc; 413 { 414 415 /* Not needed - DMA was stopped prior to examining sci_csr */ 416 } 417 418 419 void 420 si_obio_dma_stop(ncr_sc) 421 struct ncr5380_softc *ncr_sc; 422 { 423 struct si_softc *sc = (struct si_softc *)ncr_sc; 424 struct sci_req *sr = ncr_sc->sc_current; 425 struct si_dma_handle *dh = sr->sr_dma_hand; 426 volatile struct si_regs *si = sc->sc_regs; 427 int resid, ntrans, tmo, udc_cnt; 428 429 if ((ncr_sc->sc_state & NCR_DOINGDMA) == 0) { 430 #ifdef DEBUG 431 printf("si_dma_stop: dma not running\n"); 432 #endif 433 return; 434 } 435 ncr_sc->sc_state &= ~NCR_DOINGDMA; 436 437 NCR_TRACE("si_dma_stop: top, csr=0x%x\n", si->si_csr); 438 439 /* OK, have either phase mis-match or end of DMA. */ 440 /* Set an impossible phase to prevent data movement? */ 441 *ncr_sc->sci_tcmd = PHASE_INVALID; 442 443 /* Check for DMA errors. */ 444 if (si->si_csr & (SI_CSR_DMA_CONFLICT | SI_CSR_DMA_BUS_ERR)) { 445 printf("si: DMA error, csr=0x%x, reset\n", si->si_csr); 446 sr->sr_xs->error = XS_DRIVER_STUFFUP; 447 ncr_sc->sc_state |= NCR_ABORTING; 448 si_reset_adapter(ncr_sc); 449 goto out; 450 } 451 452 /* Note that timeout may have set the error flag. */ 453 if (ncr_sc->sc_state & NCR_ABORTING) 454 goto out; 455 456 /* 457 * After a read, wait for the FIFO to empty. 458 * Note: this only works on the OBIO version. 459 */ 460 if ((dh->dh_flags & SIDH_OUT) == 0) { 461 tmo = 200000; /* X10 = 2 sec. */ 462 for (;;) { 463 if (si->si_csr & SI_CSR_FIFO_EMPTY) 464 break; 465 if (--tmo <= 0) { 466 printf("si: dma fifo did not empty, reset\n"); 467 ncr_sc->sc_state |= NCR_ABORTING; 468 /* si_reset_adapter(ncr_sc); */ 469 goto out; 470 } 471 delay(10); 472 } 473 } 474 475 /* 476 * Now try to figure out how much actually transferred 477 * The fifo_count might not reflect how many bytes were 478 * actually transferred. 479 */ 480 resid = si->fifo_count & 0xFFFF; 481 ntrans = sc->sc_reqlen - resid; 482 483 #ifdef DEBUG 484 if (si_debug & 2) { 485 printf("si_dma_stop: resid=0x%x ntrans=0x%x\n", 486 resid, ntrans); 487 } 488 #endif 489 490 /* XXX: Treat (ntrans==0) as a special, non-error case? */ 491 if (ntrans < MIN_DMA_LEN) { 492 printf("si: fifo count: 0x%x\n", resid); 493 ncr_sc->sc_state |= NCR_ABORTING; 494 goto out; 495 } 496 if (ntrans > ncr_sc->sc_datalen) 497 panic("si_dma_stop: excess transfer"); 498 499 /* Adjust data pointer */ 500 ncr_sc->sc_dataptr += ntrans; 501 ncr_sc->sc_datalen -= ntrans; 502 503 /* 504 * After a read, we may need to clean-up 505 * "Left-over bytes" (yuck!) 506 */ 507 if ((dh->dh_flags & SIDH_OUT) == 0) { 508 /* If odd transfer count, grab last byte by hand. */ 509 if (ntrans & 1) { 510 NCR_TRACE("si_dma_stop: leftover 1 at 0x%x\n", 511 (int) ncr_sc->sc_dataptr - 1); 512 ncr_sc->sc_dataptr[-1] = 513 (si->fifo_data & 0xff00) >> 8; 514 goto out; 515 } 516 /* UDC might not have transfered the last word. */ 517 udc_cnt = si_obio_udc_read(si, UDC_ADR_COUNT); 518 if (((udc_cnt * 2) - resid) == 2) { 519 NCR_TRACE("si_dma_stop: leftover 2 at 0x%x\n", 520 (int) ncr_sc->sc_dataptr - 2); 521 ncr_sc->sc_dataptr[-2] = 522 (si->fifo_data & 0xff00) >> 8; 523 ncr_sc->sc_dataptr[-1] = 524 (si->fifo_data & 0x00ff); 525 } 526 } 527 528 out: 529 /* Reset the UDC. */ 530 si_obio_udc_write(si, UDC_ADR_COMMAND, UDC_CMD_RESET); 531 si->fifo_count = 0; 532 si->si_csr &= ~SI_CSR_SEND; 533 534 /* Reset the FIFO */ 535 si->si_csr &= ~SI_CSR_FIFO_RES; /* active low */ 536 si->si_csr |= SI_CSR_FIFO_RES; 537 538 /* Put SBIC back in PIO mode. */ 539 /* XXX: set tcmd to PHASE_INVALID? */ 540 *ncr_sc->sci_mode &= ~(SCI_MODE_DMA | SCI_MODE_DMA_IE); 541 *ncr_sc->sci_icmd = 0; 542 } 543 544
Indexes created Tue Sep 30 20:09:53 GMT 2025