si_obio.c revision 1.8
1 /* $NetBSD: si_obio.c,v 1.8 1996/12/17 21:10:54 gwr Exp $ */ 2 3 /*- 4 * Copyright (c) 1996 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Adam Glass, David Jones, and Gordon W. Ross. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE 30 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 /* 40 * This file contains only the machine-dependent parts of the 41 * Sun3 SCSI driver. (Autoconfig stuff and DMA functions.) 42 * The machine-independent parts are in ncr5380sbc.c 43 * 44 * Supported hardware includes: 45 * Sun SCSI-3 on OBIO (Sun3/50,Sun3/60) 46 * Sun SCSI-3 on VME (Sun3/160,Sun3/260) 47 * 48 * Could be made to support the Sun3/E if someone wanted to. 49 * 50 * Note: Both supported variants of the Sun SCSI-3 adapter have 51 * some really unusual "features" for this driver to deal with, 52 * generally related to the DMA engine. The OBIO variant will 53 * ignore any attempt to write the FIFO count register while the 54 * SCSI bus is in DATA_IN or DATA_OUT phase. This is dealt with 55 * by setting the FIFO count early in COMMAND or MSG_IN phase. 56 * 57 * The VME variant has a bit to enable or disable the DMA engine, 58 * but that bit also gates the interrupt line from the NCR5380! 59 * Therefore, in order to get any interrupt from the 5380, (i.e. 60 * for reselect) one must clear the DMA engine transfer count and 61 * then enable DMA. This has the further complication that you 62 * CAN NOT touch the NCR5380 while the DMA enable bit is set, so 63 * we have to turn DMA back off before we even look at the 5380. 64 * 65 * What wonderfully whacky hardware this is! 66 * 67 * Credits, history: 68 * 69 * David Jones wrote the initial version of this module, which 70 * included support for the VME adapter only. (no reselection). 71 * 72 * Gordon Ross added support for the OBIO adapter, and re-worked 73 * both the VME and OBIO code to support disconnect/reselect. 74 * (Required figuring out the hardware "features" noted above.) 75 * 76 * The autoconfiguration boilerplate came from Adam Glass. 77 */ 78 79 /***************************************************************** 80 * OBIO functions for DMA 81 ****************************************************************/ 82 83 #include <sys/param.h> 84 #include <sys/systm.h> 85 #include <sys/errno.h> 86 #include <sys/kernel.h> 87 #include <sys/malloc.h> 88 #include <sys/device.h> 89 #include <sys/buf.h> 90 #include <sys/proc.h> 91 #include <sys/user.h> 92 93 #include <scsi/scsi_all.h> 94 #include <scsi/scsi_debug.h> 95 #include <scsi/scsiconf.h> 96 97 #include <machine/autoconf.h> 98 #include <machine/obio.h> 99 #include <machine/dvma.h> 100 101 #define DEBUG XXX 102 103 #include <dev/ic/ncr5380reg.h> 104 #include <dev/ic/ncr5380var.h> 105 106 #include "sireg.h" 107 #include "sivar.h" 108 #include "am9516.h" 109 110 /* 111 * How many uS. to delay after touching the am9516 UDC. 112 */ 113 #define UDC_WAIT_USEC 5 114 115 void si_obio_dma_setup __P((struct ncr5380_softc *)); 116 void si_obio_dma_start __P((struct ncr5380_softc *)); 117 void si_obio_dma_eop __P((struct ncr5380_softc *)); 118 void si_obio_dma_stop __P((struct ncr5380_softc *)); 119 120 static __inline__ void si_obio_udc_write 121 __P((volatile struct si_regs *si, int regnum, int value)); 122 static __inline__ int si_obio_udc_read 123 __P((volatile struct si_regs *si, int regnum)); 124 125 126 /* 127 * New-style autoconfig attachment 128 */ 129 130 static int si_obio_match __P((struct device *, struct cfdata *, void *)); 131 static void si_obio_attach __P((struct device *, struct device *, void *)); 132 133 struct cfattach si_obio_ca = { 134 sizeof(struct si_softc), si_obio_match, si_obio_attach 135 }; 136 137 /* Options. Interesting values are: 1,3,7 */ 138 /* XXX: Using 1 for now to mask a (pmap?) bug not yet found... */ 139 int si_obio_options = 1; /* XXX */ 140 141 142 static int 143 si_obio_match(parent, cf, args) 144 struct device *parent; 145 struct cfdata *cf; 146 void *args; 147 { 148 struct confargs *ca = args; 149 150 /* Make sure there is something there... */ 151 if (bus_peek(ca->ca_bustype, ca->ca_paddr + 1, 1) == -1) 152 return (0); 153 154 /* Default interrupt priority. */ 155 if (ca->ca_intpri == -1) 156 ca->ca_intpri = 2; 157 158 return (1); 159 } 160 161 static void 162 si_obio_attach(parent, self, args) 163 struct device *parent, *self; 164 void *args; 165 { 166 struct si_softc *sc = (struct si_softc *) self; 167 struct ncr5380_softc *ncr_sc = &sc->ncr_sc; 168 struct cfdata *cf = self->dv_cfdata; 169 struct confargs *ca = args; 170 171 /* Get options from config flags... */ 172 sc->sc_options = cf->cf_flags | si_obio_options; 173 printf(": options=%d\n", sc->sc_options); 174 175 sc->sc_adapter_type = ca->ca_bustype; 176 sc->sc_regs = (struct si_regs *) 177 obio_alloc(ca->ca_paddr, sizeof(struct si_regs)); 178 179 /* 180 * MD function pointers used by the MI code. 181 */ 182 ncr_sc->sc_pio_out = ncr5380_pio_out; 183 ncr_sc->sc_pio_in = ncr5380_pio_in; 184 ncr_sc->sc_dma_alloc = si_dma_alloc; 185 ncr_sc->sc_dma_free = si_dma_free; 186 ncr_sc->sc_dma_setup = si_obio_dma_setup; 187 ncr_sc->sc_dma_start = si_obio_dma_start; 188 ncr_sc->sc_dma_poll = si_dma_poll; 189 ncr_sc->sc_dma_eop = si_obio_dma_eop; 190 ncr_sc->sc_dma_stop = si_obio_dma_stop; 191 ncr_sc->sc_intr_on = NULL; 192 ncr_sc->sc_intr_off = NULL; 193 194 /* Need DVMA-capable memory for the UDC command block. */ 195 sc->sc_dmacmd = dvma_malloc(sizeof (struct udc_table)); 196 197 /* Attach interrupt handler. */ 198 isr_add_autovect(si_intr, (void *)sc, ca->ca_intpri); 199 200 /* Do the common attach stuff. */ 201 si_attach(sc); 202 } 203 204 205 static __inline__ void 206 si_obio_udc_write(si, regnum, value) 207 volatile struct si_regs *si; 208 int regnum, value; 209 { 210 si->udc_addr = regnum; 211 delay(UDC_WAIT_USEC); 212 si->udc_data = value; 213 delay(UDC_WAIT_USEC); 214 } 215 216 static __inline__ int 217 si_obio_udc_read(si, regnum) 218 volatile struct si_regs *si; 219 int regnum; 220 { 221 int value; 222 223 si->udc_addr = regnum; 224 delay(UDC_WAIT_USEC); 225 value = si->udc_data; 226 delay(UDC_WAIT_USEC); 227 228 return (value); 229 } 230 231 232 /* 233 * This function is called during the COMMAND or MSG_IN phase 234 * that preceeds a DATA_IN or DATA_OUT phase, in case we need 235 * to setup the DMA engine before the bus enters a DATA phase. 236 * 237 * The OBIO "si" IGNORES any attempt to set the FIFO count 238 * register after the SCSI bus goes into any DATA phase, so 239 * this function has to setup the evil FIFO logic. 240 */ 241 void 242 si_obio_dma_setup(ncr_sc) 243 struct ncr5380_softc *ncr_sc; 244 { 245 struct si_softc *sc = (struct si_softc *)ncr_sc; 246 struct sci_req *sr = ncr_sc->sc_current; 247 struct si_dma_handle *dh = sr->sr_dma_hand; 248 volatile struct si_regs *si = sc->sc_regs; 249 struct udc_table *cmd; 250 long data_pa, cmd_pa; 251 int xlen; 252 253 /* 254 * Get the DVMA mapping for this segment. 255 * XXX - Should separate allocation and mapin. 256 */ 257 data_pa = dvma_kvtopa(dh->dh_dvma, sc->sc_adapter_type); 258 data_pa += (ncr_sc->sc_dataptr - dh->dh_addr); 259 if (data_pa & 1) 260 panic("si_dma_start: bad pa=0x%x", data_pa); 261 xlen = ncr_sc->sc_datalen; 262 sc->sc_reqlen = xlen; /* XXX: or less? */ 263 264 #ifdef DEBUG 265 if (si_debug & 2) { 266 printf("si_dma_setup: dh=%p, pa=0x%x, xlen=0x%x\n", 267 dh, data_pa, xlen); 268 } 269 #endif 270 271 /* Reset the UDC. (In case not already reset?) */ 272 si_obio_udc_write(si, UDC_ADR_COMMAND, UDC_CMD_RESET); 273 274 /* Reset the FIFO */ 275 si->si_csr &= ~SI_CSR_FIFO_RES; /* active low */ 276 si->si_csr |= SI_CSR_FIFO_RES; 277 278 /* Set direction (send/recv) */ 279 if (dh->dh_flags & SIDH_OUT) { 280 si->si_csr |= SI_CSR_SEND; 281 } else { 282 si->si_csr &= ~SI_CSR_SEND; 283 } 284 285 /* Set the FIFO counter. */ 286 si->fifo_count = xlen; 287 288 /* Reset the UDC. */ 289 si_obio_udc_write(si, UDC_ADR_COMMAND, UDC_CMD_RESET); 290 291 /* 292 * XXX: Reset the FIFO again! Comment from Sprite: 293 * Go through reset again becuase of the bug on the 3/50 294 * where bytes occasionally linger in the DMA fifo. 295 */ 296 si->si_csr &= ~SI_CSR_FIFO_RES; /* active low */ 297 si->si_csr |= SI_CSR_FIFO_RES; 298 299 #ifdef DEBUG 300 /* Make sure the extra FIFO reset did not hit the count. */ 301 if (si->fifo_count != xlen) { 302 printf("si_dma_setup: fifo_count=0x%x, xlen=0x%x\n", 303 si->fifo_count, xlen); 304 Debugger(); 305 } 306 #endif 307 308 /* 309 * Set up the DMA controller. The DMA controller on 310 * OBIO needs a command block in DVMA space. 311 */ 312 cmd = sc->sc_dmacmd; 313 cmd->addrh = ((data_pa & 0xFF0000) >> 8) | UDC_ADDR_INFO; 314 cmd->addrl = data_pa & 0xFFFF; 315 cmd->count = xlen / 2; /* bytes -> words */ 316 cmd->cmrh = UDC_CMR_HIGH; 317 if (dh->dh_flags & SIDH_OUT) { 318 if (xlen & 1) 319 cmd->count++; 320 cmd->cmrl = UDC_CMR_LSEND; 321 cmd->rsel = UDC_RSEL_SEND; 322 } else { 323 cmd->cmrl = UDC_CMR_LRECV; 324 cmd->rsel = UDC_RSEL_RECV; 325 } 326 327 /* Tell the DMA chip where the control block is. */ 328 cmd_pa = dvma_kvtopa((long)cmd, BUS_OBIO); 329 si_obio_udc_write(si, UDC_ADR_CAR_HIGH, 330 (cmd_pa & 0xff0000) >> 8); 331 si_obio_udc_write(si, UDC_ADR_CAR_LOW, 332 (cmd_pa & 0xffff)); 333 334 /* Tell the chip to be a DMA master. */ 335 si_obio_udc_write(si, UDC_ADR_MODE, UDC_MODE); 336 337 /* Tell the chip to interrupt on error. */ 338 si_obio_udc_write(si, UDC_ADR_COMMAND, UDC_CMD_CIE); 339 340 /* Will do "start chain" command in _dma_start. */ 341 } 342 343 344 void 345 si_obio_dma_start(ncr_sc) 346 struct ncr5380_softc *ncr_sc; 347 { 348 struct si_softc *sc = (struct si_softc *)ncr_sc; 349 struct sci_req *sr = ncr_sc->sc_current; 350 struct si_dma_handle *dh = sr->sr_dma_hand; 351 volatile struct si_regs *si = sc->sc_regs; 352 int s; 353 354 #ifdef DEBUG 355 if (si_debug & 2) { 356 printf("si_dma_start: sr=%p\n", sr); 357 } 358 #endif 359 360 /* This MAY be time critical (not sure). */ 361 s = splhigh(); 362 363 /* Finally, give the UDC a "start chain" command. */ 364 si_obio_udc_write(si, UDC_ADR_COMMAND, UDC_CMD_STRT_CHN); 365 366 /* 367 * Acknowledge the phase change. (After DMA setup!) 368 * Put the SBIC into DMA mode, and start the transfer. 369 */ 370 if (dh->dh_flags & SIDH_OUT) { 371 *ncr_sc->sci_tcmd = PHASE_DATA_OUT; 372 SCI_CLR_INTR(ncr_sc); 373 *ncr_sc->sci_icmd = SCI_ICMD_DATA; 374 *ncr_sc->sci_mode |= (SCI_MODE_DMA | SCI_MODE_DMA_IE); 375 *ncr_sc->sci_dma_send = 0; /* start it */ 376 } else { 377 *ncr_sc->sci_tcmd = PHASE_DATA_IN; 378 SCI_CLR_INTR(ncr_sc); 379 *ncr_sc->sci_icmd = 0; 380 *ncr_sc->sci_mode |= (SCI_MODE_DMA | SCI_MODE_DMA_IE); 381 *ncr_sc->sci_irecv = 0; /* start it */ 382 } 383 384 splx(s); 385 ncr_sc->sc_state |= NCR_DOINGDMA; 386 387 #ifdef DEBUG 388 if (si_debug & 2) { 389 printf("si_dma_start: started, flags=0x%x\n", 390 ncr_sc->sc_state); 391 } 392 #endif 393 } 394 395 396 void 397 si_obio_dma_eop(ncr_sc) 398 struct ncr5380_softc *ncr_sc; 399 { 400 401 /* Not needed - DMA was stopped prior to examining sci_csr */ 402 } 403 404 405 void 406 si_obio_dma_stop(ncr_sc) 407 struct ncr5380_softc *ncr_sc; 408 { 409 struct si_softc *sc = (struct si_softc *)ncr_sc; 410 struct sci_req *sr = ncr_sc->sc_current; 411 struct si_dma_handle *dh = sr->sr_dma_hand; 412 volatile struct si_regs *si = sc->sc_regs; 413 int resid, ntrans, tmo, udc_cnt; 414 415 if ((ncr_sc->sc_state & NCR_DOINGDMA) == 0) { 416 #ifdef DEBUG 417 printf("si_dma_stop: dma not running\n"); 418 #endif 419 return; 420 } 421 ncr_sc->sc_state &= ~NCR_DOINGDMA; 422 423 NCR_TRACE("si_dma_stop: top, csr=0x%x\n", si->si_csr); 424 425 /* OK, have either phase mis-match or end of DMA. */ 426 /* Set an impossible phase to prevent data movement? */ 427 *ncr_sc->sci_tcmd = PHASE_INVALID; 428 429 /* Check for DMA errors. */ 430 if (si->si_csr & (SI_CSR_DMA_CONFLICT | SI_CSR_DMA_BUS_ERR)) { 431 printf("si: DMA error, csr=0x%x, reset\n", si->si_csr); 432 sr->sr_xs->error = XS_DRIVER_STUFFUP; 433 ncr_sc->sc_state |= NCR_ABORTING; 434 si_reset_adapter(ncr_sc); 435 goto out; 436 } 437 438 /* Note that timeout may have set the error flag. */ 439 if (ncr_sc->sc_state & NCR_ABORTING) 440 goto out; 441 442 /* 443 * After a read, wait for the FIFO to empty. 444 * Note: this only works on the OBIO version. 445 */ 446 if ((dh->dh_flags & SIDH_OUT) == 0) { 447 tmo = 200000; /* X10 = 2 sec. */ 448 for (;;) { 449 if (si->si_csr & SI_CSR_FIFO_EMPTY) 450 break; 451 if (--tmo <= 0) { 452 printf("si: dma fifo did not empty, reset\n"); 453 ncr_sc->sc_state |= NCR_ABORTING; 454 /* si_reset_adapter(ncr_sc); */ 455 goto out; 456 } 457 delay(10); 458 } 459 } 460 461 /* 462 * Now try to figure out how much actually transferred 463 * The fifo_count might not reflect how many bytes were 464 * actually transferred. 465 */ 466 resid = si->fifo_count & 0xFFFF; 467 ntrans = sc->sc_reqlen - resid; 468 469 #ifdef DEBUG 470 if (si_debug & 2) { 471 printf("si_dma_stop: resid=0x%x ntrans=0x%x\n", 472 resid, ntrans); 473 } 474 #endif 475 476 /* XXX: Treat (ntrans==0) as a special, non-error case? */ 477 if (ntrans < MIN_DMA_LEN) { 478 printf("si: fifo count: 0x%x\n", resid); 479 ncr_sc->sc_state |= NCR_ABORTING; 480 goto out; 481 } 482 if (ntrans > ncr_sc->sc_datalen) 483 panic("si_dma_stop: excess transfer"); 484 485 /* Adjust data pointer */ 486 ncr_sc->sc_dataptr += ntrans; 487 ncr_sc->sc_datalen -= ntrans; 488 489 /* 490 * After a read, we may need to clean-up 491 * "Left-over bytes" (yuck!) 492 */ 493 if ((dh->dh_flags & SIDH_OUT) == 0) { 494 /* If odd transfer count, grab last byte by hand. */ 495 if (ntrans & 1) { 496 NCR_TRACE("si_dma_stop: leftover 1 at 0x%x\n", 497 (int) ncr_sc->sc_dataptr - 1); 498 ncr_sc->sc_dataptr[-1] = 499 (si->fifo_data & 0xff00) >> 8; 500 goto out; 501 } 502 /* UDC might not have transfered the last word. */ 503 udc_cnt = si_obio_udc_read(si, UDC_ADR_COUNT); 504 if (((udc_cnt * 2) - resid) == 2) { 505 NCR_TRACE("si_dma_stop: leftover 2 at 0x%x\n", 506 (int) ncr_sc->sc_dataptr - 2); 507 ncr_sc->sc_dataptr[-2] = 508 (si->fifo_data & 0xff00) >> 8; 509 ncr_sc->sc_dataptr[-1] = 510 (si->fifo_data & 0x00ff); 511 } 512 } 513 514 out: 515 /* Reset the UDC. */ 516 si_obio_udc_write(si, UDC_ADR_COMMAND, UDC_CMD_RESET); 517 si->fifo_count = 0; 518 si->si_csr &= ~SI_CSR_SEND; 519 520 /* Reset the FIFO */ 521 si->si_csr &= ~SI_CSR_FIFO_RES; /* active low */ 522 si->si_csr |= SI_CSR_FIFO_RES; 523 524 /* Put SBIC back in PIO mode. */ 525 /* XXX: set tcmd to PHASE_INVALID? */ 526 *ncr_sc->sci_mode &= ~(SCI_MODE_DMA | SCI_MODE_DMA_IE); 527 *ncr_sc->sci_icmd = 0; 528 } 529 530
Indexes created Tue Sep 30 20:09:53 GMT 2025