si_sebuf.c revision 1.10
1 /* $NetBSD: si_sebuf.c,v 1.10 2000/03/18 16:13:25 mycroft Exp $ */ 2 3 /*- 4 * Copyright (c) 1996 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Gordon W. Ross. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 /* 40 * Sun3/E SCSI driver (machine-dependent portion). 41 * The machine-independent parts are in ncr5380sbc.c 42 * 43 * XXX - Mostly from the si driver. Merge? 44 */ 45 46 #include <sys/param.h> 47 #include <sys/systm.h> 48 #include <sys/errno.h> 49 #include <sys/kernel.h> 50 #include <sys/malloc.h> 51 #include <sys/device.h> 52 #include <sys/buf.h> 53 #include <sys/proc.h> 54 #include <sys/user.h> 55 56 #include <dev/scsipi/scsi_all.h> 57 #include <dev/scsipi/scsipi_all.h> 58 #include <dev/scsipi/scsipi_debug.h> 59 #include <dev/scsipi/scsiconf.h> 60 61 #include <machine/autoconf.h> 62 63 /* #define DEBUG XXX */ 64 65 #include <dev/ic/ncr5380reg.h> 66 #include <dev/ic/ncr5380var.h> 67 68 #include "sereg.h" 69 #include "sevar.h" 70 71 /* 72 * Transfers smaller than this are done using PIO 73 * (on assumption they're not worth DMA overhead) 74 */ 75 #define MIN_DMA_LEN 128 76 77 /* 78 * Transfers lager than 65535 bytes need to be split-up. 79 * (Some of the FIFO logic has only 16 bits counters.) 80 * Make the size an integer multiple of the page size 81 * to avoid buf/cluster remap problems. (paranoid?) 82 */ 83 #define MAX_DMA_LEN 0xE000 84 85 /* 86 * This structure is used to keep track of mapped DMA requests. 87 */ 88 struct se_dma_handle { 89 int dh_flags; 90 #define SIDH_BUSY 1 /* This DH is in use */ 91 #define SIDH_OUT 2 /* DMA does data out (write) */ 92 u_char * dh_addr; /* KVA of start of buffer */ 93 int dh_maplen; /* Length of KVA mapping. */ 94 long dh_dma; /* Offset in DMA buffer. */ 95 }; 96 97 /* 98 * The first structure member has to be the ncr5380_softc 99 * so we can just cast to go back and fourth between them. 100 */ 101 struct se_softc { 102 struct ncr5380_softc ncr_sc; 103 volatile struct se_regs *sc_regs; 104 int sc_adapter_type; 105 int sc_adapter_iv; /* int. vec */ 106 int sc_options; /* options for this instance */ 107 int sc_reqlen; /* requested transfer length */ 108 struct se_dma_handle *sc_dma; 109 /* DMA command block for the OBIO controller. */ 110 void *sc_dmacmd; 111 }; 112 113 /* Options for disconnect/reselect, DMA, and interrupts. */ 114 #define SE_NO_DISCONNECT 0xff 115 #define SE_NO_PARITY_CHK 0xff00 116 #define SE_FORCE_POLLING 0x10000 117 #define SE_DISABLE_DMA 0x20000 118 119 void se_dma_alloc __P((struct ncr5380_softc *)); 120 void se_dma_free __P((struct ncr5380_softc *)); 121 void se_dma_poll __P((struct ncr5380_softc *)); 122 123 void se_dma_setup __P((struct ncr5380_softc *)); 124 void se_dma_start __P((struct ncr5380_softc *)); 125 void se_dma_eop __P((struct ncr5380_softc *)); 126 void se_dma_stop __P((struct ncr5380_softc *)); 127 128 void se_intr_on __P((struct ncr5380_softc *)); 129 void se_intr_off __P((struct ncr5380_softc *)); 130 131 static int se_intr __P((void *)); 132 static void se_reset __P((struct ncr5380_softc *)); 133 134 /* 135 * New-style autoconfig attachment 136 */ 137 138 static int se_match __P((struct device *, struct cfdata *, void *)); 139 static void se_attach __P((struct device *, struct device *, void *)); 140 141 struct cfattach si_sebuf_ca = { 142 sizeof(struct se_softc), se_match, se_attach 143 }; 144 145 static void se_minphys __P((struct buf *)); 146 147 /* Options for disconnect/reselect, DMA, and interrupts. */ 148 int se_options = SE_DISABLE_DMA | SE_FORCE_POLLING | 0xff; 149 150 /* How long to wait for DMA before declaring an error. */ 151 int se_dma_intr_timo = 500; /* ticks (sec. X 100) */ 152 153 int se_debug = 0; 154 #ifdef DEBUG 155 static int se_link_flags = 0 /* | SDEV_DB2 */ ; 156 #endif 157 158 159 static int 160 se_match(parent, cf, args) 161 struct device *parent; 162 struct cfdata *cf; 163 void *args; 164 { 165 struct sebuf_attach_args *aa = args; 166 167 /* Match by name. */ 168 if (strcmp(aa->name, "se")) 169 return (0); 170 171 /* Anyting else to check? */ 172 173 return (1); 174 } 175 176 static void 177 se_attach(parent, self, args) 178 struct device *parent, *self; 179 void *args; 180 { 181 struct se_softc *sc = (struct se_softc *) self; 182 struct ncr5380_softc *ncr_sc = &sc->ncr_sc; 183 struct cfdata *cf = self->dv_cfdata; 184 struct sebuf_attach_args *aa = args; 185 volatile struct se_regs *regs; 186 int i; 187 188 /* Get options from config flags if specified. */ 189 if (cf->cf_flags) 190 sc->sc_options = cf->cf_flags; 191 else 192 sc->sc_options = se_options; 193 194 printf(": options=0x%x\n", sc->sc_options); 195 196 sc->sc_adapter_type = aa->ca.ca_bustype; 197 sc->sc_adapter_iv = aa->ca.ca_intvec; 198 sc->sc_regs = regs = aa->regs; 199 200 /* 201 * MD function pointers used by the MI code. 202 */ 203 ncr_sc->sc_pio_out = ncr5380_pio_out; 204 ncr_sc->sc_pio_in = ncr5380_pio_in; 205 206 #if 0 /* XXX - not yet... */ 207 ncr_sc->sc_dma_alloc = se_dma_alloc; 208 ncr_sc->sc_dma_free = se_dma_free; 209 ncr_sc->sc_dma_setup = se_dma_setup; 210 ncr_sc->sc_dma_start = se_dma_start; 211 ncr_sc->sc_dma_poll = se_dma_poll; 212 ncr_sc->sc_dma_eop = se_dma_eop; 213 ncr_sc->sc_dma_stop = se_dma_stop; 214 ncr_sc->sc_intr_on = se_intr_on; 215 ncr_sc->sc_intr_off = se_intr_off; 216 #endif /* XXX */ 217 218 /* Attach interrupt handler. */ 219 isr_add_vectored(se_intr, (void *)sc, 220 aa->ca.ca_intpri, aa->ca.ca_intvec); 221 222 /* Reset the hardware. */ 223 se_reset(ncr_sc); 224 225 /* Do the common attach stuff. */ 226 227 /* 228 * Support the "options" (config file flags). 229 * Disconnect/reselect is a per-target mask. 230 * Interrupts and DMA are per-controller. 231 */ 232 ncr_sc->sc_no_disconnect = 233 (sc->sc_options & SE_NO_DISCONNECT); 234 ncr_sc->sc_parity_disable = 235 (sc->sc_options & SE_NO_PARITY_CHK) >> 8; 236 if (sc->sc_options & SE_FORCE_POLLING) 237 ncr_sc->sc_flags |= NCR5380_FORCE_POLLING; 238 239 #if 1 /* XXX - Temporary */ 240 /* XXX - In case we think DMA is completely broken... */ 241 if (sc->sc_options & SE_DISABLE_DMA) { 242 /* Override this function pointer. */ 243 ncr_sc->sc_dma_alloc = NULL; 244 } 245 #endif 246 ncr_sc->sc_min_dma_len = MIN_DMA_LEN; 247 248 #ifdef DEBUG 249 if (se_debug) 250 printf("se: Set TheSoftC=%p TheRegs=%p\n", sc, regs); 251 ncr_sc->sc_link.flags |= se_link_flags; 252 #endif 253 254 /* 255 * Initialize fields used by the MI code 256 */ 257 ncr_sc->sci_r0 = ®s->ncrregs[0]; 258 ncr_sc->sci_r1 = ®s->ncrregs[1]; 259 ncr_sc->sci_r2 = ®s->ncrregs[2]; 260 ncr_sc->sci_r3 = ®s->ncrregs[3]; 261 ncr_sc->sci_r4 = ®s->ncrregs[4]; 262 ncr_sc->sci_r5 = ®s->ncrregs[5]; 263 ncr_sc->sci_r6 = ®s->ncrregs[6]; 264 ncr_sc->sci_r7 = ®s->ncrregs[7]; 265 266 /* 267 * Allocate DMA handles. 268 */ 269 i = SCI_OPENINGS * sizeof(struct se_dma_handle); 270 sc->sc_dma = (struct se_dma_handle *) 271 malloc(i, M_DEVBUF, M_WAITOK); 272 if (sc->sc_dma == NULL) 273 panic("se: dma_malloc failed\n"); 274 for (i = 0; i < SCI_OPENINGS; i++) 275 sc->sc_dma[i].dh_flags = 0; 276 277 ncr_sc->sc_adapter.scsipi_scsi.adapter_target = 7; 278 ncr_sc->sc_adapter.scsipi_minphys = se_minphys; 279 280 /* 281 * Initialize se board itself. 282 */ 283 ncr5380_attach(ncr_sc); 284 } 285 286 static void 287 se_reset(struct ncr5380_softc *ncr_sc) 288 { 289 struct se_softc *sc = (struct se_softc *)ncr_sc; 290 volatile struct se_regs *se = sc->sc_regs; 291 292 #ifdef DEBUG 293 if (se_debug) { 294 printf("se_reset\n"); 295 } 296 #endif 297 298 /* The reset bits in the CSR are active low. */ 299 se->se_csr = 0; 300 delay(10); 301 se->se_csr = SE_CSR_SCSI_RES /* | SE_CSR_INTR_EN */ ; 302 delay(10); 303 304 /* Make sure the DMA engine is stopped. */ 305 se->dma_addr = 0; 306 se->dma_cntr = 0; 307 se->se_ivec = sc->sc_adapter_iv; 308 } 309 310 /* 311 * This is called when the bus is going idle, 312 * so we want to enable the SBC interrupts. 313 * That is controlled by the DMA enable! 314 * Who would have guessed! 315 * What a NASTY trick! 316 */ 317 void 318 se_intr_on(ncr_sc) 319 struct ncr5380_softc *ncr_sc; 320 { 321 struct se_softc *sc = (struct se_softc *)ncr_sc; 322 volatile struct se_regs *se = sc->sc_regs; 323 324 /* receive mode should be safer */ 325 se->se_csr &= ~SE_CSR_SEND; 326 327 /* Clear the count so nothing happens. */ 328 se->dma_cntr = 0; 329 330 /* Clear the start address too. (paranoid?) */ 331 se->dma_addr = 0; 332 333 /* Finally, enable the DMA engine. */ 334 se->se_csr |= SE_CSR_INTR_EN; 335 } 336 337 /* 338 * This is called when the bus is idle and we are 339 * about to start playing with the SBC chip. 340 */ 341 void 342 se_intr_off(ncr_sc) 343 struct ncr5380_softc *ncr_sc; 344 { 345 struct se_softc *sc = (struct se_softc *)ncr_sc; 346 volatile struct se_regs *se = sc->sc_regs; 347 348 se->se_csr &= ~SE_CSR_INTR_EN; 349 } 350 351 /* 352 * This function is called during the COMMAND or MSG_IN phase 353 * that preceeds a DATA_IN or DATA_OUT phase, in case we need 354 * to setup the DMA engine before the bus enters a DATA phase. 355 * 356 * On the VME version, setup the start addres, but clear the 357 * count (to make sure it stays idle) and set that later. 358 * XXX: The VME adapter appears to suppress SBC interrupts 359 * when the FIFO is not empty or the FIFO count is non-zero! 360 * XXX: Need to copy data into the DMA buffer... 361 */ 362 void 363 se_dma_setup(ncr_sc) 364 struct ncr5380_softc *ncr_sc; 365 { 366 struct se_softc *sc = (struct se_softc *)ncr_sc; 367 struct sci_req *sr = ncr_sc->sc_current; 368 struct se_dma_handle *dh = sr->sr_dma_hand; 369 volatile struct se_regs *se = sc->sc_regs; 370 long data_pa; 371 int xlen; 372 373 /* 374 * Get the DMA mapping for this segment. 375 * XXX - Should separate allocation and mapin. 376 */ 377 data_pa = 0; /* XXX se_dma_kvtopa(dh->dh_dma); */ 378 data_pa += (ncr_sc->sc_dataptr - dh->dh_addr); 379 if (data_pa & 1) 380 panic("se_dma_start: bad pa=0x%lx", data_pa); 381 xlen = ncr_sc->sc_datalen; 382 xlen &= ~1; /* XXX: necessary? */ 383 sc->sc_reqlen = xlen; /* XXX: or less? */ 384 385 #ifdef DEBUG 386 if (se_debug & 2) { 387 printf("se_dma_setup: dh=%p, pa=0x%lx, xlen=0x%x\n", 388 dh, data_pa, xlen); 389 } 390 #endif 391 392 /* Set direction (send/recv) */ 393 if (dh->dh_flags & SIDH_OUT) { 394 se->se_csr |= SE_CSR_SEND; 395 } else { 396 se->se_csr &= ~SE_CSR_SEND; 397 } 398 399 /* Load the start address. */ 400 se->dma_addr = (ushort)(data_pa & 0xFFFF); 401 402 /* 403 * Keep the count zero or it may start early! 404 */ 405 se->dma_cntr = 0; 406 } 407 408 409 void 410 se_dma_start(ncr_sc) 411 struct ncr5380_softc *ncr_sc; 412 { 413 struct se_softc *sc = (struct se_softc *)ncr_sc; 414 struct sci_req *sr = ncr_sc->sc_current; 415 struct se_dma_handle *dh = sr->sr_dma_hand; 416 volatile struct se_regs *se = sc->sc_regs; 417 int s, xlen; 418 419 xlen = sc->sc_reqlen; 420 421 /* This MAY be time critical (not sure). */ 422 s = splhigh(); 423 424 se->dma_cntr = (ushort)(xlen & 0xFFFF); 425 426 /* 427 * Acknowledge the phase change. (After DMA setup!) 428 * Put the SBIC into DMA mode, and start the transfer. 429 */ 430 if (dh->dh_flags & SIDH_OUT) { 431 *ncr_sc->sci_tcmd = PHASE_DATA_OUT; 432 SCI_CLR_INTR(ncr_sc); 433 *ncr_sc->sci_icmd = SCI_ICMD_DATA; 434 *ncr_sc->sci_mode |= (SCI_MODE_DMA | SCI_MODE_DMA_IE); 435 *ncr_sc->sci_dma_send = 0; /* start it */ 436 } else { 437 *ncr_sc->sci_tcmd = PHASE_DATA_IN; 438 SCI_CLR_INTR(ncr_sc); 439 *ncr_sc->sci_icmd = 0; 440 *ncr_sc->sci_mode |= (SCI_MODE_DMA | SCI_MODE_DMA_IE); 441 *ncr_sc->sci_irecv = 0; /* start it */ 442 } 443 444 /* Let'er rip! */ 445 se->se_csr |= SE_CSR_INTR_EN; 446 447 splx(s); 448 ncr_sc->sc_state |= NCR_DOINGDMA; 449 450 #ifdef DEBUG 451 if (se_debug & 2) { 452 printf("se_dma_start: started, flags=0x%x\n", 453 ncr_sc->sc_state); 454 } 455 #endif 456 } 457 458 459 void 460 se_dma_eop(ncr_sc) 461 struct ncr5380_softc *ncr_sc; 462 { 463 464 /* Not needed - DMA was stopped prior to examining sci_csr */ 465 } 466 467 468 void 469 se_dma_stop(ncr_sc) 470 struct ncr5380_softc *ncr_sc; 471 { 472 struct se_softc *sc = (struct se_softc *)ncr_sc; 473 struct sci_req *sr = ncr_sc->sc_current; 474 struct se_dma_handle *dh = sr->sr_dma_hand; 475 volatile struct se_regs *se = sc->sc_regs; 476 int resid, ntrans; 477 478 if ((ncr_sc->sc_state & NCR_DOINGDMA) == 0) { 479 #ifdef DEBUG 480 printf("se_dma_stop: dma not running\n"); 481 #endif 482 return; 483 } 484 ncr_sc->sc_state &= ~NCR_DOINGDMA; 485 486 /* First, halt the DMA engine. */ 487 se->se_csr &= ~SE_CSR_INTR_EN; /* VME only */ 488 489 /* Set an impossible phase to prevent data movement? */ 490 *ncr_sc->sci_tcmd = PHASE_INVALID; 491 492 /* Note that timeout may have set the error flag. */ 493 if (ncr_sc->sc_state & NCR_ABORTING) 494 goto out; 495 496 /* XXX: Wait for DMA to actually finish? */ 497 498 /* 499 * Now try to figure out how much actually transferred 500 */ 501 resid = se->dma_cntr & 0xFFFF; 502 if (dh->dh_flags & SIDH_OUT) 503 if ((resid > 0) && (resid < sc->sc_reqlen)) 504 resid++; 505 ntrans = sc->sc_reqlen - resid; 506 507 #ifdef DEBUG 508 if (se_debug & 2) { 509 printf("se_dma_stop: resid=0x%x ntrans=0x%x\n", 510 resid, ntrans); 511 } 512 #endif 513 514 if (ntrans < MIN_DMA_LEN) { 515 printf("se: fifo count: 0x%x\n", resid); 516 ncr_sc->sc_state |= NCR_ABORTING; 517 goto out; 518 } 519 if (ntrans > ncr_sc->sc_datalen) 520 panic("se_dma_stop: excess transfer"); 521 522 /* Adjust data pointer */ 523 ncr_sc->sc_dataptr += ntrans; 524 ncr_sc->sc_datalen -= ntrans; 525 526 out: 527 se->dma_addr = 0; 528 se->dma_cntr = 0; 529 530 /* Put SBIC back in PIO mode. */ 531 *ncr_sc->sci_mode &= ~(SCI_MODE_DMA | SCI_MODE_DMA_IE); 532 *ncr_sc->sci_icmd = 0; 533 } 534 535 /*****************************************************************/ 536 537 static void 538 se_minphys(struct buf *bp) 539 { 540 541 if (bp->b_bcount > MAX_DMA_LEN) 542 bp->b_bcount = MAX_DMA_LEN; 543 544 return (minphys(bp)); 545 } 546 547 548 int 549 se_intr(void *arg) 550 { 551 struct se_softc *sc = arg; 552 volatile struct se_regs *se = sc->sc_regs; 553 int dma_error, claimed; 554 u_short csr; 555 556 claimed = 0; 557 dma_error = 0; 558 559 /* SBC interrupt? DMA interrupt? */ 560 csr = se->se_csr; 561 NCR_TRACE("se_intr: csr=0x%x\n", csr); 562 563 if (csr & SE_CSR_SBC_IP) { 564 claimed = ncr5380_intr(&sc->ncr_sc); 565 #ifdef DEBUG 566 if (!claimed) { 567 printf("se_intr: spurious from SBC\n"); 568 } 569 #endif 570 /* Yes, we DID cause this interrupt. */ 571 claimed = 1; 572 } 573 574 return (claimed); 575 } 576 577 578 /***************************************************************** 579 * Common functions for DMA 580 ****************************************************************/ 581 582 /* 583 * Allocate a DMA handle and put it in sc->sc_dma. Prepare 584 * for DMA transfer. On the Sun3/E, this means we have to 585 * allocate space in the DMA buffer for this transfer. 586 */ 587 void 588 se_dma_alloc(ncr_sc) 589 struct ncr5380_softc *ncr_sc; 590 { 591 struct se_softc *sc = (struct se_softc *)ncr_sc; 592 struct sci_req *sr = ncr_sc->sc_current; 593 struct scsipi_xfer *xs = sr->sr_xs; 594 struct se_dma_handle *dh; 595 int i, xlen; 596 u_long addr; 597 598 #ifdef DIAGNOSTIC 599 if (sr->sr_dma_hand != NULL) 600 panic("se_dma_alloc: already have DMA handle"); 601 #endif 602 603 addr = (u_long) ncr_sc->sc_dataptr; 604 xlen = ncr_sc->sc_datalen; 605 606 /* If the DMA start addr is misaligned then do PIO */ 607 if ((addr & 1) || (xlen & 1)) { 608 printf("se_dma_alloc: misaligned.\n"); 609 return; 610 } 611 612 /* Make sure our caller checked sc_min_dma_len. */ 613 if (xlen < MIN_DMA_LEN) 614 panic("se_dma_alloc: xlen=0x%x\n", xlen); 615 616 /* 617 * Never attempt single transfers of more than 63k, because 618 * our count register may be only 16 bits (an OBIO adapter). 619 * This should never happen since already bounded by minphys(). 620 * XXX - Should just segment these... 621 */ 622 if (xlen > MAX_DMA_LEN) { 623 printf("se_dma_alloc: excessive xlen=0x%x\n", xlen); 624 ncr_sc->sc_datalen = xlen = MAX_DMA_LEN; 625 } 626 627 /* Find free DMA handle. Guaranteed to find one since we have 628 as many DMA handles as the driver has processes. */ 629 for (i = 0; i < SCI_OPENINGS; i++) { 630 if ((sc->sc_dma[i].dh_flags & SIDH_BUSY) == 0) 631 goto found; 632 } 633 panic("se: no free DMA handles."); 634 found: 635 636 dh = &sc->sc_dma[i]; 637 dh->dh_flags = SIDH_BUSY; 638 639 /* Copy the "write" flag for convenience. */ 640 if (xs->xs_control & XS_CTL_DATA_OUT) 641 dh->dh_flags |= SIDH_OUT; 642 643 dh->dh_addr = (u_char*) addr; 644 dh->dh_maplen = xlen; 645 dh->dh_dma = 0; /* XXX - Allocate space in DMA buffer. */ 646 /* XXX: dh->dh_dma = alloc(xlen) */ 647 if (!dh->dh_dma) { 648 /* Can't remap segment */ 649 printf("se_dma_alloc: can't remap %p/0x%x\n", 650 dh->dh_addr, dh->dh_maplen); 651 dh->dh_flags = 0; 652 return; 653 } 654 655 /* success */ 656 sr->sr_dma_hand = dh; 657 658 return; 659 } 660 661 662 void 663 se_dma_free(ncr_sc) 664 struct ncr5380_softc *ncr_sc; 665 { 666 struct sci_req *sr = ncr_sc->sc_current; 667 struct se_dma_handle *dh = sr->sr_dma_hand; 668 669 #ifdef DIAGNOSTIC 670 if (dh == NULL) 671 panic("se_dma_free: no DMA handle"); 672 #endif 673 674 if (ncr_sc->sc_state & NCR_DOINGDMA) 675 panic("se_dma_free: free while in progress"); 676 677 if (dh->dh_flags & SIDH_BUSY) { 678 /* XXX: Should separate allocation and mapping. */ 679 /* XXX: Give back the DMA space. */ 680 /* XXX: free((caddr_t)dh->dh_dma, dh->dh_maplen); */ 681 dh->dh_dma = 0; 682 dh->dh_flags = 0; 683 } 684 sr->sr_dma_hand = NULL; 685 } 686 687 688 #define CSR_MASK SE_CSR_SBC_IP 689 #define POLL_TIMO 50000 /* X100 = 5 sec. */ 690 691 /* 692 * Poll (spin-wait) for DMA completion. 693 * Called right after xx_dma_start(), and 694 * xx_dma_stop() will be called next. 695 * Same for either VME or OBIO. 696 */ 697 void 698 se_dma_poll(ncr_sc) 699 struct ncr5380_softc *ncr_sc; 700 { 701 struct se_softc *sc = (struct se_softc *)ncr_sc; 702 struct sci_req *sr = ncr_sc->sc_current; 703 volatile struct se_regs *se = sc->sc_regs; 704 int tmo; 705 706 /* Make sure DMA started successfully. */ 707 if (ncr_sc->sc_state & NCR_ABORTING) 708 return; 709 710 /* 711 * XXX: The Sun driver waits for ~SE_CSR_DMA_ACTIVE here 712 * XXX: (on obio) or even worse (on vme) a 10mS. delay! 713 * XXX: I really doubt that is necessary... 714 */ 715 716 /* Wait for any "dma complete" or error bits. */ 717 tmo = POLL_TIMO; 718 for (;;) { 719 if (se->se_csr & CSR_MASK) 720 break; 721 if (--tmo <= 0) { 722 printf("se: DMA timeout (while polling)\n"); 723 /* Indicate timeout as MI code would. */ 724 sr->sr_flags |= SR_OVERDUE; 725 break; 726 } 727 delay(100); 728 } 729 NCR_TRACE("se_dma_poll: waited %d\n", 730 POLL_TIMO - tmo); 731 732 #ifdef DEBUG 733 if (se_debug & 2) { 734 printf("se_dma_poll: done, csr=0x%x\n", se->se_csr); 735 } 736 #endif 737 } 738 739
Indexes created Thu Oct 02 14:10:14 GMT 2025