si_sebuf.c revision 1.20.2.2
1 /* $NetBSD: si_sebuf.c,v 1.20.2.2 2004/09/18 14:41:39 skrll Exp $ */ 2 3 /*- 4 * Copyright (c) 1996 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Gordon W. Ross. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 /* 40 * Sun3/E SCSI driver (machine-dependent portion). 41 * The machine-independent parts are in ncr5380sbc.c 42 * 43 * XXX - Mostly from the si driver. Merge? 44 */ 45 46 #include <sys/cdefs.h> 47 __KERNEL_RCSID(0, "$NetBSD: si_sebuf.c,v 1.20.2.2 2004/09/18 14:41:39 skrll Exp $"); 48 49 #include <sys/param.h> 50 #include <sys/systm.h> 51 #include <sys/errno.h> 52 #include <sys/kernel.h> 53 #include <sys/malloc.h> 54 #include <sys/device.h> 55 #include <sys/buf.h> 56 #include <sys/proc.h> 57 #include <sys/user.h> 58 59 #include <dev/scsipi/scsi_all.h> 60 #include <dev/scsipi/scsipi_all.h> 61 #include <dev/scsipi/scsipi_debug.h> 62 #include <dev/scsipi/scsiconf.h> 63 64 #include <machine/autoconf.h> 65 66 /* #define DEBUG XXX */ 67 68 #include <dev/ic/ncr5380reg.h> 69 #include <dev/ic/ncr5380var.h> 70 71 #include "sereg.h" 72 #include "sevar.h" 73 74 /* 75 * Transfers smaller than this are done using PIO 76 * (on assumption they're not worth DMA overhead) 77 */ 78 #define MIN_DMA_LEN 128 79 80 /* 81 * Transfers lager than 65535 bytes need to be split-up. 82 * (Some of the FIFO logic has only 16 bits counters.) 83 * Make the size an integer multiple of the page size 84 * to avoid buf/cluster remap problems. (paranoid?) 85 */ 86 #define MAX_DMA_LEN 0xE000 87 88 /* 89 * This structure is used to keep track of mapped DMA requests. 90 */ 91 struct se_dma_handle { 92 int dh_flags; 93 #define SIDH_BUSY 1 /* This DH is in use */ 94 #define SIDH_OUT 2 /* DMA does data out (write) */ 95 u_char * dh_addr; /* KVA of start of buffer */ 96 int dh_maplen; /* Length of KVA mapping. */ 97 long dh_dma; /* Offset in DMA buffer. */ 98 }; 99 100 /* 101 * The first structure member has to be the ncr5380_softc 102 * so we can just cast to go back and fourth between them. 103 */ 104 struct se_softc { 105 struct ncr5380_softc ncr_sc; 106 volatile struct se_regs *sc_regs; 107 int sc_adapter_type; 108 int sc_adapter_iv; /* int. vec */ 109 int sc_options; /* options for this instance */ 110 int sc_reqlen; /* requested transfer length */ 111 struct se_dma_handle *sc_dma; 112 /* DMA command block for the OBIO controller. */ 113 void *sc_dmacmd; 114 }; 115 116 /* Options for disconnect/reselect, DMA, and interrupts. */ 117 #define SE_NO_DISCONNECT 0xff 118 #define SE_NO_PARITY_CHK 0xff00 119 #define SE_FORCE_POLLING 0x10000 120 #define SE_DISABLE_DMA 0x20000 121 122 void se_dma_alloc __P((struct ncr5380_softc *)); 123 void se_dma_free __P((struct ncr5380_softc *)); 124 void se_dma_poll __P((struct ncr5380_softc *)); 125 126 void se_dma_setup __P((struct ncr5380_softc *)); 127 void se_dma_start __P((struct ncr5380_softc *)); 128 void se_dma_eop __P((struct ncr5380_softc *)); 129 void se_dma_stop __P((struct ncr5380_softc *)); 130 131 void se_intr_on __P((struct ncr5380_softc *)); 132 void se_intr_off __P((struct ncr5380_softc *)); 133 134 static int se_intr __P((void *)); 135 static void se_reset __P((struct ncr5380_softc *)); 136 137 /* 138 * New-style autoconfig attachment 139 */ 140 141 static int se_match __P((struct device *, struct cfdata *, void *)); 142 static void se_attach __P((struct device *, struct device *, void *)); 143 144 CFATTACH_DECL(si_sebuf, sizeof(struct se_softc), 145 se_match, se_attach, NULL, NULL); 146 147 static void se_minphys __P((struct buf *)); 148 149 /* Options for disconnect/reselect, DMA, and interrupts. */ 150 int se_options = SE_DISABLE_DMA | SE_FORCE_POLLING | 0xff; 151 152 /* How long to wait for DMA before declaring an error. */ 153 int se_dma_intr_timo = 500; /* ticks (sec. X 100) */ 154 155 int se_debug = 0; 156 157 static int 158 se_match(parent, cf, args) 159 struct device *parent; 160 struct cfdata *cf; 161 void *args; 162 { 163 struct sebuf_attach_args *aa = args; 164 165 /* Match by name. */ 166 if (strcmp(aa->name, "se")) 167 return (0); 168 169 /* Anyting else to check? */ 170 171 return (1); 172 } 173 174 static void 175 se_attach(parent, self, args) 176 struct device *parent, *self; 177 void *args; 178 { 179 struct se_softc *sc = (struct se_softc *) self; 180 struct ncr5380_softc *ncr_sc = &sc->ncr_sc; 181 struct cfdata *cf = self->dv_cfdata; 182 struct sebuf_attach_args *aa = args; 183 volatile struct se_regs *regs; 184 int i; 185 186 /* Get options from config flags if specified. */ 187 if (cf->cf_flags) 188 sc->sc_options = cf->cf_flags; 189 else 190 sc->sc_options = se_options; 191 192 printf(": options=0x%x\n", sc->sc_options); 193 194 sc->sc_adapter_type = aa->ca.ca_bustype; 195 sc->sc_adapter_iv = aa->ca.ca_intvec; 196 sc->sc_regs = regs = aa->regs; 197 198 /* 199 * MD function pointers used by the MI code. 200 */ 201 ncr_sc->sc_pio_out = ncr5380_pio_out; 202 ncr_sc->sc_pio_in = ncr5380_pio_in; 203 204 #if 0 /* XXX - not yet... */ 205 ncr_sc->sc_dma_alloc = se_dma_alloc; 206 ncr_sc->sc_dma_free = se_dma_free; 207 ncr_sc->sc_dma_setup = se_dma_setup; 208 ncr_sc->sc_dma_start = se_dma_start; 209 ncr_sc->sc_dma_poll = se_dma_poll; 210 ncr_sc->sc_dma_eop = se_dma_eop; 211 ncr_sc->sc_dma_stop = se_dma_stop; 212 ncr_sc->sc_intr_on = se_intr_on; 213 ncr_sc->sc_intr_off = se_intr_off; 214 #endif /* XXX */ 215 216 /* Attach interrupt handler. */ 217 isr_add_vectored(se_intr, (void *)sc, 218 aa->ca.ca_intpri, aa->ca.ca_intvec); 219 220 /* Reset the hardware. */ 221 se_reset(ncr_sc); 222 223 /* Do the common attach stuff. */ 224 225 /* 226 * Support the "options" (config file flags). 227 * Disconnect/reselect is a per-target mask. 228 * Interrupts and DMA are per-controller. 229 */ 230 ncr_sc->sc_no_disconnect = 231 (sc->sc_options & SE_NO_DISCONNECT); 232 ncr_sc->sc_parity_disable = 233 (sc->sc_options & SE_NO_PARITY_CHK) >> 8; 234 if (sc->sc_options & SE_FORCE_POLLING) 235 ncr_sc->sc_flags |= NCR5380_FORCE_POLLING; 236 237 #if 1 /* XXX - Temporary */ 238 /* XXX - In case we think DMA is completely broken... */ 239 if (sc->sc_options & SE_DISABLE_DMA) { 240 /* Override this function pointer. */ 241 ncr_sc->sc_dma_alloc = NULL; 242 } 243 #endif 244 ncr_sc->sc_min_dma_len = MIN_DMA_LEN; 245 246 /* 247 * Initialize fields used by the MI code 248 */ 249 ncr_sc->sci_r0 = ®s->ncrregs[0]; 250 ncr_sc->sci_r1 = ®s->ncrregs[1]; 251 ncr_sc->sci_r2 = ®s->ncrregs[2]; 252 ncr_sc->sci_r3 = ®s->ncrregs[3]; 253 ncr_sc->sci_r4 = ®s->ncrregs[4]; 254 ncr_sc->sci_r5 = ®s->ncrregs[5]; 255 ncr_sc->sci_r6 = ®s->ncrregs[6]; 256 ncr_sc->sci_r7 = ®s->ncrregs[7]; 257 258 ncr_sc->sc_rev = NCR_VARIANT_NCR5380; 259 260 /* 261 * Allocate DMA handles. 262 */ 263 i = SCI_OPENINGS * sizeof(struct se_dma_handle); 264 sc->sc_dma = (struct se_dma_handle *) 265 malloc(i, M_DEVBUF, M_WAITOK); 266 if (sc->sc_dma == NULL) 267 panic("se: dma_malloc failed"); 268 for (i = 0; i < SCI_OPENINGS; i++) 269 sc->sc_dma[i].dh_flags = 0; 270 271 ncr_sc->sc_channel.chan_id = 7; 272 ncr_sc->sc_adapter.adapt_minphys = se_minphys; 273 274 /* 275 * Initialize se board itself. 276 */ 277 ncr5380_attach(ncr_sc); 278 } 279 280 static void 281 se_reset(struct ncr5380_softc *ncr_sc) 282 { 283 struct se_softc *sc = (struct se_softc *)ncr_sc; 284 volatile struct se_regs *se = sc->sc_regs; 285 286 #ifdef DEBUG 287 if (se_debug) { 288 printf("se_reset\n"); 289 } 290 #endif 291 292 /* The reset bits in the CSR are active low. */ 293 se->se_csr = 0; 294 delay(10); 295 se->se_csr = SE_CSR_SCSI_RES /* | SE_CSR_INTR_EN */ ; 296 delay(10); 297 298 /* Make sure the DMA engine is stopped. */ 299 se->dma_addr = 0; 300 se->dma_cntr = 0; 301 se->se_ivec = sc->sc_adapter_iv; 302 } 303 304 /* 305 * This is called when the bus is going idle, 306 * so we want to enable the SBC interrupts. 307 * That is controlled by the DMA enable! 308 * Who would have guessed! 309 * What a NASTY trick! 310 */ 311 void 312 se_intr_on(ncr_sc) 313 struct ncr5380_softc *ncr_sc; 314 { 315 struct se_softc *sc = (struct se_softc *)ncr_sc; 316 volatile struct se_regs *se = sc->sc_regs; 317 318 /* receive mode should be safer */ 319 se->se_csr &= ~SE_CSR_SEND; 320 321 /* Clear the count so nothing happens. */ 322 se->dma_cntr = 0; 323 324 /* Clear the start address too. (paranoid?) */ 325 se->dma_addr = 0; 326 327 /* Finally, enable the DMA engine. */ 328 se->se_csr |= SE_CSR_INTR_EN; 329 } 330 331 /* 332 * This is called when the bus is idle and we are 333 * about to start playing with the SBC chip. 334 */ 335 void 336 se_intr_off(ncr_sc) 337 struct ncr5380_softc *ncr_sc; 338 { 339 struct se_softc *sc = (struct se_softc *)ncr_sc; 340 volatile struct se_regs *se = sc->sc_regs; 341 342 se->se_csr &= ~SE_CSR_INTR_EN; 343 } 344 345 /* 346 * This function is called during the COMMAND or MSG_IN phase 347 * that precedes a DATA_IN or DATA_OUT phase, in case we need 348 * to setup the DMA engine before the bus enters a DATA phase. 349 * 350 * On the VME version, setup the start addres, but clear the 351 * count (to make sure it stays idle) and set that later. 352 * XXX: The VME adapter appears to suppress SBC interrupts 353 * when the FIFO is not empty or the FIFO count is non-zero! 354 * XXX: Need to copy data into the DMA buffer... 355 */ 356 void 357 se_dma_setup(ncr_sc) 358 struct ncr5380_softc *ncr_sc; 359 { 360 struct se_softc *sc = (struct se_softc *)ncr_sc; 361 struct sci_req *sr = ncr_sc->sc_current; 362 struct se_dma_handle *dh = sr->sr_dma_hand; 363 volatile struct se_regs *se = sc->sc_regs; 364 long data_pa; 365 int xlen; 366 367 /* 368 * Get the DMA mapping for this segment. 369 * XXX - Should separate allocation and mapin. 370 */ 371 data_pa = 0; /* XXX se_dma_kvtopa(dh->dh_dma); */ 372 data_pa += (ncr_sc->sc_dataptr - dh->dh_addr); 373 if (data_pa & 1) 374 panic("se_dma_start: bad pa=0x%lx", data_pa); 375 xlen = ncr_sc->sc_datalen; 376 xlen &= ~1; /* XXX: necessary? */ 377 sc->sc_reqlen = xlen; /* XXX: or less? */ 378 379 #ifdef DEBUG 380 if (se_debug & 2) { 381 printf("se_dma_setup: dh=%p, pa=0x%lx, xlen=0x%x\n", 382 dh, data_pa, xlen); 383 } 384 #endif 385 386 /* Set direction (send/recv) */ 387 if (dh->dh_flags & SIDH_OUT) { 388 se->se_csr |= SE_CSR_SEND; 389 } else { 390 se->se_csr &= ~SE_CSR_SEND; 391 } 392 393 /* Load the start address. */ 394 se->dma_addr = (ushort)(data_pa & 0xFFFF); 395 396 /* 397 * Keep the count zero or it may start early! 398 */ 399 se->dma_cntr = 0; 400 } 401 402 403 void 404 se_dma_start(ncr_sc) 405 struct ncr5380_softc *ncr_sc; 406 { 407 struct se_softc *sc = (struct se_softc *)ncr_sc; 408 struct sci_req *sr = ncr_sc->sc_current; 409 struct se_dma_handle *dh = sr->sr_dma_hand; 410 volatile struct se_regs *se = sc->sc_regs; 411 int s, xlen; 412 413 xlen = sc->sc_reqlen; 414 415 /* This MAY be time critical (not sure). */ 416 s = splhigh(); 417 418 se->dma_cntr = (ushort)(xlen & 0xFFFF); 419 420 /* 421 * Acknowledge the phase change. (After DMA setup!) 422 * Put the SBIC into DMA mode, and start the transfer. 423 */ 424 if (dh->dh_flags & SIDH_OUT) { 425 *ncr_sc->sci_tcmd = PHASE_DATA_OUT; 426 SCI_CLR_INTR(ncr_sc); 427 *ncr_sc->sci_icmd = SCI_ICMD_DATA; 428 *ncr_sc->sci_mode |= (SCI_MODE_DMA | SCI_MODE_DMA_IE); 429 *ncr_sc->sci_dma_send = 0; /* start it */ 430 } else { 431 *ncr_sc->sci_tcmd = PHASE_DATA_IN; 432 SCI_CLR_INTR(ncr_sc); 433 *ncr_sc->sci_icmd = 0; 434 *ncr_sc->sci_mode |= (SCI_MODE_DMA | SCI_MODE_DMA_IE); 435 *ncr_sc->sci_irecv = 0; /* start it */ 436 } 437 438 /* Let'er rip! */ 439 se->se_csr |= SE_CSR_INTR_EN; 440 441 splx(s); 442 ncr_sc->sc_state |= NCR_DOINGDMA; 443 444 #ifdef DEBUG 445 if (se_debug & 2) { 446 printf("se_dma_start: started, flags=0x%x\n", 447 ncr_sc->sc_state); 448 } 449 #endif 450 } 451 452 453 void 454 se_dma_eop(ncr_sc) 455 struct ncr5380_softc *ncr_sc; 456 { 457 458 /* Not needed - DMA was stopped prior to examining sci_csr */ 459 } 460 461 462 void 463 se_dma_stop(ncr_sc) 464 struct ncr5380_softc *ncr_sc; 465 { 466 struct se_softc *sc = (struct se_softc *)ncr_sc; 467 struct sci_req *sr = ncr_sc->sc_current; 468 struct se_dma_handle *dh = sr->sr_dma_hand; 469 volatile struct se_regs *se = sc->sc_regs; 470 int resid, ntrans; 471 472 if ((ncr_sc->sc_state & NCR_DOINGDMA) == 0) { 473 #ifdef DEBUG 474 printf("se_dma_stop: DMA not running\n"); 475 #endif 476 return; 477 } 478 ncr_sc->sc_state &= ~NCR_DOINGDMA; 479 480 /* First, halt the DMA engine. */ 481 se->se_csr &= ~SE_CSR_INTR_EN; /* VME only */ 482 483 /* Set an impossible phase to prevent data movement? */ 484 *ncr_sc->sci_tcmd = PHASE_INVALID; 485 486 /* Note that timeout may have set the error flag. */ 487 if (ncr_sc->sc_state & NCR_ABORTING) 488 goto out; 489 490 /* XXX: Wait for DMA to actually finish? */ 491 492 /* 493 * Now try to figure out how much actually transferred 494 */ 495 resid = se->dma_cntr & 0xFFFF; 496 if (dh->dh_flags & SIDH_OUT) 497 if ((resid > 0) && (resid < sc->sc_reqlen)) 498 resid++; 499 ntrans = sc->sc_reqlen - resid; 500 501 #ifdef DEBUG 502 if (se_debug & 2) { 503 printf("se_dma_stop: resid=0x%x ntrans=0x%x\n", 504 resid, ntrans); 505 } 506 #endif 507 508 if (ntrans < MIN_DMA_LEN) { 509 printf("se: fifo count: 0x%x\n", resid); 510 ncr_sc->sc_state |= NCR_ABORTING; 511 goto out; 512 } 513 if (ntrans > ncr_sc->sc_datalen) 514 panic("se_dma_stop: excess transfer"); 515 516 /* Adjust data pointer */ 517 ncr_sc->sc_dataptr += ntrans; 518 ncr_sc->sc_datalen -= ntrans; 519 520 out: 521 se->dma_addr = 0; 522 se->dma_cntr = 0; 523 524 /* Put SBIC back in PIO mode. */ 525 *ncr_sc->sci_mode &= ~(SCI_MODE_DMA | SCI_MODE_DMA_IE); 526 *ncr_sc->sci_icmd = 0; 527 } 528 529 /*****************************************************************/ 530 531 static void 532 se_minphys(struct buf *bp) 533 { 534 535 if (bp->b_bcount > MAX_DMA_LEN) 536 bp->b_bcount = MAX_DMA_LEN; 537 538 minphys(bp); 539 } 540 541 542 int 543 se_intr(void *arg) 544 { 545 struct se_softc *sc = arg; 546 volatile struct se_regs *se = sc->sc_regs; 547 int dma_error, claimed; 548 u_short csr; 549 550 claimed = 0; 551 dma_error = 0; 552 553 /* SBC interrupt? DMA interrupt? */ 554 csr = se->se_csr; 555 NCR_TRACE("se_intr: csr=0x%x\n", csr); 556 557 if (csr & SE_CSR_SBC_IP) { 558 claimed = ncr5380_intr(&sc->ncr_sc); 559 #ifdef DEBUG 560 if (!claimed) { 561 printf("se_intr: spurious from SBC\n"); 562 } 563 #endif 564 /* Yes, we DID cause this interrupt. */ 565 claimed = 1; 566 } 567 568 return (claimed); 569 } 570 571 572 /***************************************************************** 573 * Common functions for DMA 574 ****************************************************************/ 575 576 /* 577 * Allocate a DMA handle and put it in sc->sc_dma. Prepare 578 * for DMA transfer. On the Sun3/E, this means we have to 579 * allocate space in the DMA buffer for this transfer. 580 */ 581 void 582 se_dma_alloc(ncr_sc) 583 struct ncr5380_softc *ncr_sc; 584 { 585 struct se_softc *sc = (struct se_softc *)ncr_sc; 586 struct sci_req *sr = ncr_sc->sc_current; 587 struct scsipi_xfer *xs = sr->sr_xs; 588 struct se_dma_handle *dh; 589 int i, xlen; 590 u_long addr; 591 592 #ifdef DIAGNOSTIC 593 if (sr->sr_dma_hand != NULL) 594 panic("se_dma_alloc: already have DMA handle"); 595 #endif 596 597 addr = (u_long) ncr_sc->sc_dataptr; 598 xlen = ncr_sc->sc_datalen; 599 600 /* If the DMA start addr is misaligned then do PIO */ 601 if ((addr & 1) || (xlen & 1)) { 602 printf("se_dma_alloc: misaligned.\n"); 603 return; 604 } 605 606 /* Make sure our caller checked sc_min_dma_len. */ 607 if (xlen < MIN_DMA_LEN) 608 panic("se_dma_alloc: xlen=0x%x", xlen); 609 610 /* 611 * Never attempt single transfers of more than 63k, because 612 * our count register may be only 16 bits (an OBIO adapter). 613 * This should never happen since already bounded by minphys(). 614 * XXX - Should just segment these... 615 */ 616 if (xlen > MAX_DMA_LEN) { 617 printf("se_dma_alloc: excessive xlen=0x%x\n", xlen); 618 ncr_sc->sc_datalen = xlen = MAX_DMA_LEN; 619 } 620 621 /* Find free DMA handle. Guaranteed to find one since we have 622 as many DMA handles as the driver has processes. */ 623 for (i = 0; i < SCI_OPENINGS; i++) { 624 if ((sc->sc_dma[i].dh_flags & SIDH_BUSY) == 0) 625 goto found; 626 } 627 panic("se: no free DMA handles."); 628 found: 629 630 dh = &sc->sc_dma[i]; 631 dh->dh_flags = SIDH_BUSY; 632 633 /* Copy the "write" flag for convenience. */ 634 if (xs->xs_control & XS_CTL_DATA_OUT) 635 dh->dh_flags |= SIDH_OUT; 636 637 dh->dh_addr = (u_char*) addr; 638 dh->dh_maplen = xlen; 639 dh->dh_dma = 0; /* XXX - Allocate space in DMA buffer. */ 640 /* XXX: dh->dh_dma = alloc(xlen) */ 641 if (!dh->dh_dma) { 642 /* Can't remap segment */ 643 printf("se_dma_alloc: can't remap %p/0x%x\n", 644 dh->dh_addr, dh->dh_maplen); 645 dh->dh_flags = 0; 646 return; 647 } 648 649 /* success */ 650 sr->sr_dma_hand = dh; 651 652 return; 653 } 654 655 656 void 657 se_dma_free(ncr_sc) 658 struct ncr5380_softc *ncr_sc; 659 { 660 struct sci_req *sr = ncr_sc->sc_current; 661 struct se_dma_handle *dh = sr->sr_dma_hand; 662 663 #ifdef DIAGNOSTIC 664 if (dh == NULL) 665 panic("se_dma_free: no DMA handle"); 666 #endif 667 668 if (ncr_sc->sc_state & NCR_DOINGDMA) 669 panic("se_dma_free: free while in progress"); 670 671 if (dh->dh_flags & SIDH_BUSY) { 672 /* XXX: Should separate allocation and mapping. */ 673 /* XXX: Give back the DMA space. */ 674 /* XXX: free((caddr_t)dh->dh_dma, dh->dh_maplen); */ 675 dh->dh_dma = 0; 676 dh->dh_flags = 0; 677 } 678 sr->sr_dma_hand = NULL; 679 } 680 681 682 #define CSR_MASK SE_CSR_SBC_IP 683 #define POLL_TIMO 50000 /* X100 = 5 sec. */ 684 685 /* 686 * Poll (spin-wait) for DMA completion. 687 * Called right after xx_dma_start(), and 688 * xx_dma_stop() will be called next. 689 * Same for either VME or OBIO. 690 */ 691 void 692 se_dma_poll(ncr_sc) 693 struct ncr5380_softc *ncr_sc; 694 { 695 struct se_softc *sc = (struct se_softc *)ncr_sc; 696 struct sci_req *sr = ncr_sc->sc_current; 697 volatile struct se_regs *se = sc->sc_regs; 698 int tmo; 699 700 /* Make sure DMA started successfully. */ 701 if (ncr_sc->sc_state & NCR_ABORTING) 702 return; 703 704 /* 705 * XXX: The Sun driver waits for ~SE_CSR_DMA_ACTIVE here 706 * XXX: (on obio) or even worse (on vme) a 10mS. delay! 707 * XXX: I really doubt that is necessary... 708 */ 709 710 /* Wait for any "DMA complete" or error bits. */ 711 tmo = POLL_TIMO; 712 for (;;) { 713 if (se->se_csr & CSR_MASK) 714 break; 715 if (--tmo <= 0) { 716 printf("se: DMA timeout (while polling)\n"); 717 /* Indicate timeout as MI code would. */ 718 sr->sr_flags |= SR_OVERDUE; 719 break; 720 } 721 delay(100); 722 } 723 NCR_TRACE("se_dma_poll: waited %d\n", 724 POLL_TIMO - tmo); 725 726 #ifdef DEBUG 727 if (se_debug & 2) { 728 printf("se_dma_poll: done, csr=0x%x\n", se->se_csr); 729 } 730 #endif 731 } 732 733
Indexes created Thu Oct 02 14:10:14 GMT 2025