si_sebuf.c revision 1.6
1 /* $NetBSD: si_sebuf.c,v 1.6 1998/10/10 00:28:39 thorpej Exp $ */ 2 3 /*- 4 * Copyright (c) 1996 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Gordon W. Ross. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 /* 40 * Sun3/E SCSI driver (machine-dependent portion). 41 * The machine-independent parts are in ncr5380sbc.c 42 * 43 * XXX - Mostly from the si driver. Merge? 44 */ 45 46 #include <sys/param.h> 47 #include <sys/systm.h> 48 #include <sys/errno.h> 49 #include <sys/kernel.h> 50 #include <sys/malloc.h> 51 #include <sys/device.h> 52 #include <sys/buf.h> 53 #include <sys/proc.h> 54 #include <sys/user.h> 55 56 #include <dev/scsipi/scsi_all.h> 57 #include <dev/scsipi/scsipi_all.h> 58 #include <dev/scsipi/scsipi_debug.h> 59 #include <dev/scsipi/scsiconf.h> 60 61 #include <machine/autoconf.h> 62 63 /* #define DEBUG XXX */ 64 65 #include <dev/ic/ncr5380reg.h> 66 #include <dev/ic/ncr5380var.h> 67 68 #include "sereg.h" 69 #include "sevar.h" 70 71 /* 72 * Transfers smaller than this are done using PIO 73 * (on assumption they're not worth DMA overhead) 74 */ 75 #define MIN_DMA_LEN 128 76 77 /* 78 * Transfers lager than 65535 bytes need to be split-up. 79 * (Some of the FIFO logic has only 16 bits counters.) 80 * Make the size an integer multiple of the page size 81 * to avoid buf/cluster remap problems. (paranoid?) 82 */ 83 #define MAX_DMA_LEN 0xE000 84 85 /* 86 * This structure is used to keep track of mapped DMA requests. 87 */ 88 struct se_dma_handle { 89 int dh_flags; 90 #define SIDH_BUSY 1 /* This DH is in use */ 91 #define SIDH_OUT 2 /* DMA does data out (write) */ 92 u_char * dh_addr; /* KVA of start of buffer */ 93 int dh_maplen; /* Length of KVA mapping. */ 94 long dh_dma; /* Offset in DMA buffer. */ 95 }; 96 97 /* 98 * The first structure member has to be the ncr5380_softc 99 * so we can just cast to go back and fourth between them. 100 */ 101 struct se_softc { 102 struct ncr5380_softc ncr_sc; 103 volatile struct se_regs *sc_regs; 104 int sc_adapter_type; 105 int sc_adapter_iv; /* int. vec */ 106 int sc_options; /* options for this instance */ 107 int sc_reqlen; /* requested transfer length */ 108 struct se_dma_handle *sc_dma; 109 /* DMA command block for the OBIO controller. */ 110 void *sc_dmacmd; 111 }; 112 113 /* Options for disconnect/reselect, DMA, and interrupts. */ 114 #define SE_NO_DISCONNECT 0xff 115 #define SE_NO_PARITY_CHK 0xff00 116 #define SE_FORCE_POLLING 0x10000 117 #define SE_DISABLE_DMA 0x20000 118 119 void se_dma_alloc __P((struct ncr5380_softc *)); 120 void se_dma_free __P((struct ncr5380_softc *)); 121 void se_dma_poll __P((struct ncr5380_softc *)); 122 123 void se_dma_setup __P((struct ncr5380_softc *)); 124 void se_dma_start __P((struct ncr5380_softc *)); 125 void se_dma_eop __P((struct ncr5380_softc *)); 126 void se_dma_stop __P((struct ncr5380_softc *)); 127 128 void se_intr_on __P((struct ncr5380_softc *)); 129 void se_intr_off __P((struct ncr5380_softc *)); 130 131 static int se_intr __P((void *)); 132 static void se_reset __P((struct ncr5380_softc *)); 133 134 /* 135 * New-style autoconfig attachment 136 */ 137 138 static int se_match __P((struct device *, struct cfdata *, void *)); 139 static void se_attach __P((struct device *, struct device *, void *)); 140 141 struct cfattach si_sebuf_ca = { 142 sizeof(struct se_softc), se_match, se_attach 143 }; 144 145 static void se_minphys __P((struct buf *)); 146 static struct scsipi_adapter se_ops = { 147 ncr5380_scsi_cmd, /* scsipi_cmd() */ 148 se_minphys, /* scsipi_minphys() */ 149 NULL, /* scsipi_ioctl() */ 150 }; 151 152 /* This is copied from julian's bt driver */ 153 /* "so we have a default dev struct for our link struct." */ 154 static struct scsipi_device se_dev = { 155 NULL, /* Use default error handler. */ 156 NULL, /* Use default start handler. */ 157 NULL, /* Use default async handler. */ 158 NULL, /* Use default "done" routine. */ 159 }; 160 161 /* Options for disconnect/reselect, DMA, and interrupts. */ 162 int se_options = SE_DISABLE_DMA | SE_FORCE_POLLING | 0xff; 163 164 /* How long to wait for DMA before declaring an error. */ 165 int se_dma_intr_timo = 500; /* ticks (sec. X 100) */ 166 167 int se_debug = 0; 168 #ifdef DEBUG 169 static int se_link_flags = 0 /* | SDEV_DB2 */ ; 170 #endif 171 172 173 static int 174 se_match(parent, cf, args) 175 struct device *parent; 176 struct cfdata *cf; 177 void *args; 178 { 179 struct sebuf_attach_args *aa = args; 180 181 /* Match by name. */ 182 if (strcmp(aa->name, "se")) 183 return (0); 184 185 /* Anyting else to check? */ 186 187 return (1); 188 } 189 190 static void 191 se_attach(parent, self, args) 192 struct device *parent, *self; 193 void *args; 194 { 195 struct se_softc *sc = (struct se_softc *) self; 196 struct ncr5380_softc *ncr_sc = &sc->ncr_sc; 197 struct cfdata *cf = self->dv_cfdata; 198 struct sebuf_attach_args *aa = args; 199 volatile struct se_regs *regs; 200 int i; 201 202 /* Get options from config flags if specified. */ 203 if (cf->cf_flags) 204 sc->sc_options = cf->cf_flags; 205 else 206 sc->sc_options = se_options; 207 208 printf(": options=0x%x\n", sc->sc_options); 209 210 sc->sc_adapter_type = aa->ca.ca_bustype; 211 sc->sc_adapter_iv = aa->ca.ca_intvec; 212 sc->sc_regs = regs = aa->regs; 213 214 /* 215 * MD function pointers used by the MI code. 216 */ 217 ncr_sc->sc_pio_out = ncr5380_pio_out; 218 ncr_sc->sc_pio_in = ncr5380_pio_in; 219 220 #if 0 /* XXX - not yet... */ 221 ncr_sc->sc_dma_alloc = se_dma_alloc; 222 ncr_sc->sc_dma_free = se_dma_free; 223 ncr_sc->sc_dma_setup = se_dma_setup; 224 ncr_sc->sc_dma_start = se_dma_start; 225 ncr_sc->sc_dma_poll = se_dma_poll; 226 ncr_sc->sc_dma_eop = se_dma_eop; 227 ncr_sc->sc_dma_stop = se_dma_stop; 228 ncr_sc->sc_intr_on = se_intr_on; 229 ncr_sc->sc_intr_off = se_intr_off; 230 #endif /* XXX */ 231 232 /* Attach interrupt handler. */ 233 isr_add_vectored(se_intr, (void *)sc, 234 aa->ca.ca_intpri, aa->ca.ca_intvec); 235 236 /* Reset the hardware. */ 237 se_reset(ncr_sc); 238 239 /* Do the common attach stuff. */ 240 241 /* 242 * Support the "options" (config file flags). 243 * Disconnect/reselect is a per-target mask. 244 * Interrupts and DMA are per-controller. 245 */ 246 ncr_sc->sc_no_disconnect = 247 (sc->sc_options & SE_NO_DISCONNECT); 248 ncr_sc->sc_parity_disable = 249 (sc->sc_options & SE_NO_PARITY_CHK) >> 8; 250 if (sc->sc_options & SE_FORCE_POLLING) 251 ncr_sc->sc_flags |= NCR5380_FORCE_POLLING; 252 253 #if 1 /* XXX - Temporary */ 254 /* XXX - In case we think DMA is completely broken... */ 255 if (sc->sc_options & SE_DISABLE_DMA) { 256 /* Override this function pointer. */ 257 ncr_sc->sc_dma_alloc = NULL; 258 } 259 #endif 260 ncr_sc->sc_min_dma_len = MIN_DMA_LEN; 261 262 /* 263 * Fill in the prototype scsi_link. 264 */ 265 ncr_sc->sc_link.scsipi_scsi.channel = SCSI_CHANNEL_ONLY_ONE; 266 ncr_sc->sc_link.adapter_softc = sc; 267 ncr_sc->sc_link.scsipi_scsi.adapter_target = 7; 268 ncr_sc->sc_link.adapter = &se_ops; 269 ncr_sc->sc_link.device = &se_dev; 270 ncr_sc->sc_link.type = BUS_SCSI; 271 272 #ifdef DEBUG 273 if (se_debug) 274 printf("se: Set TheSoftC=%p TheRegs=%p\n", sc, regs); 275 ncr_sc->sc_link.flags |= se_link_flags; 276 #endif 277 278 /* 279 * Initialize fields used by the MI code 280 */ 281 ncr_sc->sci_r0 = ®s->ncrregs[0]; 282 ncr_sc->sci_r1 = ®s->ncrregs[1]; 283 ncr_sc->sci_r2 = ®s->ncrregs[2]; 284 ncr_sc->sci_r3 = ®s->ncrregs[3]; 285 ncr_sc->sci_r4 = ®s->ncrregs[4]; 286 ncr_sc->sci_r5 = ®s->ncrregs[5]; 287 ncr_sc->sci_r6 = ®s->ncrregs[6]; 288 ncr_sc->sci_r7 = ®s->ncrregs[7]; 289 290 /* 291 * Allocate DMA handles. 292 */ 293 i = SCI_OPENINGS * sizeof(struct se_dma_handle); 294 sc->sc_dma = (struct se_dma_handle *) 295 malloc(i, M_DEVBUF, M_WAITOK); 296 if (sc->sc_dma == NULL) 297 panic("se: dma_malloc failed\n"); 298 for (i = 0; i < SCI_OPENINGS; i++) 299 sc->sc_dma[i].dh_flags = 0; 300 301 /* 302 * Initialize se board itself. 303 */ 304 ncr5380_init(ncr_sc); 305 ncr5380_reset_scsibus(ncr_sc); 306 config_found(&(ncr_sc->sc_dev), &(ncr_sc->sc_link), scsiprint); 307 } 308 309 static void 310 se_reset(struct ncr5380_softc *ncr_sc) 311 { 312 struct se_softc *sc = (struct se_softc *)ncr_sc; 313 volatile struct se_regs *se = sc->sc_regs; 314 315 #ifdef DEBUG 316 if (se_debug) { 317 printf("se_reset\n"); 318 } 319 #endif 320 321 /* The reset bits in the CSR are active low. */ 322 se->se_csr = 0; 323 delay(10); 324 se->se_csr = SE_CSR_SCSI_RES /* | SE_CSR_INTR_EN */ ; 325 delay(10); 326 327 /* Make sure the DMA engine is stopped. */ 328 se->dma_addr = 0; 329 se->dma_cntr = 0; 330 se->se_ivec = sc->sc_adapter_iv; 331 } 332 333 /* 334 * This is called when the bus is going idle, 335 * so we want to enable the SBC interrupts. 336 * That is controlled by the DMA enable! 337 * Who would have guessed! 338 * What a NASTY trick! 339 */ 340 void 341 se_intr_on(ncr_sc) 342 struct ncr5380_softc *ncr_sc; 343 { 344 struct se_softc *sc = (struct se_softc *)ncr_sc; 345 volatile struct se_regs *se = sc->sc_regs; 346 347 /* receive mode should be safer */ 348 se->se_csr &= ~SE_CSR_SEND; 349 350 /* Clear the count so nothing happens. */ 351 se->dma_cntr = 0; 352 353 /* Clear the start address too. (paranoid?) */ 354 se->dma_addr = 0; 355 356 /* Finally, enable the DMA engine. */ 357 se->se_csr |= SE_CSR_INTR_EN; 358 } 359 360 /* 361 * This is called when the bus is idle and we are 362 * about to start playing with the SBC chip. 363 */ 364 void 365 se_intr_off(ncr_sc) 366 struct ncr5380_softc *ncr_sc; 367 { 368 struct se_softc *sc = (struct se_softc *)ncr_sc; 369 volatile struct se_regs *se = sc->sc_regs; 370 371 se->se_csr &= ~SE_CSR_INTR_EN; 372 } 373 374 /* 375 * This function is called during the COMMAND or MSG_IN phase 376 * that preceeds a DATA_IN or DATA_OUT phase, in case we need 377 * to setup the DMA engine before the bus enters a DATA phase. 378 * 379 * On the VME version, setup the start addres, but clear the 380 * count (to make sure it stays idle) and set that later. 381 * XXX: The VME adapter appears to suppress SBC interrupts 382 * when the FIFO is not empty or the FIFO count is non-zero! 383 * XXX: Need to copy data into the DMA buffer... 384 */ 385 void 386 se_dma_setup(ncr_sc) 387 struct ncr5380_softc *ncr_sc; 388 { 389 struct se_softc *sc = (struct se_softc *)ncr_sc; 390 struct sci_req *sr = ncr_sc->sc_current; 391 struct se_dma_handle *dh = sr->sr_dma_hand; 392 volatile struct se_regs *se = sc->sc_regs; 393 long data_pa; 394 int xlen; 395 396 /* 397 * Get the DMA mapping for this segment. 398 * XXX - Should separate allocation and mapin. 399 */ 400 data_pa = 0; /* XXX se_dma_kvtopa(dh->dh_dma); */ 401 data_pa += (ncr_sc->sc_dataptr - dh->dh_addr); 402 if (data_pa & 1) 403 panic("se_dma_start: bad pa=0x%lx", data_pa); 404 xlen = ncr_sc->sc_datalen; 405 xlen &= ~1; /* XXX: necessary? */ 406 sc->sc_reqlen = xlen; /* XXX: or less? */ 407 408 #ifdef DEBUG 409 if (se_debug & 2) { 410 printf("se_dma_setup: dh=%p, pa=0x%lx, xlen=0x%x\n", 411 dh, data_pa, xlen); 412 } 413 #endif 414 415 /* Set direction (send/recv) */ 416 if (dh->dh_flags & SIDH_OUT) { 417 se->se_csr |= SE_CSR_SEND; 418 } else { 419 se->se_csr &= ~SE_CSR_SEND; 420 } 421 422 /* Load the start address. */ 423 se->dma_addr = (ushort)(data_pa & 0xFFFF); 424 425 /* 426 * Keep the count zero or it may start early! 427 */ 428 se->dma_cntr = 0; 429 } 430 431 432 void 433 se_dma_start(ncr_sc) 434 struct ncr5380_softc *ncr_sc; 435 { 436 struct se_softc *sc = (struct se_softc *)ncr_sc; 437 struct sci_req *sr = ncr_sc->sc_current; 438 struct se_dma_handle *dh = sr->sr_dma_hand; 439 volatile struct se_regs *se = sc->sc_regs; 440 int s, xlen; 441 442 xlen = sc->sc_reqlen; 443 444 /* This MAY be time critical (not sure). */ 445 s = splhigh(); 446 447 se->dma_cntr = (ushort)(xlen & 0xFFFF); 448 449 /* 450 * Acknowledge the phase change. (After DMA setup!) 451 * Put the SBIC into DMA mode, and start the transfer. 452 */ 453 if (dh->dh_flags & SIDH_OUT) { 454 *ncr_sc->sci_tcmd = PHASE_DATA_OUT; 455 SCI_CLR_INTR(ncr_sc); 456 *ncr_sc->sci_icmd = SCI_ICMD_DATA; 457 *ncr_sc->sci_mode |= (SCI_MODE_DMA | SCI_MODE_DMA_IE); 458 *ncr_sc->sci_dma_send = 0; /* start it */ 459 } else { 460 *ncr_sc->sci_tcmd = PHASE_DATA_IN; 461 SCI_CLR_INTR(ncr_sc); 462 *ncr_sc->sci_icmd = 0; 463 *ncr_sc->sci_mode |= (SCI_MODE_DMA | SCI_MODE_DMA_IE); 464 *ncr_sc->sci_irecv = 0; /* start it */ 465 } 466 467 /* Let'er rip! */ 468 se->se_csr |= SE_CSR_INTR_EN; 469 470 splx(s); 471 ncr_sc->sc_state |= NCR_DOINGDMA; 472 473 #ifdef DEBUG 474 if (se_debug & 2) { 475 printf("se_dma_start: started, flags=0x%x\n", 476 ncr_sc->sc_state); 477 } 478 #endif 479 } 480 481 482 void 483 se_dma_eop(ncr_sc) 484 struct ncr5380_softc *ncr_sc; 485 { 486 487 /* Not needed - DMA was stopped prior to examining sci_csr */ 488 } 489 490 491 void 492 se_dma_stop(ncr_sc) 493 struct ncr5380_softc *ncr_sc; 494 { 495 struct se_softc *sc = (struct se_softc *)ncr_sc; 496 struct sci_req *sr = ncr_sc->sc_current; 497 struct se_dma_handle *dh = sr->sr_dma_hand; 498 volatile struct se_regs *se = sc->sc_regs; 499 int resid, ntrans; 500 501 if ((ncr_sc->sc_state & NCR_DOINGDMA) == 0) { 502 #ifdef DEBUG 503 printf("se_dma_stop: dma not running\n"); 504 #endif 505 return; 506 } 507 ncr_sc->sc_state &= ~NCR_DOINGDMA; 508 509 /* First, halt the DMA engine. */ 510 se->se_csr &= ~SE_CSR_INTR_EN; /* VME only */ 511 512 /* Set an impossible phase to prevent data movement? */ 513 *ncr_sc->sci_tcmd = PHASE_INVALID; 514 515 /* Note that timeout may have set the error flag. */ 516 if (ncr_sc->sc_state & NCR_ABORTING) 517 goto out; 518 519 /* XXX: Wait for DMA to actually finish? */ 520 521 /* 522 * Now try to figure out how much actually transferred 523 */ 524 resid = se->dma_cntr & 0xFFFF; 525 if (dh->dh_flags & SIDH_OUT) 526 if ((resid > 0) && (resid < sc->sc_reqlen)) 527 resid++; 528 ntrans = sc->sc_reqlen - resid; 529 530 #ifdef DEBUG 531 if (se_debug & 2) { 532 printf("se_dma_stop: resid=0x%x ntrans=0x%x\n", 533 resid, ntrans); 534 } 535 #endif 536 537 if (ntrans < MIN_DMA_LEN) { 538 printf("se: fifo count: 0x%x\n", resid); 539 ncr_sc->sc_state |= NCR_ABORTING; 540 goto out; 541 } 542 if (ntrans > ncr_sc->sc_datalen) 543 panic("se_dma_stop: excess transfer"); 544 545 /* Adjust data pointer */ 546 ncr_sc->sc_dataptr += ntrans; 547 ncr_sc->sc_datalen -= ntrans; 548 549 out: 550 se->dma_addr = 0; 551 se->dma_cntr = 0; 552 553 /* Put SBIC back in PIO mode. */ 554 *ncr_sc->sci_mode &= ~(SCI_MODE_DMA | SCI_MODE_DMA_IE); 555 *ncr_sc->sci_icmd = 0; 556 } 557 558 /*****************************************************************/ 559 560 static void 561 se_minphys(struct buf *bp) 562 { 563 if (bp->b_bcount > MAX_DMA_LEN) { 564 #ifdef DEBUG 565 if (se_debug) { 566 printf("se_minphys len = 0x%x.\n", bp->b_bcount); 567 Debugger(); 568 } 569 #endif 570 bp->b_bcount = MAX_DMA_LEN; 571 } 572 return (minphys(bp)); 573 } 574 575 576 int 577 se_intr(void *arg) 578 { 579 struct se_softc *sc = arg; 580 volatile struct se_regs *se = sc->sc_regs; 581 int dma_error, claimed; 582 u_short csr; 583 584 claimed = 0; 585 dma_error = 0; 586 587 /* SBC interrupt? DMA interrupt? */ 588 csr = se->se_csr; 589 NCR_TRACE("se_intr: csr=0x%x\n", csr); 590 591 if (csr & SE_CSR_SBC_IP) { 592 claimed = ncr5380_intr(&sc->ncr_sc); 593 #ifdef DEBUG 594 if (!claimed) { 595 printf("se_intr: spurious from SBC\n"); 596 if (se_debug & 4) { 597 Debugger(); /* XXX */ 598 } 599 } 600 #endif 601 /* Yes, we DID cause this interrupt. */ 602 claimed = 1; 603 } 604 605 return (claimed); 606 } 607 608 609 /***************************************************************** 610 * Common functions for DMA 611 ****************************************************************/ 612 613 /* 614 * Allocate a DMA handle and put it in sc->sc_dma. Prepare 615 * for DMA transfer. On the Sun3/E, this means we have to 616 * allocate space in the DMA buffer for this transfer. 617 */ 618 void 619 se_dma_alloc(ncr_sc) 620 struct ncr5380_softc *ncr_sc; 621 { 622 struct se_softc *sc = (struct se_softc *)ncr_sc; 623 struct sci_req *sr = ncr_sc->sc_current; 624 struct scsipi_xfer *xs = sr->sr_xs; 625 struct se_dma_handle *dh; 626 int i, xlen; 627 u_long addr; 628 629 #ifdef DIAGNOSTIC 630 if (sr->sr_dma_hand != NULL) 631 panic("se_dma_alloc: already have DMA handle"); 632 #endif 633 634 addr = (u_long) ncr_sc->sc_dataptr; 635 xlen = ncr_sc->sc_datalen; 636 637 /* If the DMA start addr is misaligned then do PIO */ 638 if ((addr & 1) || (xlen & 1)) { 639 printf("se_dma_alloc: misaligned.\n"); 640 return; 641 } 642 643 /* Make sure our caller checked sc_min_dma_len. */ 644 if (xlen < MIN_DMA_LEN) 645 panic("se_dma_alloc: xlen=0x%x\n", xlen); 646 647 /* 648 * Never attempt single transfers of more than 63k, because 649 * our count register may be only 16 bits (an OBIO adapter). 650 * This should never happen since already bounded by minphys(). 651 * XXX - Should just segment these... 652 */ 653 if (xlen > MAX_DMA_LEN) { 654 printf("se_dma_alloc: excessive xlen=0x%x\n", xlen); 655 Debugger(); 656 ncr_sc->sc_datalen = xlen = MAX_DMA_LEN; 657 } 658 659 /* Find free DMA handle. Guaranteed to find one since we have 660 as many DMA handles as the driver has processes. */ 661 for (i = 0; i < SCI_OPENINGS; i++) { 662 if ((sc->sc_dma[i].dh_flags & SIDH_BUSY) == 0) 663 goto found; 664 } 665 panic("se: no free DMA handles."); 666 found: 667 668 dh = &sc->sc_dma[i]; 669 dh->dh_flags = SIDH_BUSY; 670 671 /* Copy the "write" flag for convenience. */ 672 if (xs->flags & SCSI_DATA_OUT) 673 dh->dh_flags |= SIDH_OUT; 674 675 dh->dh_addr = (u_char*) addr; 676 dh->dh_maplen = xlen; 677 dh->dh_dma = 0; /* XXX - Allocate space in DMA buffer. */ 678 /* XXX: dh->dh_dma = alloc(xlen) */ 679 if (!dh->dh_dma) { 680 /* Can't remap segment */ 681 printf("se_dma_alloc: can't remap %p/0x%x\n", 682 dh->dh_addr, dh->dh_maplen); 683 dh->dh_flags = 0; 684 return; 685 } 686 687 /* success */ 688 sr->sr_dma_hand = dh; 689 690 return; 691 } 692 693 694 void 695 se_dma_free(ncr_sc) 696 struct ncr5380_softc *ncr_sc; 697 { 698 struct sci_req *sr = ncr_sc->sc_current; 699 struct se_dma_handle *dh = sr->sr_dma_hand; 700 701 #ifdef DIAGNOSTIC 702 if (dh == NULL) 703 panic("se_dma_free: no DMA handle"); 704 #endif 705 706 if (ncr_sc->sc_state & NCR_DOINGDMA) 707 panic("se_dma_free: free while in progress"); 708 709 if (dh->dh_flags & SIDH_BUSY) { 710 /* XXX: Should separate allocation and mapping. */ 711 /* XXX: Give back the DMA space. */ 712 /* XXX: free((caddr_t)dh->dh_dma, dh->dh_maplen); */ 713 dh->dh_dma = 0; 714 dh->dh_flags = 0; 715 } 716 sr->sr_dma_hand = NULL; 717 } 718 719 720 #define CSR_MASK SE_CSR_SBC_IP 721 #define POLL_TIMO 50000 /* X100 = 5 sec. */ 722 723 /* 724 * Poll (spin-wait) for DMA completion. 725 * Called right after xx_dma_start(), and 726 * xx_dma_stop() will be called next. 727 * Same for either VME or OBIO. 728 */ 729 void 730 se_dma_poll(ncr_sc) 731 struct ncr5380_softc *ncr_sc; 732 { 733 struct se_softc *sc = (struct se_softc *)ncr_sc; 734 struct sci_req *sr = ncr_sc->sc_current; 735 volatile struct se_regs *se = sc->sc_regs; 736 int tmo; 737 738 /* Make sure DMA started successfully. */ 739 if (ncr_sc->sc_state & NCR_ABORTING) 740 return; 741 742 /* 743 * XXX: The Sun driver waits for ~SE_CSR_DMA_ACTIVE here 744 * XXX: (on obio) or even worse (on vme) a 10mS. delay! 745 * XXX: I really doubt that is necessary... 746 */ 747 748 /* Wait for any "dma complete" or error bits. */ 749 tmo = POLL_TIMO; 750 for (;;) { 751 if (se->se_csr & CSR_MASK) 752 break; 753 if (--tmo <= 0) { 754 printf("se: DMA timeout (while polling)\n"); 755 /* Indicate timeout as MI code would. */ 756 sr->sr_flags |= SR_OVERDUE; 757 break; 758 } 759 delay(100); 760 } 761 NCR_TRACE("se_dma_poll: waited %d\n", 762 POLL_TIMO - tmo); 763 764 #ifdef DEBUG 765 if (se_debug & 2) { 766 printf("se_dma_poll: done, csr=0x%x\n", se->se_csr); 767 } 768 #endif 769 } 770 771
Indexes created Thu Oct 02 14:10:14 GMT 2025