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cpu.h revision 1.1
      1 /* Copyright (c) 1993 Adam Glass
      2  * Copyright (c) 1988 University of Utah.
      3  * Copyright (c) 1982, 1990 The Regents of the University of California.
      4  * All rights reserved.
      5  *
      6  * This code is derived from software contributed to Berkeley by
      7  * the Systems Programming Group of the University of Utah Computer
      8  * Science Department.
      9  *
     10  * Redistribution and use in source and binary forms, with or without
     11  * modification, are permitted provided that the following conditions
     12  * are met:
     13  * 1. Redistributions of source code must retain the above copyright
     14  *    notice, this list of conditions and the following disclaimer.
     15  * 2. Redistributions in binary form must reproduce the above copyright
     16  *    notice, this list of conditions and the following disclaimer in the
     17  *    documentation and/or other materials provided with the distribution.
     18  * 3. All advertising materials mentioning features or use of this software
     19  *    must display the following acknowledgement:
     20  *	This product includes software developed by the University of
     21  *	California, Berkeley and its contributors.
     22  * 4. Neither the name of the University nor the names of its contributors
     23  *    may be used to endorse or promote products derived from this software
     24  *    without specific prior written permission.
     25  *
     26  * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
     27  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
     28  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
     29  * ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
     30  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
     31  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
     32  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
     33  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
     34  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
     35  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
     36  * SUCH DAMAGE.
     37  *
     38  * from: Utah $Hdr: cpu.h 1.16 91/03/25$
     39  *
     40  *	from: @(#)cpu.h	7.7 (Berkeley) 6/27/91
     41  *	cpu.h,v 1.2 1993/05/22 07:58:17 cgd Exp
     42  */
     43 
     44 /*
     45  * Exported definitions unique to sun3/68k cpu support.
     46  */
     47 
     48 /*
     49  * definitions of cpu-dependent requirements
     50  * referenced in generic code
     51  */
     52 #define	COPY_SIGCODE		/* copy sigcode above user stack in exec */
     53 
     54 /*
     55  * function vs. inline configuration;
     56  * these are defined to get generic functions
     57  * rather than inline or machine-dependent implementations
     58  */
     59 #define	NEED_MINMAX		/* need {,i,l,ul}{min,max} functions */
     60 #define	NEED_FFS		/* don't need ffs function */
     61 #define	NEED_BCMP		/* don't need bcmp function */
     62 #define	NEED_STRLEN		/* don't need strlen function */
     63 
     64 #define	cpu_exec(p)	/* nothing */
     65 #define	cpu_wait(p)	/* nothing */
     66 
     67 /*
     68  * Arguments to hardclock, softclock and gatherstats
     69  * encapsulate the previous machine state in an opaque
     70  * clockframe; for hp300, use just what the hardware
     71  * leaves on the stack.
     72  */
     73 typedef struct intrframe {
     74 	int	pc;
     75 	int	ps;
     76 } clockframe;
     77 
     78 #define	CLKF_USERMODE(framep)	(((framep)->ps & PSL_S) == 0)
     79 #define	CLKF_BASEPRI(framep)	(((framep)->ps & PSL_IPL7) == 0)
     80 #define	CLKF_PC(framep)		((framep)->pc)
     81 
     82 /*
     83  * Preempt the current process if in interrupt from user mode,
     84  * or after the current trap/syscall if in system mode.
     85  */
     86 #define	need_resched()	{ want_resched++; aston(); }
     87 
     88 /*
     89  * Give a profiling tick to the current process from the softclock
     90  * interrupt.  On hp300, request an ast to send us through trap(),
     91  * marking the proc as needing a profiling tick.
     92  */
     93 #define	profile_tick(p, framep)	{ (p)->p_flag |= SOWEUPC; aston(); }
     94 
     95 /*
     96  * Notify the current process (p) that it has a signal pending,
     97  * process as soon as possible.
     98  */
     99 #define	signotify(p)	aston()
    100 
    101 #define aston() (astpending++)
    102 
    103 int	astpending;		/* need to trap before returning to user mode */
    104 int	want_resched;		/* resched() was called */
    105 
    106 
    107 
    108 /*
    109  * The rest of this should probably be moved to ../hp300/hp300cpu.h,
    110  * although some of it could probably be put into generic 68k headers.
    111  */
    112 
    113 /* values for machineid */
    114 
    115 #define CPU_ARCH_MASK  0xf0
    116 #define SUN3_ARCH      0x10
    117 #define SUN3_IMPL_MASK 0x0f
    118 #define SUN3_MACH_160  0x01
    119 #define SUN3_MACH_50   0x02
    120 #define SUN3_MACH_260  0x03
    121 #define SUN3_MACH_110  0x04
    122 #define SUN3_MACH_60   0x07
    123 #define SUN3_MACH_E    0x08
    124 
    125 #ifdef KERNEL
    126 extern	int machineid, mmutype, ectype;
    127 extern	char *intiobase, *intiolimit;
    128 
    129 /* what is this supposed to do? i.e. how is it different than startrtclock? */
    130 #define	enablertclock()
    131 
    132 #endif
    133 
    134 /* 680X0 function codes */
    135 #define	FC_USERD	1	/* user data space */
    136 #define	FC_USERP	2	/* user program space */
    137 #define	FC_CONTROL	3	/* HPMMU: clear TLB entries */
    138 #define	FC_SUPERD	5	/* supervisor data space */
    139 #define	FC_SUPERP	6	/* supervisor program space */
    140 #define	FC_CPU		7	/* CPU space */
    141 
    142 /* fields in the 68020 cache control register */
    143 #define	IC_ENABLE	0x0001	/* enable instruction cache */
    144 #define	IC_FREEZE	0x0002	/* freeze instruction cache */
    145 #define	IC_CE		0x0004	/* clear instruction cache entry */
    146 #define	IC_CLR		0x0008	/* clear entire instruction cache */
    147 
    148