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z8530var.h revision 1.8
      1  1.8  chs /*	$NetBSD: z8530var.h,v 1.8 2002/03/11 07:11:26 chs Exp $	*/
      2  1.2  gwr 
      3  1.2  gwr /*
      4  1.2  gwr  * Copyright (c) 1994 Gordon W. Ross
      5  1.2  gwr  * Copyright (c) 1992, 1993
      6  1.2  gwr  *	The Regents of the University of California.  All rights reserved.
      7  1.2  gwr  *
      8  1.2  gwr  * This software was developed by the Computer Systems Engineering group
      9  1.2  gwr  * at Lawrence Berkeley Laboratory under DARPA contract BG 91-66 and
     10  1.2  gwr  * contributed to Berkeley.
     11  1.2  gwr  *
     12  1.2  gwr  * All advertising materials mentioning features or use of this software
     13  1.2  gwr  * must display the following acknowledgement:
     14  1.2  gwr  *	This product includes software developed by the University of
     15  1.2  gwr  *	California, Lawrence Berkeley Laboratory.
     16  1.2  gwr  *
     17  1.2  gwr  * Redistribution and use in source and binary forms, with or without
     18  1.2  gwr  * modification, are permitted provided that the following conditions
     19  1.2  gwr  * are met:
     20  1.2  gwr  * 1. Redistributions of source code must retain the above copyright
     21  1.2  gwr  *    notice, this list of conditions and the following disclaimer.
     22  1.2  gwr  * 2. Redistributions in binary form must reproduce the above copyright
     23  1.2  gwr  *    notice, this list of conditions and the following disclaimer in the
     24  1.2  gwr  *    documentation and/or other materials provided with the distribution.
     25  1.2  gwr  * 3. All advertising materials mentioning features or use of this software
     26  1.2  gwr  *    must display the following acknowledgement:
     27  1.2  gwr  *	This product includes software developed by the University of
     28  1.2  gwr  *	California, Berkeley and its contributors.
     29  1.2  gwr  * 4. Neither the name of the University nor the names of its contributors
     30  1.2  gwr  *    may be used to endorse or promote products derived from this software
     31  1.2  gwr  *    without specific prior written permission.
     32  1.2  gwr  *
     33  1.2  gwr  * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
     34  1.2  gwr  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
     35  1.2  gwr  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
     36  1.2  gwr  * ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
     37  1.2  gwr  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
     38  1.2  gwr  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
     39  1.2  gwr  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
     40  1.2  gwr  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
     41  1.2  gwr  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
     42  1.2  gwr  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
     43  1.2  gwr  * SUCH DAMAGE.
     44  1.2  gwr  *
     45  1.2  gwr  *	@(#)zsvar.h	8.1 (Berkeley) 6/11/93
     46  1.2  gwr  */
     47  1.2  gwr 
     48  1.2  gwr #include <dev/ic/z8530sc.h>
     49  1.2  gwr 
     50  1.6  gwr struct zsc_softc {
     51  1.6  gwr 	struct	device zsc_dev;		/* required first: base device */
     52  1.6  gwr 	struct	zs_chanstate *zsc_cs[2];	/* channel A and B soft state */
     53  1.6  gwr 	/* Machine-dependent part follows... */
     54  1.6  gwr 	struct zs_chanstate  zsc_cs_store[2];
     55  1.6  gwr };
     56  1.6  gwr 
     57  1.2  gwr /*
     58  1.3  gwr  * Functions to read and write individual registers in a channel.
     59  1.3  gwr  * The ZS chip requires a 1.6 uSec. recovery time between accesses,
     60  1.3  gwr  * and the Sun3 hardware does NOT take care of this for you.
     61  1.3  gwr  * The delay is now handled inside the chip access functions.
     62  1.3  gwr  * These could be inlines, but with the delay, speed is moot.
     63  1.2  gwr  */
     64  1.2  gwr 
     65  1.3  gwr u_char zs_read_reg __P((struct zs_chanstate *cs, u_char reg));
     66  1.3  gwr u_char zs_read_csr __P((struct zs_chanstate *cs));
     67  1.3  gwr u_char zs_read_data __P((struct zs_chanstate *cs));
     68  1.3  gwr 
     69  1.3  gwr void  zs_write_reg __P((struct zs_chanstate *cs, u_char reg, u_char val));
     70  1.3  gwr void  zs_write_csr __P((struct zs_chanstate *cs, u_char val));
     71  1.3  gwr void  zs_write_data __P((struct zs_chanstate *cs, u_char val));
     72  1.3  gwr 
     73  1.6  gwr /* Zilog Serial hardware interrupts (hard-wired at 6) */
     74  1.6  gwr #define splzs()         spl6()
     75  1.2  gwr 
     76  1.7  chs /* We want to call it "zs" instead of "zsc" (sigh). */
     77  1.7  chs #ifndef ZSCCF_CHANNEL
     78  1.7  chs #define ZSCCF_CHANNEL 0
     79  1.7  chs #define ZSCCF_CHANNEL_DEFAULT -1
     80  1.7  chs #endif
     81  1.8  chs 
     82  1.8  chs #undef cn_trap
     83  1.8  chs #define cn_trap() zs_abort(NULL)
     84