1 1.3 tsutsui /* $NetBSD: enable.h,v 1.3 2013/09/06 17:43:19 tsutsui Exp $ */ 2 1.1 gwr 3 1.1 gwr /*- 4 1.1 gwr * Copyright (c) 1997 The NetBSD Foundation, Inc. 5 1.1 gwr * All rights reserved. 6 1.1 gwr * 7 1.1 gwr * This code is derived from software contributed to The NetBSD Foundation 8 1.1 gwr * by Jeremy Cooper. 9 1.1 gwr * 10 1.1 gwr * Redistribution and use in source and binary forms, with or without 11 1.1 gwr * modification, are permitted provided that the following conditions 12 1.1 gwr * are met: 13 1.1 gwr * 1. Redistributions of source code must retain the above copyright 14 1.1 gwr * notice, this list of conditions and the following disclaimer. 15 1.1 gwr * 2. Redistributions in binary form must reproduce the above copyright 16 1.1 gwr * notice, this list of conditions and the following disclaimer in the 17 1.1 gwr * documentation and/or other materials provided with the distribution. 18 1.1 gwr * 19 1.1 gwr * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 1.1 gwr * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 1.1 gwr * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 1.1 gwr * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 1.1 gwr * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 1.1 gwr * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 1.1 gwr * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 1.1 gwr * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 1.1 gwr * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 1.1 gwr * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 1.1 gwr * POSSIBILITY OF SUCH DAMAGE. 30 1.1 gwr */ 31 1.1 gwr 32 1.1 gwr /* 33 1.1 gwr * System Enable Register 34 1.1 gwr * The Sun3x System Enable Register controls the function of a few 35 1.1 gwr * on-board devices and general system operation. It is cleared when 36 1.1 gwr * the system is reset. 37 1.1 gwr * 38 1.1 gwr * 15 0 39 1.1 gwr * +---+---+---+---+---+---+---+---+---+---+---+---+---+---.---.---+ 40 1.1 gwr * |BT |FPP|DMA| 0 |VID|RES|FPA|DIA| 0 |CCH|IOC|LBK|DCH| UNUSED | 41 1.1 gwr * +---+---+---+---+---+---+---+---+---+---+---+---+---+---.---.---+ 42 1.1 gwr * 43 1.3 tsutsui * 44 1.1 gwr * Bits in the Enable Register defined. 45 1.1 gwr */ 46 1.1 gwr #define ENA_DBGCACHE 0x0008 /* Debug mode for system cache */ 47 1.1 gwr #define ENA_LOOPBACK 0x0010 /* VME loopback mode */ 48 1.1 gwr #define ENA_IOCACHE 0x0020 /* Enable I/O cache */ 49 1.1 gwr #define ENA_CACHE 0x0040 /* Enable system cache */ 50 1.1 gwr #define ENA_DIAG 0x0100 /* Diagnostic switch */ 51 1.1 gwr #define ENA_FPA 0x0200 /* Enable floating point acc. */ 52 1.1 gwr #define ENA_RES 0x0400 /* Video display resolution (0 => hi, 1 => low) */ 53 1.1 gwr #define ENA_VIDEO 0x0800 /* Enable video display */ 54 1.1 gwr #define ENA_SDVMA 0x2000 /* Enable system DVMA */ 55 1.1 gwr #define ENA_FPP 0x4000 /* Enable floating point coprocessor */ 56 1.1 gwr #define ENA_NOTBOOT 0x8000 /* Non-boot state (0 => boot, 1 => normal) */ 57 1.1 gwr 58 1.1 gwr #ifdef _KERNEL 59 1.1 gwr extern volatile short *enable_reg; 60 1.1 gwr #endif 61 1.1 gwr 62
Indexes created Sat Sep 20 22:09:52 GMT 2025