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iommu.h revision 1.2 
      1 /*	$NetBSD: iommu.h,v 1.2 1997/01/16 06:38:26 jeremy Exp $	*/
      2 
      3 /*-
      4  * Copyright (c) 1996 The NetBSD Foundation, Inc.
      5  * All rights reserved.
      6  *
      7  * This code is derived from software contributed to The NetBSD Foundation
      8  * by Jeremy Cooper.
      9  *
     10  * Redistribution and use in source and binary forms, with or without
     11  * modification, are permitted provided that the following conditions
     12  * are met:
     13  * 1. Redistributions of source code must retain the above copyright
     14  *    notice, this list of conditions and the following disclaimer.
     15  * 2. Redistributions in binary form must reproduce the above copyright
     16  *    notice, this list of conditions and the following disclaimer in the
     17  *    documentation and/or other materials provided with the distribution.
     18  * 3. All advertising materials mentioning features or use of this software
     19  *    must display the following acknowledgement:
     20  *        This product includes software developed by the NetBSD
     21  *        Foundation, Inc. and its contributors.
     22  * 4. Neither the name of The NetBSD Foundation nor the names of its
     23  *    contributors may be used to endorse or promote products derived
     24  *    from this software without specific prior written permission.
     25  *
     26  * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
     27  * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
     28  * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
     29  * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
     30  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
     31  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
     32  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
     33  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
     34  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
     35  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
     36  * POSSIBILITY OF SUCH DAMAGE.
     37  */
     38 
     39 /*
     40  * Structure and definition of descriptors used in the I/O Mapper.
     41  */
     42 #ifndef _SUN3X_IOMMU_H
     43 #define _SUN3X_IOMMU_H
     44 
     45 /* The I/O Mapper is a special type of MMU in the sun3x architecture
     46  * (and supposedly in the sun4m as well) that translates an addresses
     47  * access by a DMA device during a DMA access, into a physical destination
     48  * address; it is an MMU that stands between DMA devices and physical memory.
     49  *
     50  * The input address space managed by the I/O mapper is 24 bits wide and broken
     51  * into pages of 8K-byte size.  The output address space is a full 32 bits
     52  * wide.  The mapping of each input page is described by a page entry
     53  * descriptor.  There are exactly 2048 such descriptors in the I/O mapper, the
     54  * first entry of which is located at physical address 0x60000000 in sun3x
     55  * machines.
     56  *
     57  * Since not every device transfers to a full 24 bit address space, each
     58  * device is wired so that its address space is always flush against the
     59  * high end of the I/O mapper.  That is, a device with a 16 bit address space
     60  * can only access 64k of memory.  This 64k is wired to the top 64k in the
     61  * I/O mapper's input address space.
     62  *
     63  * In addition to describing address mappings, a page entry also indicates
     64  * whether the page is read-only, inhibits system caches from caching data
     65  * addresses to or from it, and whether or not DMA transfers must be completed
     66  * in 16 byte blocks.  (This is used for cache optimization in sun3x systems
     67  * with special DMA caches.)
     68  */
     69 
     70 /** I/O MAPPER Page Entry Descriptor
     71  *  31                                                             16
     72  *  +---.---.---.---.---.---.---.---.---.---.---.---.---.---.---.---+
     73  *  |              PAGE PHYSICAL ADDRESS BITS (31..13)              |
     74  *  +---.---.---+---.---.---.---.---.---+---+---+---+---+---+---.---+
     75  *  |           |          UNUSED       | CI| BX| M | U | WP|   DT  |
     76  *  +---.---.---+---.---.---.---.---.---+---+---+---+---+---+---.---+
     77  *  15                                                              0
     78  *
     79  * <CI> CACHE INHIBIT   - When set, prevents instructions and data from the
     80  *                        page from being cached in any system cache.
     81  * <BX> FULL BLOCK XFER - When set, requires that all devices must transfer
     82  *                        data in multiples of 16 bytes in size.
     83  * <M>  MODIFIED        - Set when the cpu has modified (written to) the
     84  *                        physical page.
     85  * <U>  USED            - Set when the cpu has accessed the physical page.
     86  * <WP> WRITE PROTECT   - When set, prevents all DMA devices from writing to
     87  *                        the page.
     88  * <DT> DESCRIPTOR TYPE - One of the following values:
     89  *                        00 = Invalid page
     90  *                        01 = Valid page
     91  *                        1x = Invalid code for a page descriptor.
     92  */
     93 struct iommu_pde_struct {
     94 	union {
     95 		struct {
     96 			u_int	pa:19;		/* Physical Address  */
     97 			u_int	unused:6;	/* Unused bits       */
     98 			u_int	ci:1;		/* Cache Inhibit     */
     99 			u_int	bx:1;		/* Full Block Xfer   */
    100 			u_int	m:1;		/* Modified bit      */
    101 			u_int	u:1;		/* Used bit          */
    102 			u_int	wp:1;		/* Write Protect bit */
    103 			u_int	dt:2;		/* Descriptor type   */
    104 			/* Masks for the above fields. */
    105 #define	IOMMU_PDE_PA		0xFFFFE000
    106 #define	IOMMU_PDE_UNUSED	0x00001F80
    107 #define	IOMMU_PDE_CI		0x00000040
    108 #define	IOMMU_PDE_BX		0x00000020
    109 #define	IOMMU_PDE_M		0x00000010
    110 #define	IOMMU_PDE_USED		0x00000008
    111 #define	IOMMU_PDE_WP		0x00000004
    112 #define IOMMU_PDE_DT		0x00000003
    113 			/* The descriptor types */
    114 #define	IOMMU_PDE_DT_INVALID	0x00000000	/* Invalid page      */
    115 #define	IOMMU_PDE_DT_VALID	0x00000001	/* Valid page        */
    116 		} stc;
    117 		u_int32_t	raw;	/* For unstructured access to the above */
    118 	} addr;
    119 };
    120 typedef struct iommu_pde_struct iommu_pde_t;
    121 
    122 /* Constants */
    123 #define	IOMMU_PAGE_SHIFT	13
    124 
    125 /* Useful macros */
    126 #define	IOMMU_PA_PDE(pde)	((pde).addr.raw & IOMMU_PDE_PA)
    127 #define	IOMMU_VALID_DT(pde)	((pde).addr.raw & IOMMU_PDE_DT)	/* X1 */
    128 #define IOMMU_BTOP(pa)		(((u_int) pa) >> IOMMU_PAGE_SHIFT)
    129 
    130 /* X1: This macro will incorrectly report the validity for entries which
    131  * contain codes that are invalid.  (Do not confuse this with the code for
    132  * 'invalid entry', which means that the descriptor is properly formed, but
    133  * just not used.)
    134  */
    135 
    136 /* Constants for the I/O mapper as used in the sun3x */
    137 #define	IOMMU_NENT	2048	/* Number of entries in the map */
    138 
    139 #ifdef _KERNEL
    140 /* Interfaces for manipulating the I/O mapper */
    141 void iommu_enter __P((u_int32_t va, u_int32_t pa));
    142 void iommu_remove __P((u_int32_t va, u_int32_t len));
    143 #endif /* _KERNEL */
    144 
    145 #endif	/* _SUN3X_IOMMU_H */
    146