iommu.h revision 1.6
1 /* $NetBSD: iommu.h,v 1.6 2005/01/22 15:36:10 chs Exp $ */ 2 3 /*- 4 * Copyright (c) 1996 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jeremy Cooper. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 /* 40 * Structure and definition of descriptors used in the I/O Mapper. 41 */ 42 #ifndef _SUN3X_IOMMU_H 43 #define _SUN3X_IOMMU_H 44 45 /* The I/O Mapper is a special type of MMU in the sun3x architecture 46 * (and supposedly in the sun4m as well) that translates an address used by a 47 * device during a DMA transfer into an address on the internal system bus. 48 * In other words, it is an MMU that stands between devices wishing to do DMA 49 * transfers and main memory. In this description, the address issued by a 50 * DMA device is called a ``DVMA address'', while the address as it is 51 * translated and output from the I/O mapper is called a ``system bus address'' 52 * (sometimes known as a ``physical address''). 53 * 54 * The DVMA address space in the sun3x architecture is 24 bits wide, in 55 * contrast with the system bus address space, which is 32. The mapping of a 56 * DVMA address to a system bus address is accomplished by dividing the DVMA 57 * address space into 2048 8K pages. Each DVMA page is then mapped to a 58 * system bus address using a mapping described by a page descriptor entry 59 * within the I/O Mapper. This 2048 entry, page descriptor table is located 60 * at physical address 0x60000000 in the sun3x architecture and can be 61 * manipulated by the CPU with normal read and write cycles. 62 * 63 * In addition to describing an address mapping, a page descriptor entry also 64 * indicates whether the DVMA page is read-only, should be inhibited from 65 * caching by system caches, and whether or not DMA write transfers to it will 66 * be completed in 16 byte aligned blocks. (This last item is used for cache 67 * optimization in sun3x systems with special DMA caches.) 68 * 69 * Since not every DMA device is capable of addressing all 24 bits of the 70 * DVMA address space, each is wired so that the end of its address space is 71 * always flush against the end of the DVMA address space. That is, a device 72 * with a 16 bit address space (and hence an address space size of 64k) is 73 * wired such that it accesses the top 64k of DVMA space. 74 */ 75 76 /** I/O MAPPER Page Descriptor Entry 77 * 31 16 78 * +---.---.---.---.---.---.---.---.---.---.---.---.---.---.---.---+ 79 * | PAGE PHYSICAL ADDRESS BITS (31..13) | 80 * +---.---.---+---.---.---.---.---.---+---+---+---+---+---+---.---+ 81 * | | UNUSED | CI| BX| M | U | WP| DT | 82 * +---.---.---+---.---.---.---.---.---+---+---+---+---+---+---.---+ 83 * 15 0 84 * 85 * <CI> CACHE INHIBIT - When set, prevents instructions and data from the 86 * page from being cached in any system cache. 87 * <BX> FULL BLOCK XFER - When set, acts as an indicator to the caching system 88 * that all DMA transfers to this DVMA page will fill 89 * complete I/O cache blocks, eliminating the need for 90 * the cache block to be filled from main memory first 91 * before the DMA write can proceed to it. 92 * <M> MODIFIED - Set when the cpu has modified (written to) the 93 * physical page. 94 * <U> USED - Set when the cpu has accessed the physical page. 95 * <WP> WRITE PROTECT - When set, prevents all DMA devices from writing to 96 * the page. 97 * <DT> DESCRIPTOR TYPE - One of the following values: 98 * 00 = Invalid page 99 * 01 = Valid page 100 * 1x = Invalid code for a page descriptor. 101 */ 102 struct iommu_pde_struct { 103 union { 104 struct { 105 u_int pa:19; /* Physical Address */ 106 u_int unused:6; /* Unused bits */ 107 u_int ci:1; /* Cache Inhibit */ 108 u_int bx:1; /* Full Block Xfer */ 109 u_int m:1; /* Modified bit */ 110 u_int u:1; /* Used bit */ 111 u_int wp:1; /* Write Protect bit */ 112 u_int dt:2; /* Descriptor type */ 113 /* Masks for the above fields. */ 114 #define IOMMU_PDE_PA 0xFFFFE000 115 #define IOMMU_PDE_UNUSED 0x00001F80 116 #define IOMMU_PDE_CI 0x00000040 117 #define IOMMU_PDE_BX 0x00000020 118 #define IOMMU_PDE_M 0x00000010 119 #define IOMMU_PDE_USED 0x00000008 120 #define IOMMU_PDE_WP 0x00000004 121 #define IOMMU_PDE_DT 0x00000003 122 /* The descriptor types */ 123 #define IOMMU_PDE_DT_INVALID 0x00000000 /* Invalid page */ 124 #define IOMMU_PDE_DT_VALID 0x00000001 /* Valid page */ 125 } stc; 126 uint32_t raw; /* For unstructured access to the above */ 127 } addr; 128 }; 129 typedef struct iommu_pde_struct iommu_pde_t; 130 131 /* Constants */ 132 #define IOMMU_PAGE_SIZE (8 * 1024) 133 #define IOMMU_PAGE_SHIFT 13 134 135 /* Useful macros */ 136 #define IOMMU_PA_PDE(pde) ((pde).addr.raw & IOMMU_PDE_PA) 137 #define IOMMU_VALID_DT(pde) ((pde).addr.raw & IOMMU_PDE_DT) /* X1 */ 138 #define IOMMU_BTOP(pa) (((u_int) pa) >> IOMMU_PAGE_SHIFT) 139 140 /* X1: This macro will incorrectly report the validity for entries which 141 * contain codes that are invalid. (Do not confuse this with the code for 142 * 'invalid entry', which means that the descriptor is properly formed, but 143 * just not used.) 144 */ 145 146 /* Constants for the I/O mapper as used in the sun3x */ 147 #define IOMMU_NENT 2048 /* Number of PTEs in the map */ 148 /* Similarly, the virtual address mask. */ 149 #define IOMMU_VA_MASK 0xFFffff /* 16MB */ 150 151 #ifdef _KERNEL 152 /* Interfaces for manipulating the I/O mapper */ 153 void iommu_enter(uint32_t, uint32_t); 154 void iommu_remove(uint32_t, uint32_t); 155 #endif /* _KERNEL */ 156 157 #endif /* _SUN3X_IOMMU_H */ 158
Indexes created Fri Sep 26 08:10:20 GMT 2025