locore.s revision 1.16
1 /* $NetBSD: locore.s,v 1.16 1997/04/13 02:37:27 thorpej Exp $ */ 2 3 /* 4 * Copyright (c) 1988 University of Utah. 5 * Copyright (c) 1980, 1990, 1993 6 * The Regents of the University of California. All rights reserved. 7 * 8 * This code is derived from software contributed to Berkeley by 9 * the Systems Programming Group of the University of Utah Computer 10 * Science Department. 11 * 12 * Redistribution and use in source and binary forms, with or without 13 * modification, are permitted provided that the following conditions 14 * are met: 15 * 1. Redistributions of source code must retain the above copyright 16 * notice, this list of conditions and the following disclaimer. 17 * 2. Redistributions in binary form must reproduce the above copyright 18 * notice, this list of conditions and the following disclaimer in the 19 * documentation and/or other materials provided with the distribution. 20 * 3. All advertising materials mentioning features or use of this software 21 * must display the following acknowledgement: 22 * This product includes software developed by the University of 23 * California, Berkeley and its contributors. 24 * 4. Neither the name of the University nor the names of its contributors 25 * may be used to endorse or promote products derived from this software 26 * without specific prior written permission. 27 * 28 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 29 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 30 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 31 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 32 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 33 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 34 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 35 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 36 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 37 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 38 * SUCH DAMAGE. 39 * 40 * from: Utah $Hdr: locore.s 1.66 92/12/22$ 41 * @(#)locore.s 8.6 (Berkeley) 5/27/94 42 */ 43 44 #include "assym.h" 45 #include <machine/trap.h> 46 47 | Remember this is a fun project! 48 49 .data 50 .globl _mon_crp 51 _mon_crp: 52 .long 0,0 53 54 | This is for kvm_mkdb, and should be the address of the beginning 55 | of the kernel text segment (not necessarily the same as kernbase). 56 .text 57 .globl _kernel_text 58 _kernel_text: 59 60 | This is the entry point, as well as the end of the temporary stack 61 | used during process switch (one 8K page ending at start) 62 .globl tmpstk 63 tmpstk: 64 .globl start 65 start: 66 | The first step, after disabling interrupts, is to map enough of the kernel 67 | into high virtual address space so that we can use position dependent code. 68 | This is a tricky task on the sun3x because the MMU is already enabled and 69 | the ROM monitor provides no indication of where the root MMU table is mapped. 70 | Therefore we must use one of the 68030's 'transparent translation' registers 71 | to define a range in the address space where the MMU translation is 72 | turned off. Once this is complete we can modify the MMU table directly 73 | without the need for it to be mapped into virtual memory. 74 | All code must be position independent until otherwise noted, as the 75 | boot loader has loaded us into low memory but all the symbols in this 76 | code have been linked high. 77 movw #PSL_HIGHIPL, sr | no interrupts 78 movl #KERNBASE, a5 | for vtop conversion 79 lea _mon_crp, a0 | where to store the CRP 80 subl a5, a0 81 | Note: borrowing mon_crp for tt0 setup... 82 movl #0x3F8107, a0@ | map the low 1GB v=p with the 83 .long 0xf0100800 | transparent translation reg0 84 | [ pmove a0@, tt0 ] 85 | In order to map the kernel into high memory we will copy the root table 86 | entry which maps the 16 megabytes of memory starting at 0x0 into the 87 | entry which maps the 16 megabytes starting at KERNBASE. 88 pmove crp, a0@ | Get monitor CPU root pointer 89 movl a0@(4), a1 | 2nd word is PA of level A table 90 91 movl a1, a0 | compute the descriptor address 92 addl #0x3e0, a1 | for VA starting at KERNBASE 93 movl a0@, a1@ | copy descriptor type 94 movl a0@(4), a1@(4) | copy physical address 95 96 | Kernel is now double mapped at zero and KERNBASE. 97 | Force a long jump to the relocated code (high VA). 98 movl #IC_CLEAR, d0 | Flush the I-cache 99 movc d0, cacr 100 jmp L_high_code:l | long jump 101 102 L_high_code: 103 | We are now running in the correctly relocated kernel, so 104 | we are no longer restricted to position-independent code. 105 | It is handy to leave transparent translation enabled while 106 | for the low 1GB while __bootstrap() is doing its thing. 107 108 | Do bootstrap stuff needed before main() gets called. 109 | Our boot loader leaves a copy of the kernel's exec header 110 | just before the start of the kernel text segment, so the 111 | kernel can sanity-check the DDB symbols at [end...esym]. 112 | Pass the struct exec at tmpstk-32 to __bootstrap(). 113 | Also, make sure the initial frame pointer is zero so that 114 | the backtrace algorithm used by KGDB terminates nicely. 115 lea tmpstk-32, sp 116 movl #0,a6 117 jsr __bootstrap | See _startup.c 118 119 | Now turn off the transparent translation of the low 1GB. 120 | (this also flushes the ATC) 121 clrl sp@- 122 .long 0xf0170800 | pmove sp@,tt0 123 addql #4,sp 124 125 | Now that __bootstrap() is done using the PROM functions, 126 | we can safely set the sfc/dfc to something != FC_CONTROL 127 moveq #FC_USERD, d0 | make movs access "user data" 128 movc d0, sfc | space for copyin/copyout 129 movc d0, dfc 130 131 | Setup process zero user/kernel stacks. 132 movl _proc0paddr,a1 | get proc0 pcb addr 133 lea a1@(USPACE-4),sp | set SSP to last word 134 movl #USRSTACK-4,a2 135 movl a2,usp | init user SP 136 137 | Note curpcb was already set in __bootstrap(). 138 | Will do fpu initialization during autoconfig (see fpu.c) 139 | The interrupt vector table and stack are now ready. 140 | Interrupts will be enabled later, AFTER autoconfiguration 141 | is finished, to avoid spurrious interrupts. 142 143 /* 144 * Final preparation for calling main. 145 * 146 * Create a fake exception frame that returns to user mode, 147 * and save its address in p->p_md.md_regs for cpu_fork(). 148 * The new frames for process 1 and 2 will be adjusted by 149 * cpu_set_kpc() to arrange for a call to a kernel function 150 * before the new process does its rte out to user mode. 151 */ 152 clrw sp@- | tf_format,tf_vector 153 clrl sp@- | tf_pc (filled in later) 154 movw #PSL_USER,sp@- | tf_sr for user mode 155 clrl sp@- | tf_stackadj 156 lea sp@(-64),sp | tf_regs[16] 157 movl sp,a1 | a1=trapframe 158 lea _proc0,a0 | proc0.p_md.md_regs = 159 movl a1,a0@(P_MDREGS) | trapframe 160 movl a2,a1@(FR_SP) | a2 == usp (from above) 161 pea a1@ | push &trapframe 162 jbsr _main | main(&trapframe) 163 addql #4,sp | help DDB backtrace 164 trap #15 | should not get here 165 166 | This is used by cpu_fork() to return to user mode. 167 | It is called with SP pointing to a struct trapframe. 168 .globl _proc_do_uret 169 _proc_do_uret: 170 movl sp@(FR_SP),a0 | grab and load 171 movl a0,usp | user SP 172 moveml sp@+,#0x7FFF | load most registers (all but SSP) 173 addql #8,sp | pop SSP and stack adjust count 174 rte 175 176 /* 177 * proc_trampoline: 178 * This is used by cpu_set_kpc() to "push" a function call onto the 179 * kernel stack of some process, very much like a signal delivery. 180 * When we get here, the stack has: 181 * 182 * SP+8: switchframe from before cpu_set_kpc 183 * SP+4: void *proc; 184 * SP: u_long func; 185 * 186 * On entry, the switchframe pushed by cpu_set_kpc has already been 187 * popped off the stack, so all this needs to do is pop the function 188 * pointer into a register, call it, then pop the arg, and finally 189 * return using the switchframe that remains on the stack. 190 */ 191 .globl _proc_trampoline 192 _proc_trampoline: 193 movl sp@+,a0 | function pointer 194 jbsr a0@ | (*func)(procp) 195 addql #4,sp | toss the arg 196 rts | as cpu_switch would do 197 198 | That is all the assembly startup code we need on the sun3x! 199 | The rest of this is like the hp300/locore.s where possible. 200 201 /* 202 * Trap/interrupt vector routines 203 */ 204 205 .globl _buserr, _addrerr, _illinst, _zerodiv, _chkinst 206 .globl _trapvinst, _privinst, _trace, _badtrap, _fmterr 207 .globl _trap0, _trap1, _trap2, _trap12, _trap15 208 .globl _coperr, _fpfline, _fpunsupp 209 210 .globl _trap, _nofault, _longjmp 211 _buserr: 212 tstl _nofault | device probe? 213 jeq _addrerr | no, handle as usual 214 movl _nofault,sp@- | yes, 215 jbsr _longjmp | longjmp(nofault) 216 _addrerr: 217 clrl sp@- | stack adjust count 218 moveml #0xFFFF,sp@- | save user registers 219 movl usp,a0 | save the user SP 220 movl a0,sp@(FR_SP) | in the savearea 221 lea sp@(FR_HW),a1 | grab base of HW berr frame 222 moveq #0,d0 223 movw a1@(10),d0 | grab SSW for fault processing 224 btst #12,d0 | RB set? 225 jeq LbeX0 | no, test RC 226 bset #14,d0 | yes, must set FB 227 movw d0,a1@(10) | for hardware too 228 LbeX0: 229 btst #13,d0 | RC set? 230 jeq LbeX1 | no, skip 231 bset #15,d0 | yes, must set FC 232 movw d0,a1@(10) | for hardware too 233 LbeX1: 234 btst #8,d0 | data fault? 235 jeq Lbe0 | no, check for hard cases 236 movl a1@(16),d1 | fault address is as given in frame 237 jra Lbe10 | thats it 238 Lbe0: 239 btst #4,a1@(6) | long (type B) stack frame? 240 jne Lbe4 | yes, go handle 241 movl a1@(2),d1 | no, can use save PC 242 btst #14,d0 | FB set? 243 jeq Lbe3 | no, try FC 244 addql #4,d1 | yes, adjust address 245 jra Lbe10 | done 246 Lbe3: 247 btst #15,d0 | FC set? 248 jeq Lbe10 | no, done 249 addql #2,d1 | yes, adjust address 250 jra Lbe10 | done 251 Lbe4: 252 movl a1@(36),d1 | long format, use stage B address 253 btst #15,d0 | FC set? 254 jeq Lbe10 | no, all done 255 subql #2,d1 | yes, adjust address 256 Lbe10: 257 movl d1,sp@- | push fault VA 258 movl d0,sp@- | and padded SSW 259 movw a1@(6),d0 | get frame format/vector offset 260 andw #0x0FFF,d0 | clear out frame format 261 cmpw #12,d0 | address error vector? 262 jeq Lisaerr | yes, go to it 263 264 /* MMU-specific code to determine reason for bus error. */ 265 movl d1,a0 | fault address 266 movl sp@,d0 | function code from ssw 267 btst #8,d0 | data fault? 268 jne Lbe10a 269 movql #1,d0 | user program access FC 270 | (we dont separate data/program) 271 btst #5,a1@ | supervisor mode? 272 jeq Lbe10a | if no, done 273 movql #5,d0 | else supervisor program access 274 Lbe10a: 275 ptestr d0,a0@,#7 | do a table search 276 pmove psr,sp@ | save result 277 movb sp@,d1 278 btst #2,d1 | invalid? (incl. limit viol and berr) 279 jeq Lmightnotbemerr | no -> wp check 280 btst #7,d1 | is it MMU table berr? 281 jeq Lismerr | no, must be fast 282 jra Lisberr1 | real bus err needs not be fast 283 Lmightnotbemerr: 284 btst #3,d1 | write protect bit set? 285 jeq Lisberr1 | no, must be bus error 286 movl sp@,d0 | ssw into low word of d0 287 andw #0xc0,d0 | write protect is set on page: 288 cmpw #0x40,d0 | was it read cycle? 289 jeq Lisberr1 | yes, was not WPE, must be bus err 290 /* End of MMU-specific bus error code. */ 291 292 Lismerr: 293 movl #T_MMUFLT,sp@- | show that we are an MMU fault 294 jra Ltrapnstkadj | and deal with it 295 Lisaerr: 296 movl #T_ADDRERR,sp@- | mark address error 297 jra Ltrapnstkadj | and deal with it 298 Lisberr1: 299 clrw sp@ | re-clear pad word 300 Lisberr: 301 movl #T_BUSERR,sp@- | mark bus error 302 Ltrapnstkadj: 303 jbsr _trap | handle the error 304 lea sp@(12),sp | pop value args 305 movl sp@(FR_SP),a0 | restore user SP 306 movl a0,usp | from save area 307 movw sp@(FR_ADJ),d0 | need to adjust stack? 308 jne Lstkadj | yes, go to it 309 moveml sp@+,#0x7FFF | no, restore most user regs 310 addql #8,sp | toss SSP and stkadj 311 jra rei | all done 312 Lstkadj: 313 lea sp@(FR_HW),a1 | pointer to HW frame 314 addql #8,a1 | source pointer 315 movl a1,a0 | source 316 addw d0,a0 | + hole size = dest pointer 317 movl a1@-,a0@- | copy 318 movl a1@-,a0@- | 8 bytes 319 movl a0,sp@(FR_SP) | new SSP 320 moveml sp@+,#0x7FFF | restore user registers 321 movl sp@,sp | and our SP 322 jra rei | all done 323 324 /* 325 * FP exceptions. 326 */ 327 _fpfline: 328 clrl sp@- | stack adjust count 329 moveml #0xFFFF,sp@- | save registers 330 moveq #T_FPEMULI,d0 | denote as FP emulation trap 331 jra fault | do it 332 333 _fpunsupp: 334 clrl sp@- | stack adjust count 335 moveml #0xFFFF,sp@- | save registers 336 moveq #T_FPEMULD,d0 | denote as FP emulation trap 337 jra fault | do it 338 339 /* 340 * Handles all other FP coprocessor exceptions. 341 * Note that since some FP exceptions generate mid-instruction frames 342 * and may cause signal delivery, we need to test for stack adjustment 343 * after the trap call. 344 */ 345 .globl _fpfault 346 _fpfault: 347 clrl sp@- | stack adjust count 348 moveml #0xFFFF,sp@- | save user registers 349 movl usp,a0 | and save 350 movl a0,sp@(FR_SP) | the user stack pointer 351 clrl sp@- | no VA arg 352 movl _curpcb,a0 | current pcb 353 lea a0@(PCB_FPCTX),a0 | address of FP savearea 354 fsave a0@ | save state 355 tstb a0@ | null state frame? 356 jeq Lfptnull | yes, safe 357 clrw d0 | no, need to tweak BIU 358 movb a0@(1),d0 | get frame size 359 bset #3,a0@(0,d0:w) | set exc_pend bit of BIU 360 Lfptnull: 361 fmovem fpsr,sp@- | push fpsr as code argument 362 frestore a0@ | restore state 363 movl #T_FPERR,sp@- | push type arg 364 jra Ltrapnstkadj | call trap and deal with stack cleanup 365 366 /* 367 * Coprocessor and format errors can generate mid-instruction stack 368 * frames and cause signal delivery hence we need to check for potential 369 * stack adjustment. 370 */ 371 _coperr: 372 clrl sp@- | stack adjust count 373 moveml #0xFFFF,sp@- 374 movl usp,a0 | get and save 375 movl a0,sp@(FR_SP) | the user stack pointer 376 clrl sp@- | no VA arg 377 clrl sp@- | or code arg 378 movl #T_COPERR,sp@- | push trap type 379 jra Ltrapnstkadj | call trap and deal with stack adjustments 380 381 _fmterr: 382 clrl sp@- | stack adjust count 383 moveml #0xFFFF,sp@- 384 movl usp,a0 | get and save 385 movl a0,sp@(FR_SP) | the user stack pointer 386 clrl sp@- | no VA arg 387 clrl sp@- | or code arg 388 movl #T_FMTERR,sp@- | push trap type 389 jra Ltrapnstkadj | call trap and deal with stack adjustments 390 391 /* 392 * Other exceptions only cause four and six word stack frame and require 393 * no post-trap stack adjustment. 394 */ 395 _illinst: 396 clrl sp@- 397 moveml #0xFFFF,sp@- 398 moveq #T_ILLINST,d0 399 jra fault 400 401 _zerodiv: 402 clrl sp@- 403 moveml #0xFFFF,sp@- 404 moveq #T_ZERODIV,d0 405 jra fault 406 407 _chkinst: 408 clrl sp@- 409 moveml #0xFFFF,sp@- 410 moveq #T_CHKINST,d0 411 jra fault 412 413 _trapvinst: 414 clrl sp@- 415 moveml #0xFFFF,sp@- 416 moveq #T_TRAPVINST,d0 417 jra fault 418 419 _privinst: 420 clrl sp@- 421 moveml #0xFFFF,sp@- 422 moveq #T_PRIVINST,d0 423 jra fault 424 425 .globl fault 426 fault: 427 movl usp,a0 | get and save 428 movl a0,sp@(FR_SP) | the user stack pointer 429 clrl sp@- | no VA arg 430 clrl sp@- | or code arg 431 movl d0,sp@- | push trap type 432 jbsr _trap | handle trap 433 lea sp@(12),sp | pop value args 434 movl sp@(FR_SP),a0 | restore 435 movl a0,usp | user SP 436 moveml sp@+,#0x7FFF | restore most user regs 437 addql #8,sp | pop SP and stack adjust 438 jra rei | all done 439 440 .globl _straytrap 441 _badtrap: 442 clrl sp@- | stack adjust count 443 moveml #0xFFFF,sp@- | save std frame regs 444 jbsr _straytrap | report 445 moveml sp@+,#0xFFFF | restore regs 446 addql #4, sp | stack adjust count 447 jra rei | all done 448 449 /* 450 * Trap 0 is for system calls 451 */ 452 .globl _syscall 453 _trap0: 454 clrl sp@- | stack adjust count 455 moveml #0xFFFF,sp@- | save user registers 456 movl usp,a0 | save the user SP 457 movl a0,sp@(FR_SP) | in the savearea 458 movl d0,sp@- | push syscall number 459 jbsr _syscall | handle it 460 addql #4,sp | pop syscall arg 461 movl sp@(FR_SP),a0 | grab and restore 462 movl a0,usp | user SP 463 moveml sp@+,#0x7FFF | restore most registers 464 addql #8,sp | pop SP and stack adjust 465 jra rei | all done 466 467 /* 468 * Trap 1 action depends on the emulation type: 469 * NetBSD: sigreturn "syscall" 470 * HPUX: user breakpoint 471 */ 472 _trap1: 473 #if 0 /* COMPAT_HPUX */ 474 /* If process is HPUX, this is a user breakpoint. */ 475 jne _trap15 | HPUX user breakpoint 476 #endif 477 jra sigreturn | NetBSD 478 479 /* 480 * Trap 2 action depends on the emulation type: 481 * NetBSD: user breakpoint -- See XXX below... 482 * SunOS: cache flush 483 * HPUX: sigreturn 484 */ 485 _trap2: 486 #if 0 /* COMPAT_HPUX */ 487 /* If process is HPUX, this is a sigreturn call */ 488 jne sigreturn 489 #endif 490 jra _trap15 | NetBSD user breakpoint 491 | XXX - Make NetBSD use trap 15 for breakpoints? 492 | XXX - That way, we can allow this cache flush... 493 | XXX SunOS trap #2 (and NetBSD?) 494 | Flush on-chip cache (leave it enabled) 495 | movl #CACHE_CLR,d0 496 | movc d0,cacr 497 | rte 498 499 /* 500 * Trap 12 is the entry point for the cachectl "syscall" 501 * cachectl(command, addr, length) 502 * command in d0, addr in a1, length in d1 503 */ 504 .globl _cachectl 505 _trap12: 506 movl d1,sp@- | push length 507 movl a1,sp@- | push addr 508 movl d0,sp@- | push command 509 jbsr _cachectl | do it 510 lea sp@(12),sp | pop args 511 jra rei | all done 512 513 /* 514 * Trace (single-step) trap. Kernel-mode is special. 515 * User mode traps are simply passed on to trap(). 516 */ 517 _trace: 518 clrl sp@- | stack adjust count 519 moveml #0xFFFF,sp@- 520 moveq #T_TRACE,d0 521 btst #5,sp@(FR_HW) | was supervisor mode? 522 jne kbrkpt | yes, kernel brkpt 523 jra fault | no, user-mode fault 524 525 /* 526 * Trap 15 is used for: 527 * - GDB breakpoints (in user programs) 528 * - KGDB breakpoints (in the kernel) 529 * - trace traps for SUN binaries (not fully supported yet) 530 * User mode traps are simply passed to trap(). 531 */ 532 _trap15: 533 clrl sp@- | stack adjust count 534 moveml #0xFFFF,sp@- 535 moveq #T_TRAP15,d0 536 btst #5,sp@(FR_HW) | was supervisor mode? 537 jne kbrkpt | yes, kernel brkpt 538 jra fault | no, user-mode fault 539 540 kbrkpt: 541 | Kernel-mode breakpoint or trace trap. (d0=trap_type) 542 | Save the system sp rather than the user sp. 543 movw #PSL_HIGHIPL,sr | lock out interrupts 544 lea sp@(FR_SIZE),a6 | Save stack pointer 545 movl a6,sp@(FR_SP) | from before trap 546 547 | If we are not on tmpstk switch to it. 548 | (so debugger can change the stack pointer) 549 movl a6,d1 550 cmpl #tmpstk,d1 551 jls Lbrkpt2 | already on tmpstk 552 | Copy frame to the temporary stack 553 movl sp,a0 | a0=src 554 lea tmpstk-96,a1 | a1=dst 555 movl a1,sp | sp=new frame 556 moveq #FR_SIZE,d1 557 Lbrkpt1: 558 movl a0@+,a1@+ 559 subql #4,d1 560 bgt Lbrkpt1 561 562 Lbrkpt2: 563 | Call the trap handler for the kernel debugger. 564 | Do not call trap() to handle it, so that we can 565 | set breakpoints in trap() if we want. We know 566 | the trap type is either T_TRACE or T_BREAKPOINT. 567 movl d0,sp@- | push trap type 568 jbsr _trap_kdebug 569 addql #4,sp | pop args 570 571 | The stack pointer may have been modified, or 572 | data below it modified (by kgdb push call), 573 | so push the hardware frame at the current sp 574 | before restoring registers and returning. 575 movl sp@(FR_SP),a0 | modified sp 576 lea sp@(FR_SIZE),a1 | end of our frame 577 movl a1@-,a0@- | copy 2 longs with 578 movl a1@-,a0@- | ... predecrement 579 movl a0,sp@(FR_SP) | sp = h/w frame 580 moveml sp@+,#0x7FFF | restore all but sp 581 movl sp@,sp | ... and sp 582 rte | all done 583 584 /* Use common m68k sigreturn */ 585 #include <m68k/m68k/sigreturn.s> 586 587 /* 588 * Interrupt handlers. Most are auto-vectored, 589 * and hard-wired the same way on all sun3 models. 590 * Format in the stack is: 591 * d0,d1,a0,a1, sr, pc, vo 592 */ 593 594 #define INTERRUPT_SAVEREG \ 595 moveml #0xC0C0,sp@- 596 597 #define INTERRUPT_RESTORE \ 598 moveml sp@+,#0x0303 599 600 /* 601 * This is the common auto-vector interrupt handler, 602 * for which the CPU provides the vector=0x18+level. 603 * These are installed in the interrupt vector table. 604 */ 605 .align 2 606 .globl __isr_autovec, _isr_autovec 607 __isr_autovec: 608 INTERRUPT_SAVEREG 609 jbsr _isr_autovec 610 INTERRUPT_RESTORE 611 jra rei 612 613 /* clock: see clock.c */ 614 .align 2 615 .globl __isr_clock, _clock_intr 616 __isr_clock: 617 INTERRUPT_SAVEREG 618 jbsr _clock_intr 619 INTERRUPT_RESTORE 620 jra rei 621 622 | Handler for all vectored interrupts (i.e. VME interrupts) 623 .align 2 624 .globl __isr_vectored, _isr_vectored 625 __isr_vectored: 626 INTERRUPT_SAVEREG 627 jbsr _isr_vectored 628 INTERRUPT_RESTORE 629 jra rei 630 631 #undef INTERRUPT_SAVEREG 632 #undef INTERRUPT_RESTORE 633 634 /* interrupt counters (needed by vmstat) */ 635 .globl _intrcnt,_eintrcnt,_intrnames,_eintrnames 636 _intrnames: 637 .asciz "spur" | 0 638 .asciz "lev1" | 1 639 .asciz "lev2" | 2 640 .asciz "lev3" | 3 641 .asciz "lev4" | 4 642 .asciz "clock" | 5 643 .asciz "lev6" | 6 644 .asciz "nmi" | 7 645 _eintrnames: 646 647 .data 648 .even 649 _intrcnt: 650 .long 0,0,0,0,0,0,0,0,0,0 651 _eintrcnt: 652 .text 653 654 /* 655 * Emulation of VAX REI instruction. 656 * 657 * This code is (mostly) un-altered from the hp300 code, 658 * except that sun machines do not need a simulated SIR 659 * because they have a real software interrupt register. 660 * 661 * This code deals with checking for and servicing ASTs 662 * (profiling, scheduling) and software interrupts (network, softclock). 663 * We check for ASTs first, just like the VAX. To avoid excess overhead 664 * the T_ASTFLT handling code will also check for software interrupts so we 665 * do not have to do it here. After identifying that we need an AST we 666 * drop the IPL to allow device interrupts. 667 * 668 * This code is complicated by the fact that sendsig may have been called 669 * necessitating a stack cleanup. 670 */ 671 672 .globl _astpending 673 .globl rei 674 rei: 675 #ifdef DIAGNOSTIC 676 tstl _panicstr | have we paniced? 677 jne Ldorte | yes, do not make matters worse 678 #endif 679 tstl _astpending | AST pending? 680 jeq Ldorte | no, done 681 Lrei1: 682 btst #5,sp@ | yes, are we returning to user mode? 683 jne Ldorte | no, done 684 movw #PSL_LOWIPL,sr | lower SPL 685 clrl sp@- | stack adjust 686 moveml #0xFFFF,sp@- | save all registers 687 movl usp,a1 | including 688 movl a1,sp@(FR_SP) | the users SP 689 clrl sp@- | VA == none 690 clrl sp@- | code == none 691 movl #T_ASTFLT,sp@- | type == async system trap 692 jbsr _trap | go handle it 693 lea sp@(12),sp | pop value args 694 movl sp@(FR_SP),a0 | restore user SP 695 movl a0,usp | from save area 696 movw sp@(FR_ADJ),d0 | need to adjust stack? 697 jne Laststkadj | yes, go to it 698 moveml sp@+,#0x7FFF | no, restore most user regs 699 addql #8,sp | toss SP and stack adjust 700 rte | and do real RTE 701 Laststkadj: 702 lea sp@(FR_HW),a1 | pointer to HW frame 703 addql #8,a1 | source pointer 704 movl a1,a0 | source 705 addw d0,a0 | + hole size = dest pointer 706 movl a1@-,a0@- | copy 707 movl a1@-,a0@- | 8 bytes 708 movl a0,sp@(FR_SP) | new SSP 709 moveml sp@+,#0x7FFF | restore user registers 710 movl sp@,sp | and our SP 711 Ldorte: 712 rte | real return 713 714 /* 715 * Initialization is at the beginning of this file, because the 716 * kernel entry point needs to be at zero for compatibility with 717 * the Sun boot loader. This works on Sun machines because the 718 * interrupt vector table for reset is NOT at address zero. 719 * (The MMU has a "boot" bit that forces access to the PROM) 720 */ 721 722 /* 723 * Use common m68k sigcode. 724 */ 725 #include <m68k/m68k/sigcode.s> 726 727 .text 728 729 /* 730 * Primitives 731 */ 732 #include <machine/asm.h> 733 734 /* 735 * Use common m68k support routines. 736 */ 737 #include <m68k/m68k/support.s> 738 739 .globl _whichqs,_qs,_cnt,_panic 740 .globl _curproc 741 .comm _want_resched,4 742 743 /* 744 * Use common m68k process manipulation routines. 745 */ 746 #include <m68k/m68k/proc_subr.s> 747 748 | Message for Lbadsw panic 749 Lsw0: 750 .asciz "cpu_switch" 751 .even 752 753 .globl _curpcb 754 .globl _masterpaddr | XXX compatibility (debuggers) 755 .data 756 _masterpaddr: | XXX compatibility (debuggers) 757 _curpcb: 758 .long 0 759 .comm nullpcb,SIZEOF_PCB 760 .text 761 762 /* 763 * At exit of a process, do a cpu_switch for the last time. 764 * Switch to a safe stack and PCB, and deallocate the process's resources. 765 * The ipl is high enough to prevent the memory from being reallocated. 766 */ 767 ENTRY(switch_exit) 768 movl sp@(4),a0 | struct proc *p 769 movl #nullpcb,_curpcb | save state into garbage pcb 770 lea tmpstk,sp | goto a tmp stack 771 movl a0,sp@- | pass proc ptr down 772 773 /* Free old process's u-area. */ 774 movl #USPACE,sp@- | size of u-area 775 movl a0@(P_ADDR),sp@- | address of process's u-area 776 movl _kernel_map,sp@- | map it was allocated in 777 jbsr _kmem_free | deallocate it 778 lea sp@(12),sp | pop args 779 780 jra _cpu_switch 781 782 /* 783 * When no processes are on the runq, cpu_switch() branches to idle 784 * to wait for something to come ready. 785 */ 786 .data 787 .globl _Idle_count 788 _Idle_count: 789 .long 0 790 .text 791 792 .globl Idle 793 Lidle: 794 stop #PSL_LOWIPL 795 Idle: 796 movw #PSL_HIGHIPL,sr 797 addql #1, _Idle_count 798 tstl _whichqs 799 jeq Lidle 800 movw #PSL_LOWIPL,sr 801 jra Lsw1 802 803 Lbadsw: 804 movl #Lsw0,sp@- 805 jbsr _panic 806 /*NOTREACHED*/ 807 808 /* 809 * cpu_switch() 810 * Hacked for sun3 811 * XXX - Arg 1 is a proc pointer (curproc) but this doesn't use it. 812 * XXX - Sould we use p->p_addr instead of curpcb? -gwr 813 */ 814 ENTRY(cpu_switch) 815 movl _curpcb,a1 | current pcb 816 movw sr,a1@(PCB_PS) | save sr before changing ipl 817 #ifdef notyet 818 movl _curproc,sp@- | remember last proc running 819 #endif 820 clrl _curproc 821 822 Lsw1: 823 /* 824 * Find the highest-priority queue that isn't empty, 825 * then take the first proc from that queue. 826 */ 827 clrl d0 828 lea _whichqs,a0 829 movl a0@,d1 830 Lswchk: 831 btst d0,d1 832 jne Lswfnd 833 addqb #1,d0 834 cmpb #32,d0 835 jne Lswchk 836 jra Idle 837 Lswfnd: 838 movw #PSL_HIGHIPL,sr | lock out interrupts 839 movl a0@,d1 | and check again... 840 bclr d0,d1 841 jeq Lsw1 | proc moved, rescan 842 movl d1,a0@ | update whichqs 843 moveq #1,d1 | double check for higher priority 844 lsll d0,d1 | process (which may have snuck in 845 subql #1,d1 | while we were finding this one) 846 andl a0@,d1 847 jeq Lswok | no one got in, continue 848 movl a0@,d1 849 bset d0,d1 | otherwise put this one back 850 movl d1,a0@ 851 jra Lsw1 | and rescan 852 Lswok: 853 movl d0,d1 854 lslb #3,d1 | convert queue number to index 855 addl #_qs,d1 | locate queue (q) 856 movl d1,a1 857 cmpl a1@(P_FORW),a1 | anyone on queue? 858 jeq Lbadsw | no, panic 859 movl a1@(P_FORW),a0 | p = q->p_forw 860 movl a0@(P_FORW),a1@(P_FORW) | q->p_forw = p->p_forw 861 movl a0@(P_FORW),a1 | q = p->p_forw 862 movl a0@(P_BACK),a1@(P_BACK) | q->p_back = p->p_back 863 cmpl a0@(P_FORW),d1 | anyone left on queue? 864 jeq Lsw2 | no, skip 865 movl _whichqs,d1 866 bset d0,d1 | yes, reset bit 867 movl d1,_whichqs 868 Lsw2: 869 movl a0,_curproc 870 clrl _want_resched 871 #ifdef notyet 872 movl sp@+,a1 | XXX - Make this work! 873 cmpl a0,a1 | switching to same proc? 874 jeq Lswdone | yes, skip save and restore 875 #endif 876 /* 877 * Save state of previous process in its pcb. 878 */ 879 movl _curpcb,a1 880 moveml #0xFCFC,a1@(PCB_REGS) | save non-scratch registers 881 movl usp,a2 | grab USP (a2 has been saved) 882 movl a2,a1@(PCB_USP) | and save it 883 884 tstl _fputype | Do we have an fpu? 885 jeq Lswnofpsave | No? Then don't try save. 886 lea a1@(PCB_FPCTX),a2 | pointer to FP save area 887 fsave a2@ | save FP state 888 tstb a2@ | null state frame? 889 jeq Lswnofpsave | yes, all done 890 fmovem fp0-fp7,a2@(FPF_REGS) | save FP general regs 891 fmovem fpcr/fpsr/fpi,a2@(FPF_FPCR) | save FP control regs 892 Lswnofpsave: 893 894 /* 895 * Now that we have saved all the registers that must be 896 * preserved, we are free to use those registers until 897 * we load the registers for the switched-to process. 898 * In this section, keep: a0=curproc, a1=curpcb 899 */ 900 901 #ifdef DIAGNOSTIC 902 tstl a0@(P_WCHAN) 903 jne Lbadsw 904 cmpb #SRUN,a0@(P_STAT) 905 jne Lbadsw 906 #endif 907 clrl a0@(P_BACK) | clear back link 908 movl a0@(P_ADDR),a1 | get p_addr 909 movl a1,_curpcb 910 911 /* 912 * Load the new VM context (new MMU root pointer) 913 */ 914 movl a0@(P_VMSPACE),a2 | vm = p->p_vmspace 915 #ifdef DIAGNOSTIC 916 tstl a2 | map == VM_MAP_NULL? 917 jeq Lbadsw | panic 918 #endif 919 #ifdef PMAP_DEBUG 920 /* 921 * Just call pmap_activate() for now. Later on, 922 * use the in-line version below (for speed). 923 */ 924 lea a2@(VM_PMAP),a2 | pmap = &vmspace.vm_pmap 925 pea a2@ | push pmap 926 jbsr _pmap_activate | pmap_activate(pmap) 927 addql #4,sp 928 movl _curpcb,a1 | restore p_addr 929 #else 930 /* XXX - Later, use this inline version. */ 931 /* Just load the new CPU Root Pointer (MMU) */ 932 lea _kernel_crp, a3 | our CPU Root Ptr. (CRP) 933 lea a2@(VM_PMAP),a2 | pmap = &vmspace.vm_pmap 934 movl a2@(PM_A_PHYS),d0 | phys = pmap->pm_a_phys 935 cmpl a3@(4),d0 | == kernel_crp.rp_addr ? 936 jeq Lsame_mmuctx | skip loadcrp/flush 937 /* OK, it is a new MMU context. Load it up. */ 938 movl d0,a3@(4) 939 movl #CACHE_CLR,d0 940 movc d0,cacr | invalidate cache(s) 941 pflusha | flush entire TLB 942 pmove a3@,crp | load new user root pointer 943 Lsame_mmuctx: 944 #endif 945 946 /* 947 * Reload the registers for the new process. 948 * After this point we can only use d0,d1,a0,a1 949 */ 950 moveml a1@(PCB_REGS),#0xFCFC | reload registers 951 movl a1@(PCB_USP),a0 952 movl a0,usp | and USP 953 954 tstl _fputype | If we don't have an fpu, 955 jeq Lres_skip | don't try to restore it. 956 lea a1@(PCB_FPCTX),a0 | pointer to FP save area 957 tstb a0@ | null state frame? 958 jeq Lresfprest | yes, easy 959 fmovem a0@(FPF_FPCR),fpcr/fpsr/fpi | restore FP control regs 960 fmovem a0@(FPF_REGS),fp0-fp7 | restore FP general regs 961 Lresfprest: 962 frestore a0@ | restore state 963 Lres_skip: 964 movw a1@(PCB_PS),d0 | no, restore PS 965 #ifdef DIAGNOSTIC 966 btst #13,d0 | supervisor mode? 967 jeq Lbadsw | no? panic! 968 #endif 969 movw d0,sr | OK, restore PS 970 moveq #1,d0 | return 1 (for alternate returns) 971 rts 972 973 /* 974 * savectx(pcb) 975 * Update pcb, saving current processor state. 976 */ 977 ENTRY(savectx) 978 movl sp@(4),a1 979 movw sr,a1@(PCB_PS) 980 movl usp,a0 | grab USP 981 movl a0,a1@(PCB_USP) | and save it 982 moveml #0xFCFC,a1@(PCB_REGS) | save non-scratch registers 983 984 tstl _fputype | Do we have FPU? 985 jeq Lsavedone | No? Then don't save state. 986 lea a1@(PCB_FPCTX),a0 | pointer to FP save area 987 fsave a0@ | save FP state 988 tstb a0@ | null state frame? 989 jeq Lsavedone | yes, all done 990 fmovem fp0-fp7,a0@(FPF_REGS) | save FP general regs 991 fmovem fpcr/fpsr/fpi,a0@(FPF_FPCR) | save FP control regs 992 Lsavedone: 993 moveq #0,d0 | return 0 994 rts 995 996 /* suline() `040 only */ 997 998 #ifdef DEBUG 999 .data 1000 .globl fulltflush, fullcflush 1001 fulltflush: 1002 .long 0 1003 fullcflush: 1004 .long 0 1005 .text 1006 #endif 1007 1008 /* 1009 * Invalidate entire TLB. 1010 */ 1011 ENTRY(TBIA) 1012 __TBIA: 1013 pflusha 1014 movl #DC_CLEAR,d0 1015 movc d0,cacr | invalidate on-chip d-cache 1016 rts 1017 1018 /* 1019 * Invalidate any TLB entry for given VA (TB Invalidate Single) 1020 */ 1021 ENTRY(TBIS) 1022 #ifdef DEBUG 1023 tstl fulltflush | being conservative? 1024 jne __TBIA | yes, flush entire TLB 1025 #endif 1026 movl sp@(4),a0 1027 pflush #0,#0,a0@ | flush address from both sides 1028 movl #DC_CLEAR,d0 1029 movc d0,cacr | invalidate on-chip data cache 1030 rts 1031 1032 /* 1033 * Invalidate supervisor side of TLB 1034 */ 1035 ENTRY(TBIAS) 1036 #ifdef DEBUG 1037 tstl fulltflush | being conservative? 1038 jne __TBIA | yes, flush everything 1039 #endif 1040 pflush #4,#4 | flush supervisor TLB entries 1041 movl #DC_CLEAR,d0 1042 movc d0,cacr | invalidate on-chip d-cache 1043 rts 1044 1045 /* 1046 * Invalidate user side of TLB 1047 */ 1048 ENTRY(TBIAU) 1049 #ifdef DEBUG 1050 tstl fulltflush | being conservative? 1051 jne __TBIA | yes, flush everything 1052 #endif 1053 pflush #0,#4 | flush user TLB entries 1054 movl #DC_CLEAR,d0 1055 movc d0,cacr | invalidate on-chip d-cache 1056 rts 1057 1058 /* 1059 * Invalidate instruction cache 1060 */ 1061 ENTRY(ICIA) 1062 movl #IC_CLEAR,d0 1063 movc d0,cacr | invalidate i-cache 1064 rts 1065 1066 /* 1067 * Invalidate data cache. 1068 * NOTE: we do not flush 68030 on-chip cache as there are no aliasing 1069 * problems with DC_WA. The only cases we have to worry about are context 1070 * switch and TLB changes, both of which are handled "in-line" in resume 1071 * and TBI*. 1072 */ 1073 ENTRY(DCIA) 1074 __DCIA: 1075 rts 1076 1077 ENTRY(DCIS) 1078 __DCIS: 1079 rts 1080 1081 /* 1082 * Invalidate data cache. 1083 */ 1084 ENTRY(DCIU) 1085 movl #DC_CLEAR,d0 1086 movc d0,cacr | invalidate on-chip d-cache 1087 rts 1088 1089 /* ICPL, ICPP, DCPL, DCPP, DCPA, DCFL, DCFP */ 1090 1091 ENTRY(PCIA) 1092 movl #DC_CLEAR,d0 1093 movc d0,cacr | invalidate on-chip d-cache 1094 rts 1095 1096 ENTRY(ecacheon) 1097 rts 1098 1099 ENTRY(ecacheoff) 1100 rts 1101 1102 /* 1103 * Get callers current SP value. 1104 * Note that simply taking the address of a local variable in a C function 1105 * doesn't work because callee saved registers may be outside the stack frame 1106 * defined by A6 (e.g. GCC generated code). 1107 * 1108 * [I don't think the ENTRY() macro will do the right thing with this -- glass] 1109 */ 1110 .globl _getsp 1111 _getsp: 1112 movl sp,d0 | get current SP 1113 addql #4,d0 | compensate for return address 1114 rts 1115 1116 ENTRY(getsfc) 1117 movc sfc,d0 1118 rts 1119 1120 ENTRY(getdfc) 1121 movc dfc,d0 1122 rts 1123 1124 ENTRY(getvbr) 1125 movc vbr, d0 1126 rts 1127 1128 ENTRY(setvbr) 1129 movl sp@(4), d0 1130 movc d0, vbr 1131 rts 1132 1133 /* 1134 * Load a new CPU Root Pointer (CRP) into the MMU. 1135 * void loadcrp(struct mmu_rootptr *); 1136 */ 1137 ENTRY(loadcrp) 1138 movl sp@(4),a0 | arg1: &CRP 1139 movl #CACHE_CLR,d0 1140 movc d0,cacr | invalidate cache(s) 1141 pflusha | flush entire TLB 1142 pmove a0@,crp | load new user root pointer 1143 rts 1144 1145 /* 1146 * Get the physical address of the PTE for a given VA. 1147 */ 1148 ENTRY(ptest_addr) 1149 movl sp@(4),a0 | VA 1150 ptestr #5,a0@,#7,a1 | a1 = addr of PTE 1151 movl a1,d0 1152 rts 1153 1154 /* 1155 * Set processor priority level calls. Most are implemented with 1156 * inline asm expansions. However, we need one instantiation here 1157 * in case some non-optimized code makes external references. 1158 * Most places will use the inlined function param.h supplies. 1159 */ 1160 1161 ENTRY(_spl) 1162 movl sp@(4),d1 1163 clrl d0 1164 movw sr,d0 1165 movw d1,sr 1166 rts 1167 1168 ENTRY(getsr) 1169 moveq #0, d0 1170 movw sr, d0 1171 rts 1172 1173 /* 1174 * Save and restore 68881 state. 1175 */ 1176 ENTRY(m68881_save) 1177 movl sp@(4),a0 | save area pointer 1178 fsave a0@ | save state 1179 tstb a0@ | null state frame? 1180 jeq Lm68881sdone | yes, all done 1181 fmovem fp0-fp7,a0@(FPF_REGS) | save FP general regs 1182 fmovem fpcr/fpsr/fpi,a0@(FPF_FPCR) | save FP control regs 1183 Lm68881sdone: 1184 rts 1185 1186 ENTRY(m68881_restore) 1187 movl sp@(4),a0 | save area pointer 1188 tstb a0@ | null state frame? 1189 jeq Lm68881rdone | yes, easy 1190 fmovem a0@(FPF_FPCR),fpcr/fpsr/fpi | restore FP control regs 1191 fmovem a0@(FPF_REGS),fp0-fp7 | restore FP general regs 1192 Lm68881rdone: 1193 frestore a0@ | restore state 1194 rts 1195 1196 /* 1197 * _delay(unsigned N) 1198 * Delay for at least (N/256) microseconds. 1199 * This routine depends on the variable: delay_divisor 1200 * which should be set based on the CPU clock rate. 1201 * XXX: Currently this is set in sun3_startup.c based on the 1202 * XXX: CPU model but this should be determined at run time... 1203 */ 1204 .globl __delay 1205 __delay: 1206 | d0 = arg = (usecs << 8) 1207 movl sp@(4),d0 1208 | d1 = delay_divisor; 1209 movl _delay_divisor,d1 1210 L_delay: 1211 subl d1,d0 1212 jgt L_delay 1213 rts 1214 1215 1216 | Define some addresses, mostly so DDB can print useful info. 1217 .globl _kernbase 1218 .set _kernbase,KERNBASE 1219 .globl _dvma_base 1220 .set _dvma_base,DVMA_SPACE_START 1221 .globl _prom_start 1222 .set _prom_start,MONSTART 1223 .globl _prom_base 1224 .set _prom_base,PROM_BASE 1225 1226 |The end! 1227
Indexes created Thu Oct 30 03:10:01 GMT 2025