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pmap.c revision 1.113.10.1
      1  1.113.10.1  pgoyette /*	$NetBSD: pmap.c,v 1.113.10.1 2017/01/07 08:56:27 pgoyette Exp $	*/
      2         1.1       gwr 
      3         1.1       gwr /*-
      4        1.10    jeremy  * Copyright (c) 1996, 1997 The NetBSD Foundation, Inc.
      5         1.1       gwr  * All rights reserved.
      6         1.1       gwr  *
      7         1.1       gwr  * This code is derived from software contributed to The NetBSD Foundation
      8         1.1       gwr  * by Jeremy Cooper.
      9         1.1       gwr  *
     10         1.1       gwr  * Redistribution and use in source and binary forms, with or without
     11         1.1       gwr  * modification, are permitted provided that the following conditions
     12         1.1       gwr  * are met:
     13         1.1       gwr  * 1. Redistributions of source code must retain the above copyright
     14         1.1       gwr  *    notice, this list of conditions and the following disclaimer.
     15         1.1       gwr  * 2. Redistributions in binary form must reproduce the above copyright
     16         1.1       gwr  *    notice, this list of conditions and the following disclaimer in the
     17         1.1       gwr  *    documentation and/or other materials provided with the distribution.
     18         1.1       gwr  *
     19         1.1       gwr  * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
     20         1.1       gwr  * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
     21         1.1       gwr  * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
     22         1.1       gwr  * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
     23         1.1       gwr  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
     24         1.1       gwr  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
     25         1.1       gwr  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
     26         1.1       gwr  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
     27         1.1       gwr  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
     28         1.1       gwr  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
     29         1.1       gwr  * POSSIBILITY OF SUCH DAMAGE.
     30         1.1       gwr  */
     31         1.1       gwr 
     32         1.1       gwr /*
     33         1.1       gwr  * XXX These comments aren't quite accurate.  Need to change.
     34         1.1       gwr  * The sun3x uses the MC68851 Memory Management Unit, which is built
     35         1.1       gwr  * into the CPU.  The 68851 maps virtual to physical addresses using
     36         1.1       gwr  * a multi-level table lookup, which is stored in the very memory that
     37         1.1       gwr  * it maps.  The number of levels of lookup is configurable from one
     38         1.1       gwr  * to four.  In this implementation, we use three, named 'A' through 'C'.
     39         1.1       gwr  *
     40       1.113   tsutsui  * The MMU translates virtual addresses into physical addresses by
     41       1.113   tsutsui  * traversing these tables in a process called a 'table walk'.  The most
     42       1.113   tsutsui  * significant 7 bits of the Virtual Address ('VA') being translated are
     43       1.113   tsutsui  * used as an index into the level A table, whose base in physical memory
     44       1.113   tsutsui  * is stored in a special MMU register, the 'CPU Root Pointer' or CRP.  The
     45         1.1       gwr  * address found at that index in the A table is used as the base
     46       1.113   tsutsui  * address for the next table, the B table.  The next six bits of the VA are
     47       1.113   tsutsui  * used as an index into the B table, which in turn gives the base address
     48         1.1       gwr  * of the third and final C table.
     49         1.1       gwr  *
     50         1.1       gwr  * The next six bits of the VA are used as an index into the C table to
     51         1.1       gwr  * locate a Page Table Entry (PTE).  The PTE is a physical address in memory
     52         1.1       gwr  * to which the remaining 13 bits of the VA are added, producing the
     53         1.1       gwr  * mapped physical address.
     54         1.1       gwr  *
     55       1.113   tsutsui  * To map the entire memory space in this manner would require 2114296 bytes
     56       1.113   tsutsui  * of page tables per process - quite expensive.  Instead we will
     57       1.113   tsutsui  * allocate a fixed but considerably smaller space for the page tables at
     58         1.1       gwr  * the time the VM system is initialized.  When the pmap code is asked by
     59         1.1       gwr  * the kernel to map a VA to a PA, it allocates tables as needed from this
     60         1.1       gwr  * pool.  When there are no more tables in the pool, tables are stolen
     61       1.113   tsutsui  * from the oldest mapped entries in the tree.  This is only possible
     62         1.1       gwr  * because all memory mappings are stored in the kernel memory map
     63         1.1       gwr  * structures, independent of the pmap structures.  A VA which references
     64         1.1       gwr  * one of these invalidated maps will cause a page fault.  The kernel
     65       1.113   tsutsui  * will determine that the page fault was caused by a task using a valid
     66         1.1       gwr  * VA, but for some reason (which does not concern it), that address was
     67         1.1       gwr  * not mapped.  It will ask the pmap code to re-map the entry and then
     68         1.1       gwr  * it will resume executing the faulting task.
     69         1.1       gwr  *
     70         1.1       gwr  * In this manner the most efficient use of the page table space is
     71       1.113   tsutsui  * achieved.  Tasks which do not execute often will have their tables
     72         1.1       gwr  * stolen and reused by tasks which execute more frequently.  The best
     73       1.113   tsutsui  * size for the page table pool will probably be determined by
     74         1.1       gwr  * experimentation.
     75         1.1       gwr  *
     76         1.1       gwr  * You read all of the comments so far.  Good for you.
     77         1.1       gwr  * Now go play!
     78         1.1       gwr  */
     79         1.1       gwr 
     80         1.1       gwr /*** A Note About the 68851 Address Translation Cache
     81         1.1       gwr  * The MC68851 has a 64 entry cache, called the Address Translation Cache
     82         1.1       gwr  * or 'ATC'.  This cache stores the most recently used page descriptors
     83         1.1       gwr  * accessed by the MMU when it does translations.  Using a marker called a
     84         1.1       gwr  * 'task alias' the MMU can store the descriptors from 8 different table
     85         1.1       gwr  * spaces concurrently.  The task alias is associated with the base
     86         1.1       gwr  * address of the level A table of that address space.  When an address
     87         1.1       gwr  * space is currently active (the CRP currently points to its A table)
     88         1.1       gwr  * the only cached descriptors that will be obeyed are ones which have a
     89         1.1       gwr  * matching task alias of the current space associated with them.
     90         1.1       gwr  *
     91         1.1       gwr  * Since the cache is always consulted before any table lookups are done,
     92         1.1       gwr  * it is important that it accurately reflect the state of the MMU tables.
     93         1.1       gwr  * Whenever a change has been made to a table that has been loaded into
     94         1.1       gwr  * the MMU, the code must be sure to flush any cached entries that are
     95         1.1       gwr  * affected by the change.  These instances are documented in the code at
     96         1.1       gwr  * various points.
     97         1.1       gwr  */
     98         1.1       gwr /*** A Note About the Note About the 68851 Address Translation Cache
     99         1.1       gwr  * 4 months into this code I discovered that the sun3x does not have
    100         1.1       gwr  * a MC68851 chip. Instead, it has a version of this MMU that is part of the
    101         1.1       gwr  * the 68030 CPU.
    102         1.1       gwr  * All though it behaves very similarly to the 68851, it only has 1 task
    103         1.8       gwr  * alias and a 22 entry cache.  So sadly (or happily), the first paragraph
    104         1.8       gwr  * of the previous note does not apply to the sun3x pmap.
    105         1.1       gwr  */
    106        1.83     lukem 
    107        1.83     lukem #include <sys/cdefs.h>
    108  1.113.10.1  pgoyette __KERNEL_RCSID(0, "$NetBSD: pmap.c,v 1.113.10.1 2017/01/07 08:56:27 pgoyette Exp $");
    109        1.45       gwr 
    110        1.45       gwr #include "opt_ddb.h"
    111        1.82    martin #include "opt_pmap_debug.h"
    112         1.1       gwr 
    113         1.1       gwr #include <sys/param.h>
    114         1.1       gwr #include <sys/systm.h>
    115         1.1       gwr #include <sys/proc.h>
    116         1.1       gwr #include <sys/malloc.h>
    117        1.56   tsutsui #include <sys/pool.h>
    118         1.1       gwr #include <sys/queue.h>
    119        1.20   thorpej #include <sys/kcore.h>
    120       1.112   tsutsui #include <sys/atomic.h>
    121        1.38       gwr 
    122        1.38       gwr #include <uvm/uvm.h>
    123        1.43       mrg 
    124         1.1       gwr #include <machine/cpu.h>
    125        1.17       gwr #include <machine/kcore.h>
    126        1.33       gwr #include <machine/mon.h>
    127         1.1       gwr #include <machine/pmap.h>
    128         1.1       gwr #include <machine/pte.h>
    129        1.37       gwr #include <machine/vmparam.h>
    130        1.75       chs #include <m68k/cacheops.h>
    131        1.33       gwr 
    132        1.33       gwr #include <sun3/sun3/cache.h>
    133        1.33       gwr #include <sun3/sun3/machdep.h>
    134         1.1       gwr 
    135         1.1       gwr #include "pmap_pvt.h"
    136         1.1       gwr 
    137         1.1       gwr /* XXX - What headers declare these? */
    138         1.1       gwr extern struct pcb *curpcb;
    139         1.7       gwr 
    140         1.1       gwr /* Defined in locore.s */
    141         1.1       gwr extern char kernel_text[];
    142         1.1       gwr 
    143         1.1       gwr /* Defined by the linker */
    144         1.1       gwr extern char etext[], edata[], end[];
    145         1.1       gwr extern char *esym;	/* DDB */
    146         1.1       gwr 
    147         1.7       gwr /*************************** DEBUGGING DEFINITIONS ***********************
    148         1.7       gwr  * Macros, preprocessor defines and variables used in debugging can make *
    149         1.7       gwr  * code hard to read.  Anything used exclusively for debugging purposes  *
    150         1.7       gwr  * is defined here to avoid having such mess scattered around the file.  *
    151         1.7       gwr  *************************************************************************/
    152         1.8       gwr #ifdef	PMAP_DEBUG
    153         1.7       gwr /*
    154         1.7       gwr  * To aid the debugging process, macros should be expanded into smaller steps
    155         1.7       gwr  * that accomplish the same goal, yet provide convenient places for placing
    156         1.8       gwr  * breakpoints.  When this code is compiled with PMAP_DEBUG mode defined, the
    157         1.7       gwr  * 'INLINE' keyword is defined to an empty string.  This way, any function
    158         1.7       gwr  * defined to be a 'static INLINE' will become 'outlined' and compiled as
    159         1.7       gwr  * a separate function, which is much easier to debug.
    160         1.7       gwr  */
    161         1.7       gwr #define	INLINE	/* nothing */
    162         1.7       gwr 
    163         1.1       gwr /*
    164         1.7       gwr  * It is sometimes convenient to watch the activity of a particular table
    165         1.7       gwr  * in the system.  The following variables are used for that purpose.
    166         1.1       gwr  */
    167         1.7       gwr a_tmgr_t *pmap_watch_atbl = 0;
    168         1.7       gwr b_tmgr_t *pmap_watch_btbl = 0;
    169         1.7       gwr c_tmgr_t *pmap_watch_ctbl = 0;
    170         1.1       gwr 
    171         1.7       gwr int pmap_debug = 0;
    172         1.7       gwr #define DPRINT(args) if (pmap_debug) printf args
    173         1.7       gwr 
    174         1.7       gwr #else	/********** Stuff below is defined if NOT debugging **************/
    175         1.7       gwr 
    176         1.7       gwr #define	INLINE	inline
    177        1.10    jeremy #define DPRINT(args)  /* nada */
    178         1.7       gwr 
    179        1.10    jeremy #endif	/* PMAP_DEBUG */
    180         1.7       gwr /*********************** END OF DEBUGGING DEFINITIONS ********************/
    181         1.1       gwr 
    182         1.1       gwr /*** Management Structure - Memory Layout
    183         1.1       gwr  * For every MMU table in the sun3x pmap system there must be a way to
    184         1.1       gwr  * manage it; we must know which process is using it, what other tables
    185         1.1       gwr  * depend on it, and whether or not it contains any locked pages.  This
    186         1.1       gwr  * is solved by the creation of 'table management'  or 'tmgr'
    187         1.1       gwr  * structures.  One for each MMU table in the system.
    188         1.1       gwr  *
    189         1.1       gwr  *                        MAP OF MEMORY USED BY THE PMAP SYSTEM
    190         1.1       gwr  *
    191         1.1       gwr  *      towards lower memory
    192         1.1       gwr  * kernAbase -> +-------------------------------------------------------+
    193         1.1       gwr  *              | Kernel     MMU A level table                          |
    194         1.1       gwr  * kernBbase -> +-------------------------------------------------------+
    195         1.1       gwr  *              | Kernel     MMU B level tables                         |
    196         1.1       gwr  * kernCbase -> +-------------------------------------------------------+
    197         1.1       gwr  *              |                                                       |
    198         1.1       gwr  *              | Kernel     MMU C level tables                         |
    199         1.1       gwr  *              |                                                       |
    200         1.7       gwr  * mmuCbase  -> +-------------------------------------------------------+
    201         1.7       gwr  *              | User       MMU C level tables                         |
    202         1.1       gwr  * mmuAbase  -> +-------------------------------------------------------+
    203         1.1       gwr  *              |                                                       |
    204         1.1       gwr  *              | User       MMU A level tables                         |
    205         1.1       gwr  *              |                                                       |
    206         1.1       gwr  * mmuBbase  -> +-------------------------------------------------------+
    207         1.1       gwr  *              | User       MMU B level tables                         |
    208         1.1       gwr  * tmgrAbase -> +-------------------------------------------------------+
    209         1.1       gwr  *              |  TMGR A level table structures                        |
    210         1.1       gwr  * tmgrBbase -> +-------------------------------------------------------+
    211         1.1       gwr  *              |  TMGR B level table structures                        |
    212         1.1       gwr  * tmgrCbase -> +-------------------------------------------------------+
    213         1.1       gwr  *              |  TMGR C level table structures                        |
    214         1.1       gwr  * pvbase    -> +-------------------------------------------------------+
    215         1.1       gwr  *              |  Physical to Virtual mapping table (list heads)       |
    216         1.1       gwr  * pvebase   -> +-------------------------------------------------------+
    217         1.1       gwr  *              |  Physical to Virtual mapping table (list elements)    |
    218         1.1       gwr  *              |                                                       |
    219         1.1       gwr  *              +-------------------------------------------------------+
    220         1.1       gwr  *      towards higher memory
    221         1.1       gwr  *
    222         1.1       gwr  * For every A table in the MMU A area, there will be a corresponding
    223         1.1       gwr  * a_tmgr structure in the TMGR A area.  The same will be true for
    224         1.1       gwr  * the B and C tables.  This arrangement will make it easy to find the
    225         1.1       gwr  * controling tmgr structure for any table in the system by use of
    226         1.1       gwr  * (relatively) simple macros.
    227         1.1       gwr  */
    228         1.7       gwr 
    229         1.7       gwr /*
    230         1.8       gwr  * Global variables for storing the base addresses for the areas
    231         1.1       gwr  * labeled above.
    232         1.1       gwr  */
    233        1.69       chs static vaddr_t  	kernAphys;
    234         1.1       gwr static mmu_long_dte_t	*kernAbase;
    235         1.1       gwr static mmu_short_dte_t	*kernBbase;
    236         1.1       gwr static mmu_short_pte_t	*kernCbase;
    237        1.15       gwr static mmu_short_pte_t	*mmuCbase;
    238        1.15       gwr static mmu_short_dte_t	*mmuBbase;
    239         1.1       gwr static mmu_long_dte_t	*mmuAbase;
    240         1.1       gwr static a_tmgr_t		*Atmgrbase;
    241         1.1       gwr static b_tmgr_t		*Btmgrbase;
    242         1.1       gwr static c_tmgr_t		*Ctmgrbase;
    243        1.15       gwr static pv_t 		*pvbase;
    244         1.1       gwr static pv_elem_t	*pvebase;
    245       1.100     pooka static struct pmap	kernel_pmap;
    246       1.101     pooka struct pmap		*const kernel_pmap_ptr = &kernel_pmap;
    247         1.1       gwr 
    248         1.8       gwr /*
    249         1.8       gwr  * This holds the CRP currently loaded into the MMU.
    250         1.8       gwr  */
    251         1.8       gwr struct mmu_rootptr kernel_crp;
    252         1.8       gwr 
    253         1.8       gwr /*
    254         1.8       gwr  * Just all around global variables.
    255         1.1       gwr  */
    256         1.1       gwr static TAILQ_HEAD(a_pool_head_struct, a_tmgr_struct) a_pool;
    257         1.1       gwr static TAILQ_HEAD(b_pool_head_struct, b_tmgr_struct) b_pool;
    258         1.1       gwr static TAILQ_HEAD(c_pool_head_struct, c_tmgr_struct) c_pool;
    259         1.7       gwr 
    260         1.7       gwr 
    261         1.7       gwr /*
    262         1.7       gwr  * Flags used to mark the safety/availability of certain operations or
    263         1.7       gwr  * resources.
    264         1.7       gwr  */
    265        1.92   tsutsui /* Safe to use pmap_bootstrap_alloc(). */
    266        1.95   thorpej static bool bootstrap_alloc_enabled = false;
    267        1.92   tsutsui /* Temporary virtual pages are in use */
    268        1.92   tsutsui int tmp_vpages_inuse;
    269         1.1       gwr 
    270         1.1       gwr /*
    271         1.1       gwr  * XXX:  For now, retain the traditional variables that were
    272         1.1       gwr  * used in the old pmap/vm interface (without NONCONTIG).
    273         1.1       gwr  */
    274        1.81   thorpej /* Kernel virtual address space available: */
    275        1.81   thorpej vaddr_t	virtual_avail, virtual_end;
    276         1.1       gwr /* Physical address space available: */
    277        1.69       chs paddr_t	avail_start, avail_end;
    278         1.1       gwr 
    279         1.7       gwr /* This keep track of the end of the contiguously mapped range. */
    280        1.69       chs vaddr_t virtual_contig_end;
    281         1.7       gwr 
    282         1.7       gwr /* Physical address used by pmap_next_page() */
    283        1.69       chs paddr_t avail_next;
    284         1.7       gwr 
    285         1.7       gwr /* These are used by pmap_copy_page(), etc. */
    286        1.69       chs vaddr_t tmp_vpages[2];
    287         1.1       gwr 
    288        1.56   tsutsui /* memory pool for pmap structures */
    289        1.56   tsutsui struct pool	pmap_pmap_pool;
    290        1.56   tsutsui 
    291         1.7       gwr /*
    292         1.7       gwr  * The 3/80 is the only member of the sun3x family that has non-contiguous
    293         1.1       gwr  * physical memory.  Memory is divided into 4 banks which are physically
    294         1.1       gwr  * locatable on the system board.  Although the size of these banks varies
    295         1.1       gwr  * with the size of memory they contain, their base addresses are
    296         1.1       gwr  * permenently fixed.  The following structure, which describes these
    297         1.1       gwr  * banks, is initialized by pmap_bootstrap() after it reads from a similar
    298         1.1       gwr  * structure provided by the ROM Monitor.
    299         1.1       gwr  *
    300         1.1       gwr  * For the other machines in the sun3x architecture which do have contiguous
    301         1.1       gwr  * RAM, this list will have only one entry, which will describe the entire
    302         1.1       gwr  * range of available memory.
    303         1.1       gwr  */
    304        1.20   thorpej struct pmap_physmem_struct avail_mem[SUN3X_NPHYS_RAM_SEGS];
    305         1.1       gwr u_int total_phys_mem;
    306         1.1       gwr 
    307         1.7       gwr /*************************************************************************/
    308         1.7       gwr 
    309         1.7       gwr /*
    310         1.7       gwr  * XXX - Should "tune" these based on statistics.
    311         1.7       gwr  *
    312         1.7       gwr  * My first guess about the relative numbers of these needed is
    313         1.7       gwr  * based on the fact that a "typical" process will have several
    314         1.7       gwr  * pages mapped at low virtual addresses (text, data, bss), then
    315         1.7       gwr  * some mapped shared libraries, and then some stack pages mapped
    316         1.7       gwr  * near the high end of the VA space.  Each process can use only
    317         1.7       gwr  * one A table, and most will use only two B tables (maybe three)
    318         1.7       gwr  * and probably about four C tables.  Therefore, the first guess
    319         1.7       gwr  * at the relative numbers of these needed is 1:2:4 -gwr
    320         1.7       gwr  *
    321         1.7       gwr  * The number of C tables needed is closely related to the amount
    322         1.7       gwr  * of physical memory available plus a certain amount attributable
    323         1.7       gwr  * to the use of double mappings.  With a few simulation statistics
    324         1.7       gwr  * we can find a reasonably good estimation of this unknown value.
    325         1.7       gwr  * Armed with that and the above ratios, we have a good idea of what
    326         1.7       gwr  * is needed at each level. -j
    327         1.7       gwr  *
    328         1.7       gwr  * Note: It is not physical memory memory size, but the total mapped
    329         1.7       gwr  * virtual space required by the combined working sets of all the
    330         1.7       gwr  * currently _runnable_ processes.  (Sleeping ones don't count.)
    331         1.7       gwr  * The amount of physical memory should be irrelevant. -gwr
    332         1.7       gwr  */
    333        1.22    jeremy #ifdef	FIXED_NTABLES
    334         1.7       gwr #define NUM_A_TABLES	16
    335         1.7       gwr #define NUM_B_TABLES	32
    336         1.7       gwr #define NUM_C_TABLES	64
    337        1.22    jeremy #else
    338        1.22    jeremy unsigned int	NUM_A_TABLES, NUM_B_TABLES, NUM_C_TABLES;
    339        1.22    jeremy #endif	/* FIXED_NTABLES */
    340         1.7       gwr 
    341         1.7       gwr /*
    342         1.7       gwr  * This determines our total virtual mapping capacity.
    343         1.7       gwr  * Yes, it is a FIXED value so we can pre-allocate.
    344         1.7       gwr  */
    345         1.7       gwr #define NUM_USER_PTES	(NUM_C_TABLES * MMU_C_TBL_SIZE)
    346        1.15       gwr 
    347        1.15       gwr /*
    348        1.15       gwr  * The size of the Kernel Virtual Address Space (KVAS)
    349        1.15       gwr  * for purposes of MMU table allocation is -KERNBASE
    350        1.15       gwr  * (length from KERNBASE to 0xFFFFffff)
    351        1.15       gwr  */
    352       1.111   tsutsui #define	KVAS_SIZE		(-KERNBASE3X)
    353        1.15       gwr 
    354        1.15       gwr /* Numbers of kernel MMU tables to support KVAS_SIZE. */
    355        1.15       gwr #define KERN_B_TABLES	(KVAS_SIZE >> MMU_TIA_SHIFT)
    356        1.15       gwr #define KERN_C_TABLES	(KVAS_SIZE >> MMU_TIB_SHIFT)
    357        1.15       gwr #define	NUM_KERN_PTES	(KVAS_SIZE >> MMU_TIC_SHIFT)
    358         1.7       gwr 
    359         1.7       gwr /*************************** MISCELANEOUS MACROS *************************/
    360        1.64   thorpej void *pmap_bootstrap_alloc(int);
    361         1.7       gwr 
    362        1.86       chs static INLINE void *mmu_ptov(paddr_t);
    363        1.86       chs static INLINE paddr_t mmu_vtop(void *);
    364         1.7       gwr 
    365         1.7       gwr #if	0
    366        1.92   tsutsui static INLINE a_tmgr_t *mmuA2tmgr(mmu_long_dte_t *);
    367        1.26    jeremy #endif /* 0 */
    368        1.92   tsutsui static INLINE b_tmgr_t *mmuB2tmgr(mmu_short_dte_t *);
    369        1.92   tsutsui static INLINE c_tmgr_t *mmuC2tmgr(mmu_short_pte_t *);
    370         1.7       gwr 
    371        1.86       chs static INLINE pv_t *pa2pv(paddr_t);
    372        1.86       chs static INLINE int   pteidx(mmu_short_pte_t *);
    373        1.86       chs static INLINE pmap_t current_pmap(void);
    374         1.7       gwr 
    375         1.7       gwr /*
    376         1.7       gwr  * We can always convert between virtual and physical addresses
    377         1.7       gwr  * for anything in the range [KERNBASE ... avail_start] because
    378         1.7       gwr  * that range is GUARANTEED to be mapped linearly.
    379         1.7       gwr  * We rely heavily upon this feature!
    380         1.7       gwr  */
    381         1.7       gwr static INLINE void *
    382        1.86       chs mmu_ptov(paddr_t pa)
    383         1.7       gwr {
    384        1.69       chs 	vaddr_t va;
    385         1.7       gwr 
    386       1.111   tsutsui 	va = (pa + KERNBASE3X);
    387         1.8       gwr #ifdef	PMAP_DEBUG
    388       1.111   tsutsui 	if ((va < KERNBASE3X) || (va >= virtual_contig_end))
    389         1.7       gwr 		panic("mmu_ptov");
    390         1.7       gwr #endif
    391        1.92   tsutsui 	return (void *)va;
    392         1.7       gwr }
    393        1.69       chs 
    394       1.113   tsutsui static INLINE paddr_t
    395        1.86       chs mmu_vtop(void *vva)
    396         1.7       gwr {
    397        1.69       chs 	vaddr_t va;
    398         1.7       gwr 
    399        1.69       chs 	va = (vaddr_t)vva;
    400         1.8       gwr #ifdef	PMAP_DEBUG
    401       1.111   tsutsui 	if ((va < KERNBASE3X) || (va >= virtual_contig_end))
    402        1.72   tsutsui 		panic("mmu_vtop");
    403         1.7       gwr #endif
    404       1.111   tsutsui 	return va - KERNBASE3X;
    405         1.7       gwr }
    406         1.7       gwr 
    407         1.7       gwr /*
    408         1.7       gwr  * These macros map MMU tables to their corresponding manager structures.
    409         1.1       gwr  * They are needed quite often because many of the pointers in the pmap
    410         1.1       gwr  * system reference MMU tables and not the structures that control them.
    411         1.1       gwr  * There needs to be a way to find one when given the other and these
    412         1.1       gwr  * macros do so by taking advantage of the memory layout described above.
    413         1.1       gwr  * Here's a quick step through the first macro, mmuA2tmgr():
    414         1.1       gwr  *
    415         1.1       gwr  * 1) find the offset of the given MMU A table from the base of its table
    416         1.1       gwr  *    pool (table - mmuAbase).
    417         1.1       gwr  * 2) convert this offset into a table index by dividing it by the
    418         1.1       gwr  *    size of one MMU 'A' table. (sizeof(mmu_long_dte_t) * MMU_A_TBL_SIZE)
    419         1.1       gwr  * 3) use this index to select the corresponding 'A' table manager
    420         1.1       gwr  *    structure from the 'A' table manager pool (Atmgrbase[index]).
    421         1.1       gwr  */
    422         1.7       gwr /*  This function is not currently used. */
    423         1.7       gwr #if	0
    424         1.7       gwr static INLINE a_tmgr_t *
    425        1.86       chs mmuA2tmgr(mmu_long_dte_t *mmuAtbl)
    426         1.7       gwr {
    427        1.69       chs 	int idx;
    428         1.7       gwr 
    429         1.7       gwr 	/* Which table is this in? */
    430         1.7       gwr 	idx = (mmuAtbl - mmuAbase) / MMU_A_TBL_SIZE;
    431         1.8       gwr #ifdef	PMAP_DEBUG
    432         1.7       gwr 	if ((idx < 0) || (idx >= NUM_A_TABLES))
    433         1.7       gwr 		panic("mmuA2tmgr");
    434         1.7       gwr #endif
    435        1.92   tsutsui 	return &Atmgrbase[idx];
    436         1.7       gwr }
    437         1.7       gwr #endif	/* 0 */
    438         1.7       gwr 
    439         1.7       gwr static INLINE b_tmgr_t *
    440        1.86       chs mmuB2tmgr(mmu_short_dte_t *mmuBtbl)
    441         1.7       gwr {
    442        1.69       chs 	int idx;
    443         1.7       gwr 
    444         1.7       gwr 	/* Which table is this in? */
    445         1.7       gwr 	idx = (mmuBtbl - mmuBbase) / MMU_B_TBL_SIZE;
    446         1.8       gwr #ifdef	PMAP_DEBUG
    447         1.7       gwr 	if ((idx < 0) || (idx >= NUM_B_TABLES))
    448         1.7       gwr 		panic("mmuB2tmgr");
    449         1.7       gwr #endif
    450        1.92   tsutsui 	return &Btmgrbase[idx];
    451         1.7       gwr }
    452         1.7       gwr 
    453         1.7       gwr /* mmuC2tmgr			INTERNAL
    454         1.7       gwr  **
    455         1.7       gwr  * Given a pte known to belong to a C table, return the address of
    456         1.7       gwr  * that table's management structure.
    457         1.7       gwr  */
    458         1.7       gwr static INLINE c_tmgr_t *
    459        1.86       chs mmuC2tmgr(mmu_short_pte_t *mmuCtbl)
    460         1.7       gwr {
    461        1.69       chs 	int idx;
    462         1.7       gwr 
    463         1.7       gwr 	/* Which table is this in? */
    464         1.7       gwr 	idx = (mmuCtbl - mmuCbase) / MMU_C_TBL_SIZE;
    465         1.8       gwr #ifdef	PMAP_DEBUG
    466         1.7       gwr 	if ((idx < 0) || (idx >= NUM_C_TABLES))
    467         1.7       gwr 		panic("mmuC2tmgr");
    468         1.7       gwr #endif
    469        1.92   tsutsui 	return &Ctmgrbase[idx];
    470         1.7       gwr }
    471         1.7       gwr 
    472         1.8       gwr /* This is now a function call below.
    473         1.1       gwr  * #define pa2pv(pa) \
    474         1.1       gwr  *	(&pvbase[(unsigned long)\
    475        1.25     veego  *		m68k_btop(pa)\
    476         1.1       gwr  *	])
    477         1.1       gwr  */
    478         1.1       gwr 
    479         1.7       gwr /* pa2pv			INTERNAL
    480         1.7       gwr  **
    481         1.7       gwr  * Return the pv_list_head element which manages the given physical
    482         1.7       gwr  * address.
    483         1.7       gwr  */
    484         1.7       gwr static INLINE pv_t *
    485        1.86       chs pa2pv(paddr_t pa)
    486         1.7       gwr {
    487        1.69       chs 	struct pmap_physmem_struct *bank;
    488        1.69       chs 	int idx;
    489         1.7       gwr 
    490         1.7       gwr 	bank = &avail_mem[0];
    491         1.7       gwr 	while (pa >= bank->pmem_end)
    492         1.7       gwr 		bank = bank->pmem_next;
    493         1.7       gwr 
    494         1.7       gwr 	pa -= bank->pmem_start;
    495        1.25     veego 	idx = bank->pmem_pvbase + m68k_btop(pa);
    496         1.8       gwr #ifdef	PMAP_DEBUG
    497         1.7       gwr 	if ((idx < 0) || (idx >= physmem))
    498         1.7       gwr 		panic("pa2pv");
    499         1.7       gwr #endif
    500         1.7       gwr 	return &pvbase[idx];
    501         1.7       gwr }
    502         1.7       gwr 
    503         1.7       gwr /* pteidx			INTERNAL
    504         1.7       gwr  **
    505         1.7       gwr  * Return the index of the given PTE within the entire fixed table of
    506         1.7       gwr  * PTEs.
    507         1.7       gwr  */
    508         1.7       gwr static INLINE int
    509        1.86       chs pteidx(mmu_short_pte_t *pte)
    510         1.7       gwr {
    511        1.92   tsutsui 
    512        1.92   tsutsui 	return pte - kernCbase;
    513         1.7       gwr }
    514         1.7       gwr 
    515         1.7       gwr /*
    516         1.8       gwr  * This just offers a place to put some debugging checks,
    517        1.76   thorpej  * and reduces the number of places "curlwp" appears...
    518         1.7       gwr  */
    519       1.113   tsutsui static INLINE pmap_t
    520        1.86       chs current_pmap(void)
    521         1.7       gwr {
    522         1.7       gwr 	struct vmspace *vm;
    523        1.67       chs 	struct vm_map *map;
    524         1.7       gwr 	pmap_t	pmap;
    525         1.7       gwr 
    526        1.97   tsutsui 	vm = curproc->p_vmspace;
    527        1.97   tsutsui 	map = &vm->vm_map;
    528        1.97   tsutsui 	pmap = vm_map_pmap(map);
    529         1.7       gwr 
    530        1.92   tsutsui 	return pmap;
    531         1.7       gwr }
    532         1.7       gwr 
    533         1.7       gwr 
    534         1.1       gwr /*************************** FUNCTION DEFINITIONS ************************
    535         1.1       gwr  * These appear here merely for the compiler to enforce type checking on *
    536         1.1       gwr  * all function calls.                                                   *
    537         1.7       gwr  *************************************************************************/
    538         1.1       gwr 
    539        1.92   tsutsui /*
    540        1.92   tsutsui  * Internal functions
    541        1.92   tsutsui  */
    542        1.92   tsutsui a_tmgr_t *get_a_table(void);
    543        1.92   tsutsui b_tmgr_t *get_b_table(void);
    544        1.92   tsutsui c_tmgr_t *get_c_table(void);
    545        1.94   thorpej int free_a_table(a_tmgr_t *, bool);
    546        1.94   thorpej int free_b_table(b_tmgr_t *, bool);
    547        1.94   thorpej int free_c_table(c_tmgr_t *, bool);
    548        1.92   tsutsui 
    549        1.92   tsutsui void pmap_bootstrap_aalign(int);
    550        1.92   tsutsui void pmap_alloc_usermmu(void);
    551        1.92   tsutsui void pmap_alloc_usertmgr(void);
    552        1.92   tsutsui void pmap_alloc_pv(void);
    553        1.92   tsutsui void pmap_init_a_tables(void);
    554        1.92   tsutsui void pmap_init_b_tables(void);
    555        1.92   tsutsui void pmap_init_c_tables(void);
    556        1.92   tsutsui void pmap_init_pv(void);
    557        1.92   tsutsui void pmap_clear_pv(paddr_t, int);
    558        1.94   thorpej static INLINE bool is_managed(paddr_t);
    559        1.92   tsutsui 
    560        1.94   thorpej bool pmap_remove_a(a_tmgr_t *, vaddr_t, vaddr_t);
    561        1.94   thorpej bool pmap_remove_b(b_tmgr_t *, vaddr_t, vaddr_t);
    562        1.94   thorpej bool pmap_remove_c(c_tmgr_t *, vaddr_t, vaddr_t);
    563        1.92   tsutsui void pmap_remove_pte(mmu_short_pte_t *);
    564        1.92   tsutsui 
    565        1.92   tsutsui void pmap_enter_kernel(vaddr_t, paddr_t, vm_prot_t);
    566        1.92   tsutsui static INLINE void pmap_remove_kernel(vaddr_t, vaddr_t);
    567        1.92   tsutsui static INLINE void pmap_protect_kernel(vaddr_t, vaddr_t, vm_prot_t);
    568        1.94   thorpej static INLINE bool pmap_extract_kernel(vaddr_t, paddr_t *);
    569        1.92   tsutsui vaddr_t pmap_get_pteinfo(u_int, pmap_t *, c_tmgr_t **);
    570        1.92   tsutsui static INLINE int pmap_dereference(pmap_t);
    571        1.92   tsutsui 
    572        1.94   thorpej bool pmap_stroll(pmap_t, vaddr_t, a_tmgr_t **, b_tmgr_t **, c_tmgr_t **,
    573        1.92   tsutsui     mmu_short_pte_t **, int *, int *, int *);
    574        1.92   tsutsui void pmap_bootstrap_copyprom(void);
    575        1.92   tsutsui void pmap_takeover_mmu(void);
    576        1.92   tsutsui void pmap_bootstrap_setprom(void);
    577        1.86       chs static void pmap_page_upload(void);
    578         1.1       gwr 
    579        1.92   tsutsui #ifdef PMAP_DEBUG
    580        1.92   tsutsui /* Debugging function definitions */
    581        1.92   tsutsui void  pv_list(paddr_t, int);
    582        1.92   tsutsui #endif /* PMAP_DEBUG */
    583        1.92   tsutsui 
    584         1.1       gwr /** Interface functions
    585         1.1       gwr  ** - functions required by the Mach VM Pmap interface, with MACHINE_CONTIG
    586         1.1       gwr  **   defined.
    587        1.92   tsutsui  **   The new UVM doesn't require them so now INTERNAL.
    588         1.1       gwr  **/
    589        1.92   tsutsui static INLINE void pmap_pinit(pmap_t);
    590        1.92   tsutsui static INLINE void pmap_release(pmap_t);
    591         1.1       gwr 
    592         1.1       gwr /********************************** CODE ********************************
    593         1.1       gwr  * Functions that are called from other parts of the kernel are labeled *
    594         1.1       gwr  * as 'INTERFACE' functions.  Functions that are only called from       *
    595         1.1       gwr  * within the pmap module are labeled as 'INTERNAL' functions.          *
    596         1.1       gwr  * Functions that are internal, but are not (currently) used at all are *
    597         1.1       gwr  * labeled 'INTERNAL_X'.                                                *
    598       1.113   tsutsui  ************************************************************************/
    599         1.1       gwr 
    600         1.1       gwr /* pmap_bootstrap			INTERNAL
    601         1.1       gwr  **
    602        1.33       gwr  * Initializes the pmap system.  Called at boot time from
    603        1.33       gwr  * locore2.c:_vm_init()
    604         1.1       gwr  *
    605         1.1       gwr  * Reminder: having a pmap_bootstrap_alloc() and also having the VM
    606         1.1       gwr  *           system implement pmap_steal_memory() is redundant.
    607         1.1       gwr  *           Don't release this code without removing one or the other!
    608         1.1       gwr  */
    609       1.113   tsutsui void
    610        1.86       chs pmap_bootstrap(vaddr_t nextva)
    611         1.1       gwr {
    612         1.1       gwr 	struct physmemory *membank;
    613         1.1       gwr 	struct pmap_physmem_struct *pmap_membank;
    614        1.69       chs 	vaddr_t va, eva;
    615        1.69       chs 	paddr_t pa;
    616         1.1       gwr 	int b, c, i, j;	/* running table counts */
    617        1.40       gwr 	int size, resvmem;
    618         1.1       gwr 
    619         1.1       gwr 	/*
    620         1.1       gwr 	 * This function is called by __bootstrap after it has
    621         1.1       gwr 	 * determined the type of machine and made the appropriate
    622         1.1       gwr 	 * patches to the ROM vectors (XXX- I don't quite know what I meant
    623         1.1       gwr 	 * by that.)  It allocates and sets up enough of the pmap system
    624         1.1       gwr 	 * to manage the kernel's address space.
    625         1.1       gwr 	 */
    626         1.1       gwr 
    627         1.1       gwr 	/*
    628         1.7       gwr 	 * Determine the range of kernel virtual and physical
    629         1.7       gwr 	 * space available. Note that we ABSOLUTELY DEPEND on
    630         1.7       gwr 	 * the fact that the first bank of memory (4MB) is
    631         1.7       gwr 	 * mapped linearly to KERNBASE (which we guaranteed in
    632         1.7       gwr 	 * the first instructions of locore.s).
    633         1.7       gwr 	 * That is plenty for our bootstrap work.
    634         1.1       gwr 	 */
    635        1.25     veego 	virtual_avail = m68k_round_page(nextva);
    636       1.111   tsutsui 	virtual_contig_end = KERNBASE3X + 0x400000; /* +4MB */
    637         1.1       gwr 	virtual_end = VM_MAX_KERNEL_ADDRESS;
    638         1.7       gwr 	/* Don't need avail_start til later. */
    639         1.1       gwr 
    640         1.7       gwr 	/* We may now call pmap_bootstrap_alloc(). */
    641        1.95   thorpej 	bootstrap_alloc_enabled = true;
    642         1.1       gwr 
    643         1.1       gwr 	/*
    644         1.1       gwr 	 * This is a somewhat unwrapped loop to deal with
    645         1.1       gwr 	 * copying the PROM's 'phsymem' banks into the pmap's
    646         1.1       gwr 	 * banks.  The following is always assumed:
    647         1.1       gwr 	 * 1. There is always at least one bank of memory.
    648         1.1       gwr 	 * 2. There is always a last bank of memory, and its
    649         1.1       gwr 	 *    pmem_next member must be set to NULL.
    650         1.1       gwr 	 */
    651         1.1       gwr 	membank = romVectorPtr->v_physmemory;
    652         1.1       gwr 	pmap_membank = avail_mem;
    653         1.1       gwr 	total_phys_mem = 0;
    654         1.1       gwr 
    655        1.40       gwr 	for (;;) { /* break on !membank */
    656         1.1       gwr 		pmap_membank->pmem_start = membank->address;
    657         1.1       gwr 		pmap_membank->pmem_end = membank->address + membank->size;
    658         1.1       gwr 		total_phys_mem += membank->size;
    659        1.40       gwr 		membank = membank->next;
    660        1.40       gwr 		if (!membank)
    661        1.40       gwr 			break;
    662         1.1       gwr 		/* This silly syntax arises because pmap_membank
    663         1.1       gwr 		 * is really a pre-allocated array, but it is put into
    664         1.1       gwr 		 * use as a linked list.
    665         1.1       gwr 		 */
    666         1.1       gwr 		pmap_membank->pmem_next = pmap_membank + 1;
    667         1.1       gwr 		pmap_membank = pmap_membank->pmem_next;
    668         1.1       gwr 	}
    669        1.40       gwr 	/* This is the last element. */
    670        1.40       gwr 	pmap_membank->pmem_next = NULL;
    671         1.1       gwr 
    672         1.1       gwr 	/*
    673        1.40       gwr 	 * Note: total_phys_mem, physmem represent
    674        1.40       gwr 	 * actual physical memory, including that
    675        1.40       gwr 	 * reserved for the PROM monitor.
    676         1.1       gwr 	 */
    677        1.40       gwr 	physmem = btoc(total_phys_mem);
    678         1.1       gwr 
    679         1.1       gwr 	/*
    680        1.60   tsutsui 	 * Avail_end is set to the first byte of physical memory
    681        1.60   tsutsui 	 * after the end of the last bank.  We use this only to
    682        1.60   tsutsui 	 * determine if a physical address is "managed" memory.
    683        1.60   tsutsui 	 * This address range should be reduced to prevent the
    684        1.40       gwr 	 * physical pages needed by the PROM monitor from being used
    685        1.40       gwr 	 * in the VM system.
    686         1.1       gwr 	 */
    687        1.40       gwr 	resvmem = total_phys_mem - *(romVectorPtr->memoryAvail);
    688        1.40       gwr 	resvmem = m68k_round_page(resvmem);
    689        1.60   tsutsui 	avail_end = pmap_membank->pmem_end - resvmem;
    690         1.1       gwr 
    691         1.1       gwr 	/*
    692        1.15       gwr 	 * First allocate enough kernel MMU tables to map all
    693        1.15       gwr 	 * of kernel virtual space from KERNBASE to 0xFFFFFFFF.
    694         1.1       gwr 	 * Note: All must be aligned on 256 byte boundaries.
    695        1.15       gwr 	 * Start with the level-A table (one of those).
    696         1.1       gwr 	 */
    697        1.69       chs 	size = sizeof(mmu_long_dte_t) * MMU_A_TBL_SIZE;
    698         1.7       gwr 	kernAbase = pmap_bootstrap_alloc(size);
    699        1.71   tsutsui 	memset(kernAbase, 0, size);
    700         1.1       gwr 
    701        1.15       gwr 	/* Now the level-B kernel tables... */
    702        1.15       gwr 	size = sizeof(mmu_short_dte_t) * MMU_B_TBL_SIZE * KERN_B_TABLES;
    703         1.7       gwr 	kernBbase = pmap_bootstrap_alloc(size);
    704        1.71   tsutsui 	memset(kernBbase, 0, size);
    705         1.1       gwr 
    706        1.15       gwr 	/* Now the level-C kernel tables... */
    707        1.15       gwr 	size = sizeof(mmu_short_pte_t) * MMU_C_TBL_SIZE * KERN_C_TABLES;
    708        1.15       gwr 	kernCbase = pmap_bootstrap_alloc(size);
    709        1.71   tsutsui 	memset(kernCbase, 0, size);
    710         1.7       gwr 	/*
    711         1.7       gwr 	 * Note: In order for the PV system to work correctly, the kernel
    712         1.7       gwr 	 * and user-level C tables must be allocated contiguously.
    713         1.7       gwr 	 * Nothing should be allocated between here and the allocation of
    714         1.7       gwr 	 * mmuCbase below.  XXX: Should do this as one allocation, and
    715         1.7       gwr 	 * then compute a pointer for mmuCbase instead of this...
    716        1.15       gwr 	 *
    717       1.113   tsutsui 	 * Allocate user MMU tables.
    718        1.70       wiz 	 * These must be contiguous with the preceding.
    719         1.7       gwr 	 */
    720        1.22    jeremy 
    721        1.22    jeremy #ifndef	FIXED_NTABLES
    722        1.22    jeremy 	/*
    723        1.22    jeremy 	 * The number of user-level C tables that should be allocated is
    724        1.22    jeremy 	 * related to the size of physical memory.  In general, there should
    725        1.22    jeremy 	 * be enough tables to map four times the amount of available RAM.
    726        1.22    jeremy 	 * The extra amount is needed because some table space is wasted by
    727        1.22    jeremy 	 * fragmentation.
    728        1.22    jeremy 	 */
    729        1.22    jeremy 	NUM_C_TABLES = (total_phys_mem * 4) / (MMU_C_TBL_SIZE * MMU_PAGE_SIZE);
    730        1.22    jeremy 	NUM_B_TABLES = NUM_C_TABLES / 2;
    731        1.22    jeremy 	NUM_A_TABLES = NUM_B_TABLES / 2;
    732        1.22    jeremy #endif	/* !FIXED_NTABLES */
    733        1.22    jeremy 
    734        1.15       gwr 	size = sizeof(mmu_short_pte_t) * MMU_C_TBL_SIZE	* NUM_C_TABLES;
    735        1.15       gwr 	mmuCbase = pmap_bootstrap_alloc(size);
    736        1.15       gwr 
    737        1.15       gwr 	size = sizeof(mmu_short_dte_t) * MMU_B_TBL_SIZE	* NUM_B_TABLES;
    738        1.15       gwr 	mmuBbase = pmap_bootstrap_alloc(size);
    739         1.1       gwr 
    740        1.69       chs 	size = sizeof(mmu_long_dte_t) * MMU_A_TBL_SIZE * NUM_A_TABLES;
    741        1.15       gwr 	mmuAbase = pmap_bootstrap_alloc(size);
    742         1.7       gwr 
    743         1.7       gwr 	/*
    744         1.7       gwr 	 * Fill in the never-changing part of the kernel tables.
    745         1.7       gwr 	 * For simplicity, the kernel's mappings will be editable as a
    746         1.1       gwr 	 * flat array of page table entries at kernCbase.  The
    747         1.1       gwr 	 * higher level 'A' and 'B' tables must be initialized to point
    748       1.113   tsutsui 	 * to this lower one.
    749         1.1       gwr 	 */
    750         1.1       gwr 	b = c = 0;
    751         1.1       gwr 
    752         1.7       gwr 	/*
    753         1.7       gwr 	 * Invalidate all mappings below KERNBASE in the A table.
    754         1.1       gwr 	 * This area has already been zeroed out, but it is good
    755         1.1       gwr 	 * practice to explicitly show that we are interpreting
    756         1.1       gwr 	 * it as a list of A table descriptors.
    757         1.1       gwr 	 */
    758       1.111   tsutsui 	for (i = 0; i < MMU_TIA(KERNBASE3X); i++) {
    759         1.1       gwr 		kernAbase[i].addr.raw = 0;
    760         1.1       gwr 	}
    761         1.1       gwr 
    762         1.7       gwr 	/*
    763         1.7       gwr 	 * Set up the kernel A and B tables so that they will reference the
    764         1.1       gwr 	 * correct spots in the contiguous table of PTEs allocated for the
    765         1.1       gwr 	 * kernel's virtual memory space.
    766         1.1       gwr 	 */
    767       1.111   tsutsui 	for (i = MMU_TIA(KERNBASE3X); i < MMU_A_TBL_SIZE; i++) {
    768         1.1       gwr 		kernAbase[i].attr.raw =
    769        1.92   tsutsui 		    MMU_LONG_DTE_LU | MMU_LONG_DTE_SUPV | MMU_DT_SHORT;
    770         1.7       gwr 		kernAbase[i].addr.raw = mmu_vtop(&kernBbase[b]);
    771         1.1       gwr 
    772        1.92   tsutsui 		for (j = 0; j < MMU_B_TBL_SIZE; j++) {
    773        1.92   tsutsui 			kernBbase[b + j].attr.raw =
    774        1.92   tsutsui 			    mmu_vtop(&kernCbase[c]) | MMU_DT_SHORT;
    775         1.1       gwr 			c += MMU_C_TBL_SIZE;
    776         1.1       gwr 		}
    777         1.1       gwr 		b += MMU_B_TBL_SIZE;
    778         1.1       gwr 	}
    779         1.1       gwr 
    780         1.7       gwr 	pmap_alloc_usermmu();	/* Allocate user MMU tables.        */
    781         1.7       gwr 	pmap_alloc_usertmgr();	/* Allocate user MMU table managers.*/
    782         1.7       gwr 	pmap_alloc_pv();	/* Allocate physical->virtual map.  */
    783         1.7       gwr 
    784         1.7       gwr 	/*
    785         1.7       gwr 	 * We are now done with pmap_bootstrap_alloc().  Round up
    786         1.7       gwr 	 * `virtual_avail' to the nearest page, and set the flag
    787         1.7       gwr 	 * to prevent use of pmap_bootstrap_alloc() hereafter.
    788         1.7       gwr 	 */
    789        1.79   thorpej 	pmap_bootstrap_aalign(PAGE_SIZE);
    790        1.95   thorpej 	bootstrap_alloc_enabled = false;
    791         1.7       gwr 
    792         1.7       gwr 	/*
    793         1.7       gwr 	 * Now that we are done with pmap_bootstrap_alloc(), we
    794         1.7       gwr 	 * must save the virtual and physical addresses of the
    795         1.7       gwr 	 * end of the linearly mapped range, which are stored in
    796         1.7       gwr 	 * virtual_contig_end and avail_start, respectively.
    797         1.7       gwr 	 * These variables will never change after this point.
    798         1.7       gwr 	 */
    799         1.7       gwr 	virtual_contig_end = virtual_avail;
    800       1.111   tsutsui 	avail_start = virtual_avail - KERNBASE3X;
    801         1.7       gwr 
    802         1.7       gwr 	/*
    803         1.7       gwr 	 * `avail_next' is a running pointer used by pmap_next_page() to
    804         1.7       gwr 	 * keep track of the next available physical page to be handed
    805         1.7       gwr 	 * to the VM system during its initialization, in which it
    806         1.7       gwr 	 * asks for physical pages, one at a time.
    807         1.7       gwr 	 */
    808         1.7       gwr 	avail_next = avail_start;
    809         1.7       gwr 
    810         1.7       gwr 	/*
    811         1.7       gwr 	 * Now allocate some virtual addresses, but not the physical pages
    812         1.7       gwr 	 * behind them.  Note that virtual_avail is already page-aligned.
    813         1.7       gwr 	 *
    814         1.7       gwr 	 * tmp_vpages[] is an array of two virtual pages used for temporary
    815         1.7       gwr 	 * kernel mappings in the pmap module to facilitate various physical
    816         1.7       gwr 	 * address-oritented operations.
    817         1.7       gwr 	 */
    818         1.7       gwr 	tmp_vpages[0] = virtual_avail;
    819        1.79   thorpej 	virtual_avail += PAGE_SIZE;
    820         1.7       gwr 	tmp_vpages[1] = virtual_avail;
    821        1.79   thorpej 	virtual_avail += PAGE_SIZE;
    822         1.7       gwr 
    823         1.7       gwr 	/** Initialize the PV system **/
    824         1.7       gwr 	pmap_init_pv();
    825         1.7       gwr 
    826         1.7       gwr 	/*
    827         1.7       gwr 	 * Fill in the kernel_pmap structure and kernel_crp.
    828         1.7       gwr 	 */
    829         1.7       gwr 	kernAphys = mmu_vtop(kernAbase);
    830         1.7       gwr 	kernel_pmap.pm_a_tmgr = NULL;
    831         1.7       gwr 	kernel_pmap.pm_a_phys = kernAphys;
    832         1.7       gwr 	kernel_pmap.pm_refcount = 1; /* always in use */
    833         1.7       gwr 
    834         1.7       gwr 	kernel_crp.rp_attr = MMU_LONG_DTE_LU | MMU_DT_LONG;
    835         1.7       gwr 	kernel_crp.rp_addr = kernAphys;
    836         1.7       gwr 
    837         1.1       gwr 	/*
    838         1.1       gwr 	 * Now pmap_enter_kernel() may be used safely and will be
    839         1.7       gwr 	 * the main interface used hereafter to modify the kernel's
    840         1.7       gwr 	 * virtual address space.  Note that since we are still running
    841         1.7       gwr 	 * under the PROM's address table, none of these table modifications
    842         1.7       gwr 	 * actually take effect until pmap_takeover_mmu() is called.
    843         1.1       gwr 	 *
    844         1.7       gwr 	 * Note: Our tables do NOT have the PROM linear mappings!
    845         1.7       gwr 	 * Only the mappings created here exist in our tables, so
    846         1.7       gwr 	 * remember to map anything we expect to use.
    847         1.1       gwr 	 */
    848       1.111   tsutsui 	va = (vaddr_t)KERNBASE3X;
    849         1.7       gwr 	pa = 0;
    850         1.1       gwr 
    851         1.1       gwr 	/*
    852         1.7       gwr 	 * The first page of the kernel virtual address space is the msgbuf
    853         1.7       gwr 	 * page.  The page attributes (data, non-cached) are set here, while
    854         1.7       gwr 	 * the address is assigned to this global pointer in cpu_startup().
    855        1.29       gwr 	 * It is non-cached, mostly due to paranoia.
    856         1.1       gwr 	 */
    857        1.29       gwr 	pmap_enter_kernel(va, pa|PMAP_NC, VM_PROT_ALL);
    858        1.92   tsutsui 	va += PAGE_SIZE;
    859        1.92   tsutsui 	pa += PAGE_SIZE;
    860         1.1       gwr 
    861         1.7       gwr 	/* Next page is used as the temporary stack. */
    862         1.1       gwr 	pmap_enter_kernel(va, pa, VM_PROT_ALL);
    863        1.92   tsutsui 	va += PAGE_SIZE;
    864        1.92   tsutsui 	pa += PAGE_SIZE;
    865         1.1       gwr 
    866         1.1       gwr 	/*
    867         1.1       gwr 	 * Map all of the kernel's text segment as read-only and cacheable.
    868         1.1       gwr 	 * (Cacheable is implied by default).  Unfortunately, the last bytes
    869         1.1       gwr 	 * of kernel text and the first bytes of kernel data will often be
    870         1.1       gwr 	 * sharing the same page.  Therefore, the last page of kernel text
    871        1.93  christos 	 * has to be mapped as read/write, to accommodate the data.
    872         1.1       gwr 	 */
    873        1.69       chs 	eva = m68k_trunc_page((vaddr_t)etext);
    874        1.79   thorpej 	for (; va < eva; va += PAGE_SIZE, pa += PAGE_SIZE)
    875         1.1       gwr 		pmap_enter_kernel(va, pa, VM_PROT_READ|VM_PROT_EXECUTE);
    876         1.1       gwr 
    877         1.7       gwr 	/*
    878         1.7       gwr 	 * Map all of the kernel's data as read/write and cacheable.
    879         1.7       gwr 	 * This includes: data, BSS, symbols, and everything in the
    880         1.7       gwr 	 * contiguous memory used by pmap_bootstrap_alloc()
    881         1.1       gwr 	 */
    882        1.79   thorpej 	for (; pa < avail_start; va += PAGE_SIZE, pa += PAGE_SIZE)
    883         1.1       gwr 		pmap_enter_kernel(va, pa, VM_PROT_READ|VM_PROT_WRITE);
    884         1.1       gwr 
    885         1.7       gwr 	/*
    886         1.7       gwr 	 * At this point we are almost ready to take over the MMU.  But first
    887         1.7       gwr 	 * we must save the PROM's address space in our map, as we call its
    888         1.7       gwr 	 * routines and make references to its data later in the kernel.
    889         1.1       gwr 	 */
    890         1.7       gwr 	pmap_bootstrap_copyprom();
    891         1.7       gwr 	pmap_takeover_mmu();
    892        1.13       gwr 	pmap_bootstrap_setprom();
    893         1.1       gwr 
    894         1.1       gwr 	/* Notify the VM system of our page size. */
    895        1.79   thorpej 	uvmexp.pagesize = PAGE_SIZE;
    896  1.113.10.1  pgoyette 	uvm_md_init();
    897        1.37       gwr 
    898        1.37       gwr 	pmap_page_upload();
    899         1.1       gwr }
    900         1.1       gwr 
    901         1.1       gwr 
    902         1.1       gwr /* pmap_alloc_usermmu			INTERNAL
    903         1.1       gwr  **
    904         1.1       gwr  * Called from pmap_bootstrap() to allocate MMU tables that will
    905         1.1       gwr  * eventually be used for user mappings.
    906         1.1       gwr  */
    907       1.113   tsutsui void
    908        1.86       chs pmap_alloc_usermmu(void)
    909         1.1       gwr {
    910        1.92   tsutsui 
    911         1.7       gwr 	/* XXX: Moved into caller. */
    912         1.1       gwr }
    913         1.1       gwr 
    914         1.1       gwr /* pmap_alloc_pv			INTERNAL
    915         1.1       gwr  **
    916         1.1       gwr  * Called from pmap_bootstrap() to allocate the physical
    917         1.1       gwr  * to virtual mapping list.  Each physical page of memory
    918         1.1       gwr  * in the system has a corresponding element in this list.
    919         1.1       gwr  */
    920       1.113   tsutsui void
    921        1.86       chs pmap_alloc_pv(void)
    922         1.1       gwr {
    923         1.1       gwr 	int	i;
    924         1.1       gwr 	unsigned int	total_mem;
    925         1.1       gwr 
    926         1.7       gwr 	/*
    927         1.7       gwr 	 * Allocate a pv_head structure for every page of physical
    928         1.1       gwr 	 * memory that will be managed by the system.  Since memory on
    929         1.1       gwr 	 * the 3/80 is non-contiguous, we cannot arrive at a total page
    930         1.1       gwr 	 * count by subtraction of the lowest available address from the
    931         1.1       gwr 	 * highest, but rather we have to step through each memory
    932         1.1       gwr 	 * bank and add the number of pages in each to the total.
    933         1.1       gwr 	 *
    934         1.1       gwr 	 * At this time we also initialize the offset of each bank's
    935         1.1       gwr 	 * starting pv_head within the pv_head list so that the physical
    936         1.1       gwr 	 * memory state routines (pmap_is_referenced(),
    937         1.1       gwr 	 * pmap_is_modified(), et al.) can quickly find coresponding
    938         1.1       gwr 	 * pv_heads in spite of the non-contiguity.
    939         1.1       gwr 	 */
    940         1.1       gwr 	total_mem = 0;
    941        1.20   thorpej 	for (i = 0; i < SUN3X_NPHYS_RAM_SEGS; i++) {
    942        1.25     veego 		avail_mem[i].pmem_pvbase = m68k_btop(total_mem);
    943        1.92   tsutsui 		total_mem += avail_mem[i].pmem_end - avail_mem[i].pmem_start;
    944         1.1       gwr 		if (avail_mem[i].pmem_next == NULL)
    945         1.1       gwr 			break;
    946         1.1       gwr 	}
    947        1.92   tsutsui 	pvbase = (pv_t *)pmap_bootstrap_alloc(sizeof(pv_t) *
    948        1.92   tsutsui 	    m68k_btop(total_phys_mem));
    949         1.1       gwr }
    950         1.1       gwr 
    951         1.1       gwr /* pmap_alloc_usertmgr			INTERNAL
    952         1.1       gwr  **
    953         1.1       gwr  * Called from pmap_bootstrap() to allocate the structures which
    954         1.1       gwr  * facilitate management of user MMU tables.  Each user MMU table
    955         1.1       gwr  * in the system has one such structure associated with it.
    956         1.1       gwr  */
    957       1.113   tsutsui void
    958        1.86       chs pmap_alloc_usertmgr(void)
    959         1.1       gwr {
    960         1.1       gwr 	/* Allocate user MMU table managers */
    961         1.7       gwr 	/* It would be a lot simpler to just make these BSS, but */
    962         1.7       gwr 	/* we may want to change their size at boot time... -j */
    963        1.92   tsutsui 	Atmgrbase =
    964        1.92   tsutsui 	    (a_tmgr_t *)pmap_bootstrap_alloc(sizeof(a_tmgr_t) * NUM_A_TABLES);
    965        1.92   tsutsui 	Btmgrbase =
    966        1.92   tsutsui 	    (b_tmgr_t *)pmap_bootstrap_alloc(sizeof(b_tmgr_t) * NUM_B_TABLES);
    967        1.92   tsutsui 	Ctmgrbase =
    968        1.92   tsutsui 	    (c_tmgr_t *)pmap_bootstrap_alloc(sizeof(c_tmgr_t) * NUM_C_TABLES);
    969         1.1       gwr 
    970         1.7       gwr 	/*
    971         1.7       gwr 	 * Allocate PV list elements for the physical to virtual
    972         1.1       gwr 	 * mapping system.
    973         1.1       gwr 	 */
    974        1.92   tsutsui 	pvebase = (pv_elem_t *)pmap_bootstrap_alloc(sizeof(pv_elem_t) *
    975        1.92   tsutsui 	    (NUM_USER_PTES + NUM_KERN_PTES));
    976         1.1       gwr }
    977         1.1       gwr 
    978         1.1       gwr /* pmap_bootstrap_copyprom()			INTERNAL
    979         1.1       gwr  **
    980         1.1       gwr  * Copy the PROM mappings into our own tables.  Note, we
    981         1.1       gwr  * can use physical addresses until __bootstrap returns.
    982         1.1       gwr  */
    983       1.113   tsutsui void
    984        1.86       chs pmap_bootstrap_copyprom(void)
    985         1.1       gwr {
    986        1.33       gwr 	struct sunromvec *romp;
    987         1.1       gwr 	int *mon_ctbl;
    988         1.1       gwr 	mmu_short_pte_t *kpte;
    989         1.1       gwr 	int i, len;
    990         1.1       gwr 
    991         1.1       gwr 	romp = romVectorPtr;
    992         1.1       gwr 
    993         1.1       gwr 	/*
    994        1.33       gwr 	 * Copy the mappings in SUN3X_MON_KDB_BASE...SUN3X_MONEND
    995        1.33       gwr 	 * Note: mon_ctbl[0] maps SUN3X_MON_KDB_BASE
    996         1.1       gwr 	 */
    997         1.1       gwr 	mon_ctbl = *romp->monptaddr;
    998       1.111   tsutsui 	i = m68k_btop(SUN3X_MON_KDB_BASE - KERNBASE3X);
    999         1.1       gwr 	kpte = &kernCbase[i];
   1000        1.33       gwr 	len = m68k_btop(SUN3X_MONEND - SUN3X_MON_KDB_BASE);
   1001         1.1       gwr 
   1002         1.1       gwr 	for (i = 0; i < len; i++) {
   1003         1.1       gwr 		kpte[i].attr.raw = mon_ctbl[i];
   1004         1.1       gwr 	}
   1005         1.1       gwr 
   1006         1.1       gwr 	/*
   1007         1.1       gwr 	 * Copy the mappings at MON_DVMA_BASE (to the end).
   1008         1.1       gwr 	 * Note, in here, mon_ctbl[0] maps MON_DVMA_BASE.
   1009        1.32       gwr 	 * Actually, we only want the last page, which the
   1010        1.32       gwr 	 * PROM has set up for use by the "ie" driver.
   1011        1.32       gwr 	 * (The i82686 needs its SCP there.)
   1012        1.32       gwr 	 * If we copy all the mappings, pmap_enter_kernel
   1013        1.32       gwr 	 * may complain about finding valid PTEs that are
   1014        1.32       gwr 	 * not recorded in our PV lists...
   1015         1.1       gwr 	 */
   1016         1.1       gwr 	mon_ctbl = *romp->shadowpteaddr;
   1017       1.111   tsutsui 	i = m68k_btop(SUN3X_MON_DVMA_BASE - KERNBASE3X);
   1018         1.1       gwr 	kpte = &kernCbase[i];
   1019        1.33       gwr 	len = m68k_btop(SUN3X_MON_DVMA_SIZE);
   1020        1.92   tsutsui 	for (i = (len - 1); i < len; i++) {
   1021         1.1       gwr 		kpte[i].attr.raw = mon_ctbl[i];
   1022         1.1       gwr 	}
   1023         1.1       gwr }
   1024       1.113   tsutsui 
   1025         1.1       gwr /* pmap_takeover_mmu			INTERNAL
   1026         1.1       gwr  **
   1027         1.1       gwr  * Called from pmap_bootstrap() after it has copied enough of the
   1028         1.1       gwr  * PROM mappings into the kernel map so that we can use our own
   1029         1.1       gwr  * MMU table.
   1030         1.1       gwr  */
   1031       1.113   tsutsui void
   1032        1.86       chs pmap_takeover_mmu(void)
   1033         1.1       gwr {
   1034         1.1       gwr 
   1035        1.13       gwr 	loadcrp(&kernel_crp);
   1036         1.1       gwr }
   1037         1.1       gwr 
   1038        1.13       gwr /* pmap_bootstrap_setprom()			INTERNAL
   1039        1.13       gwr  **
   1040        1.13       gwr  * Set the PROM mappings so it can see kernel space.
   1041        1.13       gwr  * Note that physical addresses are used here, which
   1042        1.13       gwr  * we can get away with because this runs with the
   1043        1.13       gwr  * low 1GB set for transparent translation.
   1044        1.13       gwr  */
   1045       1.113   tsutsui void
   1046        1.86       chs pmap_bootstrap_setprom(void)
   1047        1.13       gwr {
   1048        1.13       gwr 	mmu_long_dte_t *mon_dte;
   1049        1.13       gwr 	extern struct mmu_rootptr mon_crp;
   1050        1.13       gwr 	int i;
   1051        1.13       gwr 
   1052        1.92   tsutsui 	mon_dte = (mmu_long_dte_t *)mon_crp.rp_addr;
   1053       1.111   tsutsui 	for (i = MMU_TIA(KERNBASE3X); i < MMU_TIA(KERN_END3X); i++) {
   1054        1.13       gwr 		mon_dte[i].attr.raw = kernAbase[i].attr.raw;
   1055        1.13       gwr 		mon_dte[i].addr.raw = kernAbase[i].addr.raw;
   1056        1.13       gwr 	}
   1057        1.13       gwr }
   1058        1.13       gwr 
   1059        1.13       gwr 
   1060         1.1       gwr /* pmap_init			INTERFACE
   1061         1.1       gwr  **
   1062         1.1       gwr  * Called at the end of vm_init() to set up the pmap system to go
   1063         1.7       gwr  * into full time operation.  All initialization of kernel_pmap
   1064         1.7       gwr  * should be already done by now, so this should just do things
   1065         1.7       gwr  * needed for user-level pmaps to work.
   1066         1.1       gwr  */
   1067       1.113   tsutsui void
   1068        1.86       chs pmap_init(void)
   1069         1.1       gwr {
   1070        1.92   tsutsui 
   1071         1.1       gwr 	/** Initialize the manager pools **/
   1072         1.1       gwr 	TAILQ_INIT(&a_pool);
   1073         1.1       gwr 	TAILQ_INIT(&b_pool);
   1074         1.1       gwr 	TAILQ_INIT(&c_pool);
   1075         1.1       gwr 
   1076         1.1       gwr 	/**************************************************************
   1077         1.1       gwr 	 * Initialize all tmgr structures and MMU tables they manage. *
   1078         1.1       gwr 	 **************************************************************/
   1079         1.1       gwr 	/** Initialize A tables **/
   1080         1.1       gwr 	pmap_init_a_tables();
   1081         1.1       gwr 	/** Initialize B tables **/
   1082         1.1       gwr 	pmap_init_b_tables();
   1083         1.1       gwr 	/** Initialize C tables **/
   1084         1.1       gwr 	pmap_init_c_tables();
   1085        1.56   tsutsui 
   1086        1.56   tsutsui 	/** Initialize the pmap pools **/
   1087        1.56   tsutsui 	pool_init(&pmap_pmap_pool, sizeof(struct pmap), 0, 0, 0, "pmappl",
   1088        1.96        ad 	    &pool_allocator_nointr, IPL_NONE);
   1089         1.1       gwr }
   1090         1.1       gwr 
   1091         1.1       gwr /* pmap_init_a_tables()			INTERNAL
   1092         1.1       gwr  **
   1093         1.1       gwr  * Initializes all A managers, their MMU A tables, and inserts
   1094         1.1       gwr  * them into the A manager pool for use by the system.
   1095         1.1       gwr  */
   1096       1.113   tsutsui void
   1097        1.86       chs pmap_init_a_tables(void)
   1098         1.1       gwr {
   1099         1.1       gwr 	int i;
   1100         1.1       gwr 	a_tmgr_t *a_tbl;
   1101         1.1       gwr 
   1102        1.86       chs 	for (i = 0; i < NUM_A_TABLES; i++) {
   1103         1.1       gwr 		/* Select the next available A manager from the pool */
   1104         1.1       gwr 		a_tbl = &Atmgrbase[i];
   1105         1.1       gwr 
   1106         1.7       gwr 		/*
   1107         1.7       gwr 		 * Clear its parent entry.  Set its wired and valid
   1108         1.1       gwr 		 * entry count to zero.
   1109         1.1       gwr 		 */
   1110         1.1       gwr 		a_tbl->at_parent = NULL;
   1111         1.1       gwr 		a_tbl->at_wcnt = a_tbl->at_ecnt = 0;
   1112         1.1       gwr 
   1113         1.1       gwr 		/* Assign it the next available MMU A table from the pool */
   1114         1.1       gwr 		a_tbl->at_dtbl = &mmuAbase[i * MMU_A_TBL_SIZE];
   1115         1.1       gwr 
   1116         1.7       gwr 		/*
   1117       1.110      matt 		 * Initialize the MMU A table with the table in the `lwp0',
   1118         1.1       gwr 		 * or kernel, mapping.  This ensures that every process has
   1119         1.1       gwr 		 * the kernel mapped in the top part of its address space.
   1120         1.1       gwr 		 */
   1121        1.92   tsutsui 		memcpy(a_tbl->at_dtbl, kernAbase,
   1122        1.92   tsutsui 		    MMU_A_TBL_SIZE * sizeof(mmu_long_dte_t));
   1123         1.1       gwr 
   1124         1.7       gwr 		/*
   1125         1.7       gwr 		 * Finally, insert the manager into the A pool,
   1126         1.1       gwr 		 * making it ready to be used by the system.
   1127         1.1       gwr 		 */
   1128         1.1       gwr 		TAILQ_INSERT_TAIL(&a_pool, a_tbl, at_link);
   1129       1.113   tsutsui 	}
   1130         1.1       gwr }
   1131         1.1       gwr 
   1132         1.1       gwr /* pmap_init_b_tables()			INTERNAL
   1133         1.1       gwr  **
   1134         1.1       gwr  * Initializes all B table managers, their MMU B tables, and
   1135         1.1       gwr  * inserts them into the B manager pool for use by the system.
   1136         1.1       gwr  */
   1137       1.113   tsutsui void
   1138        1.86       chs pmap_init_b_tables(void)
   1139         1.1       gwr {
   1140        1.86       chs 	int i, j;
   1141         1.1       gwr 	b_tmgr_t *b_tbl;
   1142         1.1       gwr 
   1143        1.86       chs 	for (i = 0; i < NUM_B_TABLES; i++) {
   1144         1.1       gwr 		/* Select the next available B manager from the pool */
   1145         1.1       gwr 		b_tbl = &Btmgrbase[i];
   1146         1.1       gwr 
   1147         1.1       gwr 		b_tbl->bt_parent = NULL;	/* clear its parent,  */
   1148         1.1       gwr 		b_tbl->bt_pidx = 0;		/* parent index,      */
   1149         1.1       gwr 		b_tbl->bt_wcnt = 0;		/* wired entry count, */
   1150         1.1       gwr 		b_tbl->bt_ecnt = 0;		/* valid entry count. */
   1151         1.1       gwr 
   1152         1.1       gwr 		/* Assign it the next available MMU B table from the pool */
   1153         1.1       gwr 		b_tbl->bt_dtbl = &mmuBbase[i * MMU_B_TBL_SIZE];
   1154         1.1       gwr 
   1155         1.1       gwr 		/* Invalidate every descriptor in the table */
   1156        1.92   tsutsui 		for (j = 0; j < MMU_B_TBL_SIZE; j++)
   1157         1.1       gwr 			b_tbl->bt_dtbl[j].attr.raw = MMU_DT_INVALID;
   1158         1.1       gwr 
   1159         1.1       gwr 		/* Insert the manager into the B pool */
   1160         1.1       gwr 		TAILQ_INSERT_TAIL(&b_pool, b_tbl, bt_link);
   1161         1.1       gwr 	}
   1162         1.1       gwr }
   1163         1.1       gwr 
   1164         1.1       gwr /* pmap_init_c_tables()			INTERNAL
   1165         1.1       gwr  **
   1166         1.1       gwr  * Initializes all C table managers, their MMU C tables, and
   1167         1.1       gwr  * inserts them into the C manager pool for use by the system.
   1168         1.1       gwr  */
   1169       1.113   tsutsui void
   1170        1.86       chs pmap_init_c_tables(void)
   1171         1.1       gwr {
   1172        1.86       chs 	int i, j;
   1173         1.1       gwr 	c_tmgr_t *c_tbl;
   1174         1.1       gwr 
   1175        1.86       chs 	for (i = 0; i < NUM_C_TABLES; i++) {
   1176         1.1       gwr 		/* Select the next available C manager from the pool */
   1177         1.1       gwr 		c_tbl = &Ctmgrbase[i];
   1178         1.1       gwr 
   1179         1.1       gwr 		c_tbl->ct_parent = NULL;	/* clear its parent,  */
   1180         1.1       gwr 		c_tbl->ct_pidx = 0;		/* parent index,      */
   1181         1.1       gwr 		c_tbl->ct_wcnt = 0;		/* wired entry count, */
   1182        1.26    jeremy 		c_tbl->ct_ecnt = 0;		/* valid entry count, */
   1183        1.26    jeremy 		c_tbl->ct_pmap = NULL;		/* parent pmap,       */
   1184        1.26    jeremy 		c_tbl->ct_va = 0;		/* base of managed range */
   1185         1.1       gwr 
   1186       1.113   tsutsui 		/* Assign it the next available MMU C table from the pool */
   1187         1.1       gwr 		c_tbl->ct_dtbl = &mmuCbase[i * MMU_C_TBL_SIZE];
   1188         1.1       gwr 
   1189        1.92   tsutsui 		for (j = 0; j < MMU_C_TBL_SIZE; j++)
   1190         1.1       gwr 			c_tbl->ct_dtbl[j].attr.raw = MMU_DT_INVALID;
   1191         1.1       gwr 
   1192         1.1       gwr 		TAILQ_INSERT_TAIL(&c_pool, c_tbl, ct_link);
   1193         1.1       gwr 	}
   1194         1.1       gwr }
   1195         1.1       gwr 
   1196         1.1       gwr /* pmap_init_pv()			INTERNAL
   1197         1.1       gwr  **
   1198         1.1       gwr  * Initializes the Physical to Virtual mapping system.
   1199         1.1       gwr  */
   1200       1.113   tsutsui void
   1201        1.86       chs pmap_init_pv(void)
   1202         1.1       gwr {
   1203        1.86       chs 	int i;
   1204         1.7       gwr 
   1205         1.7       gwr 	/* Initialize every PV head. */
   1206        1.25     veego 	for (i = 0; i < m68k_btop(total_phys_mem); i++) {
   1207         1.7       gwr 		pvbase[i].pv_idx = PVE_EOL;	/* Indicate no mappings */
   1208         1.7       gwr 		pvbase[i].pv_flags = 0;		/* Zero out page flags  */
   1209         1.7       gwr 	}
   1210         1.1       gwr }
   1211         1.1       gwr 
   1212        1.92   tsutsui /* is_managed				INTERNAL
   1213        1.92   tsutsui  **
   1214        1.92   tsutsui  * Determine if the given physical address is managed by the PV system.
   1215        1.92   tsutsui  * Note that this logic assumes that no one will ask for the status of
   1216        1.92   tsutsui  * addresses which lie in-between the memory banks on the 3/80.  If they
   1217        1.92   tsutsui  * do so, it will falsely report that it is managed.
   1218        1.92   tsutsui  *
   1219       1.113   tsutsui  * Note: A "managed" address is one that was reported to the VM system as
   1220        1.92   tsutsui  * a "usable page" during system startup.  As such, the VM system expects the
   1221        1.92   tsutsui  * pmap module to keep an accurate track of the useage of those pages.
   1222       1.113   tsutsui  * Any page not given to the VM system at startup does not exist (as far as
   1223        1.92   tsutsui  * the VM system is concerned) and is therefore "unmanaged."  Examples are
   1224        1.92   tsutsui  * those pages which belong to the ROM monitor and the memory allocated before
   1225        1.92   tsutsui  * the VM system was started.
   1226        1.92   tsutsui  */
   1227       1.113   tsutsui static INLINE bool
   1228        1.92   tsutsui is_managed(paddr_t pa)
   1229        1.92   tsutsui {
   1230        1.92   tsutsui 	if (pa >= avail_start && pa < avail_end)
   1231        1.95   thorpej 		return true;
   1232        1.92   tsutsui 	else
   1233        1.95   thorpej 		return false;
   1234        1.92   tsutsui }
   1235        1.92   tsutsui 
   1236         1.1       gwr /* get_a_table			INTERNAL
   1237         1.1       gwr  **
   1238         1.1       gwr  * Retrieve and return a level A table for use in a user map.
   1239         1.1       gwr  */
   1240         1.1       gwr a_tmgr_t *
   1241        1.86       chs get_a_table(void)
   1242         1.1       gwr {
   1243         1.1       gwr 	a_tmgr_t *tbl;
   1244         1.7       gwr 	pmap_t pmap;
   1245         1.1       gwr 
   1246         1.1       gwr 	/* Get the top A table in the pool */
   1247        1.86       chs 	tbl = TAILQ_FIRST(&a_pool);
   1248         1.7       gwr 	if (tbl == NULL) {
   1249         1.7       gwr 		/*
   1250        1.85       wiz 		 * XXX - Instead of panicking here and in other get_x_table
   1251         1.7       gwr 		 * functions, we do have the option of sleeping on the head of
   1252         1.7       gwr 		 * the table pool.  Any function which updates the table pool
   1253         1.7       gwr 		 * would then issue a wakeup() on the head, thus waking up any
   1254         1.7       gwr 		 * processes waiting for a table.
   1255         1.7       gwr 		 *
   1256         1.7       gwr 		 * Actually, the place to sleep would be when some process
   1257         1.7       gwr 		 * asks for a "wired" mapping that would run us short of
   1258         1.7       gwr 		 * mapping resources.  This design DEPENDS on always having
   1259         1.7       gwr 		 * some mapping resources in the pool for stealing, so we
   1260         1.7       gwr 		 * must make sure we NEVER let the pool become empty. -gwr
   1261         1.7       gwr 		 */
   1262         1.1       gwr 		panic("get_a_table: out of A tables.");
   1263         1.7       gwr 	}
   1264         1.7       gwr 
   1265         1.1       gwr 	TAILQ_REMOVE(&a_pool, tbl, at_link);
   1266         1.7       gwr 	/*
   1267         1.7       gwr 	 * If the table has a non-null parent pointer then it is in use.
   1268         1.1       gwr 	 * Forcibly abduct it from its parent and clear its entries.
   1269         1.1       gwr 	 * No re-entrancy worries here.  This table would not be in the
   1270         1.1       gwr 	 * table pool unless it was available for use.
   1271         1.7       gwr 	 *
   1272        1.95   thorpej 	 * Note that the second argument to free_a_table() is false.  This
   1273         1.7       gwr 	 * indicates that the table should not be relinked into the A table
   1274         1.7       gwr 	 * pool.  That is a job for the function that called us.
   1275         1.1       gwr 	 */
   1276         1.1       gwr 	if (tbl->at_parent) {
   1277        1.91   tsutsui 		KASSERT(tbl->at_wcnt == 0);
   1278         1.7       gwr 		pmap = tbl->at_parent;
   1279        1.95   thorpej 		free_a_table(tbl, false);
   1280         1.7       gwr 		pmap->pm_a_tmgr = NULL;
   1281         1.7       gwr 		pmap->pm_a_phys = kernAphys;
   1282         1.1       gwr 	}
   1283         1.1       gwr 	return tbl;
   1284         1.1       gwr }
   1285         1.1       gwr 
   1286         1.1       gwr /* get_b_table			INTERNAL
   1287         1.1       gwr  **
   1288         1.1       gwr  * Return a level B table for use.
   1289         1.1       gwr  */
   1290         1.1       gwr b_tmgr_t *
   1291        1.86       chs get_b_table(void)
   1292         1.1       gwr {
   1293         1.1       gwr 	b_tmgr_t *tbl;
   1294         1.1       gwr 
   1295         1.1       gwr 	/* See 'get_a_table' for comments. */
   1296        1.86       chs 	tbl = TAILQ_FIRST(&b_pool);
   1297         1.1       gwr 	if (tbl == NULL)
   1298         1.1       gwr 		panic("get_b_table: out of B tables.");
   1299         1.1       gwr 	TAILQ_REMOVE(&b_pool, tbl, bt_link);
   1300         1.1       gwr 	if (tbl->bt_parent) {
   1301        1.91   tsutsui 		KASSERT(tbl->bt_wcnt == 0);
   1302         1.1       gwr 		tbl->bt_parent->at_dtbl[tbl->bt_pidx].attr.raw = MMU_DT_INVALID;
   1303         1.1       gwr 		tbl->bt_parent->at_ecnt--;
   1304        1.95   thorpej 		free_b_table(tbl, false);
   1305         1.1       gwr 	}
   1306         1.1       gwr 	return tbl;
   1307         1.1       gwr }
   1308         1.1       gwr 
   1309         1.1       gwr /* get_c_table			INTERNAL
   1310         1.1       gwr  **
   1311         1.1       gwr  * Return a level C table for use.
   1312         1.1       gwr  */
   1313         1.1       gwr c_tmgr_t *
   1314        1.86       chs get_c_table(void)
   1315         1.1       gwr {
   1316         1.1       gwr 	c_tmgr_t *tbl;
   1317         1.1       gwr 
   1318         1.1       gwr 	/* See 'get_a_table' for comments */
   1319        1.86       chs 	tbl = TAILQ_FIRST(&c_pool);
   1320         1.1       gwr 	if (tbl == NULL)
   1321         1.1       gwr 		panic("get_c_table: out of C tables.");
   1322         1.1       gwr 	TAILQ_REMOVE(&c_pool, tbl, ct_link);
   1323         1.1       gwr 	if (tbl->ct_parent) {
   1324        1.91   tsutsui 		KASSERT(tbl->ct_wcnt == 0);
   1325         1.1       gwr 		tbl->ct_parent->bt_dtbl[tbl->ct_pidx].attr.raw = MMU_DT_INVALID;
   1326         1.1       gwr 		tbl->ct_parent->bt_ecnt--;
   1327        1.95   thorpej 		free_c_table(tbl, false);
   1328         1.1       gwr 	}
   1329         1.1       gwr 	return tbl;
   1330         1.1       gwr }
   1331         1.1       gwr 
   1332         1.7       gwr /*
   1333         1.7       gwr  * The following 'free_table' and 'steal_table' functions are called to
   1334         1.1       gwr  * detach tables from their current obligations (parents and children) and
   1335         1.1       gwr  * prepare them for reuse in another mapping.
   1336         1.1       gwr  *
   1337         1.1       gwr  * Free_table is used when the calling function will handle the fate
   1338         1.1       gwr  * of the parent table, such as returning it to the free pool when it has
   1339         1.1       gwr  * no valid entries.  Functions that do not want to handle this should
   1340         1.1       gwr  * call steal_table, in which the parent table's descriptors and entry
   1341         1.1       gwr  * count are automatically modified when this table is removed.
   1342         1.1       gwr  */
   1343         1.1       gwr 
   1344         1.1       gwr /* free_a_table			INTERNAL
   1345         1.1       gwr  **
   1346         1.1       gwr  * Unmaps the given A table and all child tables from their current
   1347         1.1       gwr  * mappings.  Returns the number of pages that were invalidated.
   1348         1.7       gwr  * If 'relink' is true, the function will return the table to the head
   1349         1.7       gwr  * of the available table pool.
   1350         1.1       gwr  *
   1351         1.1       gwr  * Cache note: The MC68851 will automatically flush all
   1352         1.1       gwr  * descriptors derived from a given A table from its
   1353         1.1       gwr  * Automatic Translation Cache (ATC) if we issue a
   1354         1.1       gwr  * 'PFLUSHR' instruction with the base address of the
   1355         1.1       gwr  * table.  This function should do, and does so.
   1356         1.1       gwr  * Note note: We are using an MC68030 - there is no
   1357         1.1       gwr  * PFLUSHR.
   1358         1.1       gwr  */
   1359       1.113   tsutsui int
   1360        1.94   thorpej free_a_table(a_tmgr_t *a_tbl, bool relink)
   1361         1.1       gwr {
   1362         1.1       gwr 	int i, removed_cnt;
   1363         1.1       gwr 	mmu_long_dte_t	*dte;
   1364         1.1       gwr 	mmu_short_dte_t *dtbl;
   1365        1.91   tsutsui 	b_tmgr_t	*b_tbl;
   1366        1.91   tsutsui 	uint8_t at_wired, bt_wired;
   1367         1.1       gwr 
   1368         1.7       gwr 	/*
   1369         1.7       gwr 	 * Flush the ATC cache of all cached descriptors derived
   1370         1.1       gwr 	 * from this table.
   1371        1.22    jeremy 	 * Sun3x does not use 68851's cached table feature
   1372         1.1       gwr 	 * flush_atc_crp(mmu_vtop(a_tbl->dte));
   1373         1.1       gwr 	 */
   1374         1.1       gwr 
   1375         1.7       gwr 	/*
   1376         1.7       gwr 	 * Remove any pending cache flushes that were designated
   1377         1.1       gwr 	 * for the pmap this A table belongs to.
   1378         1.1       gwr 	 * a_tbl->parent->atc_flushq[0] = 0;
   1379        1.22    jeremy 	 * Not implemented in sun3x.
   1380         1.1       gwr 	 */
   1381         1.1       gwr 
   1382         1.7       gwr 	/*
   1383         1.7       gwr 	 * All A tables in the system should retain a map for the
   1384         1.1       gwr 	 * kernel. If the table contains any valid descriptors
   1385         1.1       gwr 	 * (other than those for the kernel area), invalidate them all,
   1386         1.1       gwr 	 * stopping short of the kernel's entries.
   1387         1.1       gwr 	 */
   1388         1.1       gwr 	removed_cnt = 0;
   1389        1.91   tsutsui 	at_wired = a_tbl->at_wcnt;
   1390         1.1       gwr 	if (a_tbl->at_ecnt) {
   1391         1.1       gwr 		dte = a_tbl->at_dtbl;
   1392       1.111   tsutsui 		for (i = 0; i < MMU_TIA(KERNBASE3X); i++) {
   1393         1.7       gwr 			/*
   1394         1.7       gwr 			 * If a table entry points to a valid B table, free
   1395         1.1       gwr 			 * it and its children.
   1396         1.1       gwr 			 */
   1397         1.1       gwr 			if (MMU_VALID_DT(dte[i])) {
   1398         1.7       gwr 				/*
   1399         1.7       gwr 				 * The following block does several things,
   1400         1.1       gwr 				 * from innermost expression to the
   1401         1.1       gwr 				 * outermost:
   1402         1.1       gwr 				 * 1) It extracts the base (cc 1996)
   1403         1.1       gwr 				 *    address of the B table pointed
   1404         1.1       gwr 				 *    to in the A table entry dte[i].
   1405         1.1       gwr 				 * 2) It converts this base address into
   1406         1.1       gwr 				 *    the virtual address it can be
   1407         1.1       gwr 				 *    accessed with. (all MMU tables point
   1408         1.1       gwr 				 *    to physical addresses.)
   1409         1.1       gwr 				 * 3) It finds the corresponding manager
   1410         1.1       gwr 				 *    structure which manages this MMU table.
   1411         1.1       gwr 				 * 4) It frees the manager structure.
   1412         1.1       gwr 				 *    (This frees the MMU table and all
   1413         1.1       gwr 				 *    child tables. See 'free_b_table' for
   1414         1.1       gwr 				 *    details.)
   1415         1.1       gwr 				 */
   1416         1.7       gwr 				dtbl = mmu_ptov(dte[i].addr.raw);
   1417        1.91   tsutsui 				b_tbl = mmuB2tmgr(dtbl);
   1418        1.91   tsutsui 				bt_wired = b_tbl->bt_wcnt;
   1419        1.95   thorpej 				removed_cnt += free_b_table(b_tbl, true);
   1420        1.91   tsutsui 				if (bt_wired)
   1421        1.91   tsutsui 					a_tbl->at_wcnt--;
   1422         1.8       gwr 				dte[i].attr.raw = MMU_DT_INVALID;
   1423         1.1       gwr 			}
   1424         1.8       gwr 		}
   1425         1.8       gwr 		a_tbl->at_ecnt = 0;
   1426         1.1       gwr 	}
   1427        1.91   tsutsui 	KASSERT(a_tbl->at_wcnt == 0);
   1428        1.91   tsutsui 
   1429         1.7       gwr 	if (relink) {
   1430         1.7       gwr 		a_tbl->at_parent = NULL;
   1431        1.91   tsutsui 		if (!at_wired)
   1432        1.91   tsutsui 			TAILQ_REMOVE(&a_pool, a_tbl, at_link);
   1433         1.7       gwr 		TAILQ_INSERT_HEAD(&a_pool, a_tbl, at_link);
   1434         1.7       gwr 	}
   1435         1.1       gwr 	return removed_cnt;
   1436         1.1       gwr }
   1437         1.1       gwr 
   1438         1.1       gwr /* free_b_table			INTERNAL
   1439         1.1       gwr  **
   1440         1.1       gwr  * Unmaps the given B table and all its children from their current
   1441         1.1       gwr  * mappings.  Returns the number of pages that were invalidated.
   1442         1.1       gwr  * (For comments, see 'free_a_table()').
   1443         1.1       gwr  */
   1444       1.113   tsutsui int
   1445        1.94   thorpej free_b_table(b_tmgr_t *b_tbl, bool relink)
   1446         1.1       gwr {
   1447         1.1       gwr 	int i, removed_cnt;
   1448         1.1       gwr 	mmu_short_dte_t *dte;
   1449         1.1       gwr 	mmu_short_pte_t	*dtbl;
   1450        1.91   tsutsui 	c_tmgr_t	*c_tbl;
   1451        1.91   tsutsui 	uint8_t bt_wired, ct_wired;
   1452         1.1       gwr 
   1453         1.1       gwr 	removed_cnt = 0;
   1454        1.91   tsutsui 	bt_wired = b_tbl->bt_wcnt;
   1455         1.1       gwr 	if (b_tbl->bt_ecnt) {
   1456         1.1       gwr 		dte = b_tbl->bt_dtbl;
   1457        1.92   tsutsui 		for (i = 0; i < MMU_B_TBL_SIZE; i++) {
   1458         1.1       gwr 			if (MMU_VALID_DT(dte[i])) {
   1459         1.7       gwr 				dtbl = mmu_ptov(MMU_DTE_PA(dte[i]));
   1460        1.91   tsutsui 				c_tbl = mmuC2tmgr(dtbl);
   1461        1.91   tsutsui 				ct_wired = c_tbl->ct_wcnt;
   1462        1.95   thorpej 				removed_cnt += free_c_table(c_tbl, true);
   1463        1.91   tsutsui 				if (ct_wired)
   1464        1.91   tsutsui 					b_tbl->bt_wcnt--;
   1465         1.8       gwr 				dte[i].attr.raw = MMU_DT_INVALID;
   1466         1.1       gwr 			}
   1467         1.8       gwr 		}
   1468         1.8       gwr 		b_tbl->bt_ecnt = 0;
   1469         1.1       gwr 	}
   1470        1.91   tsutsui 	KASSERT(b_tbl->bt_wcnt == 0);
   1471         1.1       gwr 
   1472         1.7       gwr 	if (relink) {
   1473         1.7       gwr 		b_tbl->bt_parent = NULL;
   1474        1.91   tsutsui 		if (!bt_wired)
   1475        1.91   tsutsui 			TAILQ_REMOVE(&b_pool, b_tbl, bt_link);
   1476         1.7       gwr 		TAILQ_INSERT_HEAD(&b_pool, b_tbl, bt_link);
   1477         1.7       gwr 	}
   1478         1.1       gwr 	return removed_cnt;
   1479         1.1       gwr }
   1480         1.1       gwr 
   1481         1.1       gwr /* free_c_table			INTERNAL
   1482         1.1       gwr  **
   1483         1.1       gwr  * Unmaps the given C table from use and returns it to the pool for
   1484         1.1       gwr  * re-use.  Returns the number of pages that were invalidated.
   1485         1.1       gwr  *
   1486       1.113   tsutsui  * This function preserves any physical page modification information
   1487         1.1       gwr  * contained in the page descriptors within the C table by calling
   1488         1.1       gwr  * 'pmap_remove_pte().'
   1489         1.1       gwr  */
   1490       1.113   tsutsui int
   1491        1.94   thorpej free_c_table(c_tmgr_t *c_tbl, bool relink)
   1492         1.1       gwr {
   1493        1.91   tsutsui 	mmu_short_pte_t *c_pte;
   1494         1.1       gwr 	int i, removed_cnt;
   1495        1.91   tsutsui 	uint8_t ct_wired;
   1496         1.1       gwr 
   1497         1.1       gwr 	removed_cnt = 0;
   1498        1.91   tsutsui 	ct_wired = c_tbl->ct_wcnt;
   1499         1.8       gwr 	if (c_tbl->ct_ecnt) {
   1500        1.92   tsutsui 		for (i = 0; i < MMU_C_TBL_SIZE; i++) {
   1501        1.91   tsutsui 			c_pte = &c_tbl->ct_dtbl[i];
   1502        1.91   tsutsui 			if (MMU_VALID_DT(*c_pte)) {
   1503        1.91   tsutsui 				if (c_pte->attr.raw & MMU_SHORT_PTE_WIRED)
   1504        1.91   tsutsui 					c_tbl->ct_wcnt--;
   1505        1.91   tsutsui 				pmap_remove_pte(c_pte);
   1506         1.1       gwr 				removed_cnt++;
   1507         1.1       gwr 			}
   1508         1.8       gwr 		}
   1509         1.8       gwr 		c_tbl->ct_ecnt = 0;
   1510         1.8       gwr 	}
   1511        1.91   tsutsui 	KASSERT(c_tbl->ct_wcnt == 0);
   1512         1.8       gwr 
   1513         1.7       gwr 	if (relink) {
   1514         1.7       gwr 		c_tbl->ct_parent = NULL;
   1515        1.91   tsutsui 		if (!ct_wired)
   1516        1.91   tsutsui 			TAILQ_REMOVE(&c_pool, c_tbl, ct_link);
   1517         1.7       gwr 		TAILQ_INSERT_HEAD(&c_pool, c_tbl, ct_link);
   1518         1.7       gwr 	}
   1519         1.1       gwr 	return removed_cnt;
   1520         1.1       gwr }
   1521         1.1       gwr 
   1522         1.1       gwr 
   1523         1.1       gwr /* pmap_remove_pte			INTERNAL
   1524         1.1       gwr  **
   1525         1.1       gwr  * Unmap the given pte and preserve any page modification
   1526         1.1       gwr  * information by transfering it to the pv head of the
   1527         1.1       gwr  * physical page it maps to.  This function does not update
   1528         1.1       gwr  * any reference counts because it is assumed that the calling
   1529         1.8       gwr  * function will do so.
   1530         1.1       gwr  */
   1531         1.1       gwr void
   1532        1.86       chs pmap_remove_pte(mmu_short_pte_t *pte)
   1533         1.1       gwr {
   1534         1.7       gwr 	u_short     pv_idx, targ_idx;
   1535        1.69       chs 	paddr_t     pa;
   1536         1.1       gwr 	pv_t       *pv;
   1537         1.1       gwr 
   1538         1.1       gwr 	pa = MMU_PTE_PA(*pte);
   1539         1.1       gwr 	if (is_managed(pa)) {
   1540         1.1       gwr 		pv = pa2pv(pa);
   1541         1.7       gwr 		targ_idx = pteidx(pte);	/* Index of PTE being removed    */
   1542         1.7       gwr 
   1543         1.7       gwr 		/*
   1544         1.7       gwr 		 * If the PTE being removed is the first (or only) PTE in
   1545         1.7       gwr 		 * the list of PTEs currently mapped to this page, remove the
   1546         1.7       gwr 		 * PTE by changing the index found on the PV head.  Otherwise
   1547       1.113   tsutsui 		 * a linear search through the list will have to be executed
   1548         1.7       gwr 		 * in order to find the PVE which points to the PTE being
   1549         1.7       gwr 		 * removed, so that it may be modified to point to its new
   1550         1.7       gwr 		 * neighbor.
   1551         1.7       gwr 		 */
   1552        1.69       chs 
   1553         1.7       gwr 		pv_idx = pv->pv_idx;	/* Index of first PTE in PV list */
   1554         1.7       gwr 		if (pv_idx == targ_idx) {
   1555         1.7       gwr 			pv->pv_idx = pvebase[targ_idx].pve_next;
   1556         1.7       gwr 		} else {
   1557        1.69       chs 
   1558         1.7       gwr 			/*
   1559        1.32       gwr 			 * Find the PV element pointing to the target
   1560        1.32       gwr 			 * element.  Note: may have pv_idx==PVE_EOL
   1561         1.7       gwr 			 */
   1562        1.69       chs 
   1563        1.32       gwr 			for (;;) {
   1564        1.32       gwr 				if (pv_idx == PVE_EOL) {
   1565        1.32       gwr 					goto pv_not_found;
   1566        1.32       gwr 				}
   1567        1.32       gwr 				if (pvebase[pv_idx].pve_next == targ_idx)
   1568        1.32       gwr 					break;
   1569         1.7       gwr 				pv_idx = pvebase[pv_idx].pve_next;
   1570         1.7       gwr 			}
   1571        1.69       chs 
   1572         1.7       gwr 			/*
   1573         1.7       gwr 			 * At this point, pv_idx is the index of the PV
   1574         1.7       gwr 			 * element just before the target element in the list.
   1575         1.7       gwr 			 * Unlink the target.
   1576         1.7       gwr 			 */
   1577        1.69       chs 
   1578         1.7       gwr 			pvebase[pv_idx].pve_next = pvebase[targ_idx].pve_next;
   1579         1.7       gwr 		}
   1580        1.69       chs 
   1581         1.7       gwr 		/*
   1582         1.7       gwr 		 * Save the mod/ref bits of the pte by simply
   1583         1.1       gwr 		 * ORing the entire pte onto the pv_flags member
   1584         1.1       gwr 		 * of the pv structure.
   1585         1.1       gwr 		 * There is no need to use a separate bit pattern
   1586         1.1       gwr 		 * for usage information on the pv head than that
   1587         1.1       gwr 		 * which is used on the MMU ptes.
   1588         1.1       gwr 		 */
   1589        1.69       chs 
   1590        1.92   tsutsui  pv_not_found:
   1591         1.7       gwr 		pv->pv_flags |= (u_short) pte->attr.raw;
   1592         1.1       gwr 	}
   1593         1.1       gwr 	pte->attr.raw = MMU_DT_INVALID;
   1594         1.1       gwr }
   1595         1.1       gwr 
   1596         1.1       gwr /* pmap_stroll			INTERNAL
   1597         1.1       gwr  **
   1598         1.1       gwr  * Retrieve the addresses of all table managers involved in the mapping of
   1599        1.77       wiz  * the given virtual address.  If the table walk completed successfully,
   1600        1.95   thorpej  * return true.  If it was only partially successful, return false.
   1601         1.1       gwr  * The table walk performed by this function is important to many other
   1602         1.1       gwr  * functions in this module.
   1603         1.7       gwr  *
   1604         1.7       gwr  * Note: This function ought to be easier to read.
   1605         1.1       gwr  */
   1606        1.94   thorpej bool
   1607        1.86       chs pmap_stroll(pmap_t pmap, vaddr_t va, a_tmgr_t **a_tbl, b_tmgr_t **b_tbl,
   1608        1.86       chs     c_tmgr_t **c_tbl, mmu_short_pte_t **pte, int *a_idx, int *b_idx,
   1609        1.86       chs     int *pte_idx)
   1610         1.1       gwr {
   1611         1.1       gwr 	mmu_long_dte_t *a_dte;   /* A: long descriptor table          */
   1612         1.1       gwr 	mmu_short_dte_t *b_dte;  /* B: short descriptor table         */
   1613         1.1       gwr 
   1614         1.1       gwr 	if (pmap == pmap_kernel())
   1615        1.95   thorpej 		return false;
   1616         1.1       gwr 
   1617         1.7       gwr 	/* Does the given pmap have its own A table? */
   1618         1.7       gwr 	*a_tbl = pmap->pm_a_tmgr;
   1619         1.1       gwr 	if (*a_tbl == NULL)
   1620        1.95   thorpej 		return false; /* No.  Return unknown. */
   1621         1.1       gwr 	/* Does the A table have a valid B table
   1622         1.1       gwr 	 * under the corresponding table entry?
   1623         1.1       gwr 	 */
   1624         1.1       gwr 	*a_idx = MMU_TIA(va);
   1625         1.1       gwr 	a_dte = &((*a_tbl)->at_dtbl[*a_idx]);
   1626         1.1       gwr 	if (!MMU_VALID_DT(*a_dte))
   1627        1.95   thorpej 		return false; /* No. Return unknown. */
   1628         1.1       gwr 	/* Yes. Extract B table from the A table. */
   1629         1.7       gwr 	*b_tbl = mmuB2tmgr(mmu_ptov(a_dte->addr.raw));
   1630        1.92   tsutsui 	/*
   1631        1.92   tsutsui 	 * Does the B table have a valid C table
   1632         1.1       gwr 	 * under the corresponding table entry?
   1633         1.1       gwr 	 */
   1634         1.1       gwr 	*b_idx = MMU_TIB(va);
   1635         1.1       gwr 	b_dte = &((*b_tbl)->bt_dtbl[*b_idx]);
   1636         1.1       gwr 	if (!MMU_VALID_DT(*b_dte))
   1637        1.95   thorpej 		return false; /* No. Return unknown. */
   1638         1.1       gwr 	/* Yes. Extract C table from the B table. */
   1639         1.7       gwr 	*c_tbl = mmuC2tmgr(mmu_ptov(MMU_DTE_PA(*b_dte)));
   1640         1.1       gwr 	*pte_idx = MMU_TIC(va);
   1641         1.1       gwr 	*pte = &((*c_tbl)->ct_dtbl[*pte_idx]);
   1642       1.113   tsutsui 
   1643        1.95   thorpej 	return true;
   1644         1.1       gwr }
   1645       1.113   tsutsui 
   1646         1.1       gwr /* pmap_enter			INTERFACE
   1647         1.1       gwr  **
   1648         1.1       gwr  * Called by the kernel to map a virtual address
   1649       1.113   tsutsui  * to a physical address in the given process map.
   1650         1.1       gwr  *
   1651         1.1       gwr  * Note: this function should apply an exclusive lock
   1652         1.1       gwr  * on the pmap system for its duration.  (it certainly
   1653         1.1       gwr  * would save my hair!!)
   1654         1.7       gwr  * This function ought to be easier to read.
   1655         1.1       gwr  */
   1656       1.113   tsutsui int
   1657       1.104    cegger pmap_enter(pmap_t pmap, vaddr_t va, paddr_t pa, vm_prot_t prot, u_int flags)
   1658         1.1       gwr {
   1659        1.94   thorpej 	bool insert, managed; /* Marks the need for PV insertion.*/
   1660         1.7       gwr 	u_short nidx;            /* PV list index                     */
   1661        1.52    jeremy 	int mapflags;            /* Flags for the mapping (see NOTE1) */
   1662         1.8       gwr 	u_int a_idx, b_idx, pte_idx; /* table indices                 */
   1663         1.1       gwr 	a_tmgr_t *a_tbl;         /* A: long descriptor table manager  */
   1664         1.1       gwr 	b_tmgr_t *b_tbl;         /* B: short descriptor table manager */
   1665         1.1       gwr 	c_tmgr_t *c_tbl;         /* C: short page table manager       */
   1666         1.1       gwr 	mmu_long_dte_t *a_dte;   /* A: long descriptor table          */
   1667         1.1       gwr 	mmu_short_dte_t *b_dte;  /* B: short descriptor table         */
   1668         1.1       gwr 	mmu_short_pte_t *c_pte;  /* C: short page descriptor table    */
   1669         1.1       gwr 	pv_t      *pv;           /* pv list head                      */
   1670        1.94   thorpej 	bool wired;         /* is the mapping to be wired?       */
   1671         1.1       gwr 	enum {NONE, NEWA, NEWB, NEWC} llevel; /* used at end   */
   1672         1.1       gwr 
   1673         1.1       gwr 	if (pmap == pmap_kernel()) {
   1674         1.1       gwr 		pmap_enter_kernel(va, pa, prot);
   1675        1.61       chs 		return 0;
   1676         1.1       gwr 	}
   1677         1.7       gwr 
   1678        1.52    jeremy 	/*
   1679        1.52    jeremy 	 * Determine if the mapping should be wired.
   1680        1.52    jeremy 	 */
   1681        1.52    jeremy 	wired = ((flags & PMAP_WIRED) != 0);
   1682        1.52    jeremy 
   1683        1.52    jeremy 	/*
   1684        1.52    jeremy 	 * NOTE1:
   1685        1.52    jeremy 	 *
   1686        1.52    jeremy 	 * On November 13, 1999, someone changed the pmap_enter() API such
   1687        1.52    jeremy 	 * that it now accepts a 'flags' argument.  This new argument
   1688        1.52    jeremy 	 * contains bit-flags for the architecture-independent (UVM) system to
   1689        1.52    jeremy 	 * use in signalling certain mapping requirements to the architecture-
   1690        1.52    jeremy 	 * dependent (pmap) system.  The argument it replaces, 'wired', is now
   1691        1.52    jeremy 	 * one of the flags within it.
   1692        1.52    jeremy 	 *
   1693        1.52    jeremy 	 * In addition to flags signaled by the architecture-independent
   1694        1.52    jeremy 	 * system, parts of the architecture-dependent section of the sun3x
   1695        1.52    jeremy 	 * kernel pass their own flags in the lower, unused bits of the
   1696        1.52    jeremy 	 * physical address supplied to this function.  These flags are
   1697        1.52    jeremy 	 * extracted and stored in the temporary variable 'mapflags'.
   1698        1.52    jeremy 	 *
   1699        1.52    jeremy 	 * Extract sun3x specific flags from the physical address.
   1700       1.113   tsutsui 	 */
   1701        1.92   tsutsui 	mapflags = (pa & ~MMU_PAGE_MASK);
   1702        1.92   tsutsui 	pa &= MMU_PAGE_MASK;
   1703         1.7       gwr 
   1704         1.7       gwr 	/*
   1705        1.22    jeremy 	 * Determine if the physical address being mapped is on-board RAM.
   1706        1.22    jeremy 	 * Any other area of the address space is likely to belong to a
   1707        1.22    jeremy 	 * device and hence it would be disasterous to cache its contents.
   1708         1.7       gwr 	 */
   1709        1.95   thorpej 	if ((managed = is_managed(pa)) == false)
   1710        1.52    jeremy 		mapflags |= PMAP_NC;
   1711         1.7       gwr 
   1712         1.7       gwr 	/*
   1713         1.7       gwr 	 * For user mappings we walk along the MMU tables of the given
   1714         1.1       gwr 	 * pmap, reaching a PTE which describes the virtual page being
   1715         1.1       gwr 	 * mapped or changed.  If any level of the walk ends in an invalid
   1716         1.1       gwr 	 * entry, a table must be allocated and the entry must be updated
   1717         1.1       gwr 	 * to point to it.
   1718         1.1       gwr 	 * There is a bit of confusion as to whether this code must be
   1719         1.1       gwr 	 * re-entrant.  For now we will assume it is.  To support
   1720         1.1       gwr 	 * re-entrancy we must unlink tables from the table pool before
   1721         1.1       gwr 	 * we assume we may use them.  Tables are re-linked into the pool
   1722         1.1       gwr 	 * when we are finished with them at the end of the function.
   1723         1.1       gwr 	 * But I don't feel like doing that until we have proof that this
   1724         1.1       gwr 	 * needs to be re-entrant.
   1725         1.1       gwr 	 * 'llevel' records which tables need to be relinked.
   1726         1.1       gwr 	 */
   1727         1.1       gwr 	llevel = NONE;
   1728         1.1       gwr 
   1729         1.7       gwr 	/*
   1730         1.7       gwr 	 * Step 1 - Retrieve the A table from the pmap.  If it has no
   1731         1.7       gwr 	 * A table, allocate a new one from the available pool.
   1732         1.1       gwr 	 */
   1733         1.1       gwr 
   1734         1.7       gwr 	a_tbl = pmap->pm_a_tmgr;
   1735         1.7       gwr 	if (a_tbl == NULL) {
   1736         1.7       gwr 		/*
   1737         1.7       gwr 		 * This pmap does not currently have an A table.  Allocate
   1738         1.7       gwr 		 * a new one.
   1739         1.7       gwr 		 */
   1740         1.7       gwr 		a_tbl = get_a_table();
   1741         1.7       gwr 		a_tbl->at_parent = pmap;
   1742         1.7       gwr 
   1743         1.7       gwr 		/*
   1744         1.7       gwr 		 * Assign this new A table to the pmap, and calculate its
   1745         1.7       gwr 		 * physical address so that loadcrp() can be used to make
   1746         1.7       gwr 		 * the table active.
   1747         1.7       gwr 		 */
   1748         1.7       gwr 		pmap->pm_a_tmgr = a_tbl;
   1749         1.7       gwr 		pmap->pm_a_phys = mmu_vtop(a_tbl->at_dtbl);
   1750         1.7       gwr 
   1751         1.7       gwr 		/*
   1752         1.7       gwr 		 * If the process receiving a new A table is the current
   1753         1.7       gwr 		 * process, we are responsible for setting the MMU so that
   1754         1.9       gwr 		 * it becomes the current address space.  This only adds
   1755         1.9       gwr 		 * new mappings, so no need to flush anything.
   1756         1.7       gwr 		 */
   1757         1.9       gwr 		if (pmap == current_pmap()) {
   1758         1.9       gwr 			kernel_crp.rp_addr = pmap->pm_a_phys;
   1759         1.9       gwr 			loadcrp(&kernel_crp);
   1760         1.9       gwr 		}
   1761         1.7       gwr 
   1762         1.1       gwr 		if (!wired)
   1763         1.1       gwr 			llevel = NEWA;
   1764         1.1       gwr 	} else {
   1765         1.7       gwr 		/*
   1766         1.7       gwr 		 * Use the A table already allocated for this pmap.
   1767         1.1       gwr 		 * Unlink it from the A table pool if necessary.
   1768         1.1       gwr 		 */
   1769         1.1       gwr 		if (wired && !a_tbl->at_wcnt)
   1770         1.1       gwr 			TAILQ_REMOVE(&a_pool, a_tbl, at_link);
   1771         1.1       gwr 	}
   1772         1.1       gwr 
   1773         1.7       gwr 	/*
   1774         1.7       gwr 	 * Step 2 - Walk into the B table.  If there is no valid B table,
   1775         1.1       gwr 	 * allocate one.
   1776         1.1       gwr 	 */
   1777         1.1       gwr 
   1778         1.1       gwr 	a_idx = MMU_TIA(va);            /* Calculate the TIA of the VA. */
   1779         1.1       gwr 	a_dte = &a_tbl->at_dtbl[a_idx]; /* Retrieve descriptor from table */
   1780         1.1       gwr 	if (MMU_VALID_DT(*a_dte)) {     /* Is the descriptor valid? */
   1781         1.7       gwr 		/* The descriptor is valid.  Use the B table it points to. */
   1782         1.1       gwr 		/*************************************
   1783         1.1       gwr 		 *               a_idx               *
   1784         1.1       gwr 		 *                 v                 *
   1785         1.1       gwr 		 * a_tbl -> +-+-+-+-+-+-+-+-+-+-+-+- *
   1786         1.1       gwr 		 *          | | | | | | | | | | | |  *
   1787         1.1       gwr 		 *          +-+-+-+-+-+-+-+-+-+-+-+- *
   1788         1.1       gwr 		 *                 |                 *
   1789         1.1       gwr 		 *                 \- b_tbl -> +-+-  *
   1790         1.1       gwr 		 *                             | |   *
   1791         1.1       gwr 		 *                             +-+-  *
   1792         1.1       gwr 		 *************************************/
   1793         1.7       gwr 		b_dte = mmu_ptov(a_dte->addr.raw);
   1794         1.1       gwr 		b_tbl = mmuB2tmgr(b_dte);
   1795         1.7       gwr 
   1796         1.7       gwr 		/*
   1797         1.7       gwr 		 * If the requested mapping must be wired, but this table
   1798         1.7       gwr 		 * being used to map it is not, the table must be removed
   1799         1.7       gwr 		 * from the available pool and its wired entry count
   1800         1.7       gwr 		 * incremented.
   1801         1.7       gwr 		 */
   1802         1.1       gwr 		if (wired && !b_tbl->bt_wcnt) {
   1803         1.1       gwr 			TAILQ_REMOVE(&b_pool, b_tbl, bt_link);
   1804         1.7       gwr 			a_tbl->at_wcnt++;
   1805         1.1       gwr 		}
   1806         1.1       gwr 	} else {
   1807         1.7       gwr 		/* The descriptor is invalid.  Allocate a new B table. */
   1808         1.7       gwr 		b_tbl = get_b_table();
   1809         1.7       gwr 
   1810         1.1       gwr 		/* Point the parent A table descriptor to this new B table. */
   1811         1.7       gwr 		a_dte->addr.raw = mmu_vtop(b_tbl->bt_dtbl);
   1812         1.7       gwr 		a_dte->attr.raw = MMU_LONG_DTE_LU | MMU_DT_SHORT;
   1813         1.7       gwr 		a_tbl->at_ecnt++; /* Update parent's valid entry count */
   1814         1.7       gwr 
   1815         1.1       gwr 		/* Create the necessary back references to the parent table */
   1816         1.1       gwr 		b_tbl->bt_parent = a_tbl;
   1817         1.1       gwr 		b_tbl->bt_pidx = a_idx;
   1818         1.7       gwr 
   1819         1.7       gwr 		/*
   1820         1.7       gwr 		 * If this table is to be wired, make sure the parent A table
   1821         1.1       gwr 		 * wired count is updated to reflect that it has another wired
   1822         1.1       gwr 		 * entry.
   1823         1.1       gwr 		 */
   1824         1.1       gwr 		if (wired)
   1825         1.1       gwr 			a_tbl->at_wcnt++;
   1826         1.1       gwr 		else if (llevel == NONE)
   1827         1.1       gwr 			llevel = NEWB;
   1828         1.1       gwr 	}
   1829         1.1       gwr 
   1830         1.7       gwr 	/*
   1831         1.7       gwr 	 * Step 3 - Walk into the C table, if there is no valid C table,
   1832         1.1       gwr 	 * allocate one.
   1833         1.1       gwr 	 */
   1834         1.1       gwr 
   1835         1.1       gwr 	b_idx = MMU_TIB(va);            /* Calculate the TIB of the VA */
   1836         1.1       gwr 	b_dte = &b_tbl->bt_dtbl[b_idx]; /* Retrieve descriptor from table */
   1837         1.1       gwr 	if (MMU_VALID_DT(*b_dte)) {     /* Is the descriptor valid? */
   1838         1.7       gwr 		/* The descriptor is valid.  Use the C table it points to. */
   1839         1.1       gwr 		/**************************************
   1840         1.1       gwr 		 *               c_idx                *
   1841         1.1       gwr 		 * |                v                 *
   1842         1.1       gwr 		 * \- b_tbl -> +-+-+-+-+-+-+-+-+-+-+- *
   1843         1.1       gwr 		 *             | | | | | | | | | | |  *
   1844         1.1       gwr 		 *             +-+-+-+-+-+-+-+-+-+-+- *
   1845         1.1       gwr 		 *                  |                 *
   1846         1.1       gwr 		 *                  \- c_tbl -> +-+-- *
   1847         1.1       gwr 		 *                              | | | *
   1848         1.1       gwr 		 *                              +-+-- *
   1849         1.1       gwr 		 **************************************/
   1850         1.7       gwr 		c_pte = mmu_ptov(MMU_PTE_PA(*b_dte));
   1851         1.1       gwr 		c_tbl = mmuC2tmgr(c_pte);
   1852         1.7       gwr 
   1853         1.7       gwr 		/* If mapping is wired and table is not */
   1854         1.1       gwr 		if (wired && !c_tbl->ct_wcnt) {
   1855         1.1       gwr 			TAILQ_REMOVE(&c_pool, c_tbl, ct_link);
   1856         1.1       gwr 			b_tbl->bt_wcnt++;
   1857         1.1       gwr 		}
   1858         1.1       gwr 	} else {
   1859         1.7       gwr 		/* The descriptor is invalid.  Allocate a new C table. */
   1860         1.7       gwr 		c_tbl = get_c_table();
   1861         1.7       gwr 
   1862         1.1       gwr 		/* Point the parent B table descriptor to this new C table. */
   1863         1.7       gwr 		b_dte->attr.raw = mmu_vtop(c_tbl->ct_dtbl);
   1864         1.7       gwr 		b_dte->attr.raw |= MMU_DT_SHORT;
   1865         1.7       gwr 		b_tbl->bt_ecnt++; /* Update parent's valid entry count */
   1866         1.7       gwr 
   1867         1.1       gwr 		/* Create the necessary back references to the parent table */
   1868         1.1       gwr 		c_tbl->ct_parent = b_tbl;
   1869         1.1       gwr 		c_tbl->ct_pidx = b_idx;
   1870        1.26    jeremy 		/*
   1871        1.26    jeremy 		 * Store the pmap and base virtual managed address for faster
   1872        1.26    jeremy 		 * retrieval in the PV functions.
   1873        1.26    jeremy 		 */
   1874        1.26    jeremy 		c_tbl->ct_pmap = pmap;
   1875        1.26    jeremy 		c_tbl->ct_va = (va & (MMU_TIA_MASK|MMU_TIB_MASK));
   1876         1.7       gwr 
   1877         1.7       gwr 		/*
   1878         1.7       gwr 		 * If this table is to be wired, make sure the parent B table
   1879         1.1       gwr 		 * wired count is updated to reflect that it has another wired
   1880         1.1       gwr 		 * entry.
   1881         1.1       gwr 		 */
   1882         1.1       gwr 		if (wired)
   1883         1.1       gwr 			b_tbl->bt_wcnt++;
   1884         1.1       gwr 		else if (llevel == NONE)
   1885         1.1       gwr 			llevel = NEWC;
   1886         1.1       gwr 	}
   1887         1.1       gwr 
   1888         1.7       gwr 	/*
   1889         1.7       gwr 	 * Step 4 - Deposit a page descriptor (PTE) into the appropriate
   1890         1.1       gwr 	 * slot of the C table, describing the PA to which the VA is mapped.
   1891         1.1       gwr 	 */
   1892         1.1       gwr 
   1893         1.1       gwr 	pte_idx = MMU_TIC(va);
   1894         1.1       gwr 	c_pte = &c_tbl->ct_dtbl[pte_idx];
   1895         1.1       gwr 	if (MMU_VALID_DT(*c_pte)) { /* Is the entry currently valid? */
   1896         1.7       gwr 		/*
   1897         1.7       gwr 		 * The PTE is currently valid.  This particular call
   1898         1.1       gwr 		 * is just a synonym for one (or more) of the following
   1899         1.1       gwr 		 * operations:
   1900         1.7       gwr 		 *     change protection of a page
   1901         1.1       gwr 		 *     change wiring status of a page
   1902         1.1       gwr 		 *     remove the mapping of a page
   1903         1.1       gwr 		 */
   1904         1.7       gwr 
   1905         1.7       gwr 		/* First check if this is a wiring operation. */
   1906        1.91   tsutsui 		if (c_pte->attr.raw & MMU_SHORT_PTE_WIRED) {
   1907         1.7       gwr 			/*
   1908        1.91   tsutsui 			 * The existing mapping is wired, so adjust wired
   1909        1.91   tsutsui 			 * entry count here. If new mapping is still wired,
   1910        1.91   tsutsui 			 * wired entry count will be incremented again later.
   1911         1.7       gwr 			 */
   1912        1.91   tsutsui 			c_tbl->ct_wcnt--;
   1913        1.91   tsutsui 			if (!wired) {
   1914        1.91   tsutsui 				/*
   1915        1.91   tsutsui 				 * The mapping of this PTE is being changed
   1916        1.91   tsutsui 				 * from wired to unwired.
   1917        1.91   tsutsui 				 * Adjust wired entry counts in each table and
   1918        1.91   tsutsui 				 * set llevel flag to put unwired tables back
   1919        1.91   tsutsui 				 * into the active pool.
   1920        1.91   tsutsui 				 */
   1921        1.91   tsutsui 				if (c_tbl->ct_wcnt == 0) {
   1922        1.91   tsutsui 					llevel = NEWC;
   1923        1.91   tsutsui 					if (--b_tbl->bt_wcnt == 0) {
   1924        1.91   tsutsui 						llevel = NEWB;
   1925        1.91   tsutsui 						if (--a_tbl->at_wcnt == 0) {
   1926        1.91   tsutsui 							llevel = NEWA;
   1927        1.91   tsutsui 						}
   1928        1.91   tsutsui 					}
   1929        1.91   tsutsui 				}
   1930        1.91   tsutsui 			}
   1931         1.7       gwr 		}
   1932         1.7       gwr 
   1933         1.1       gwr 		/* Is the new address the same as the old? */
   1934         1.1       gwr 		if (MMU_PTE_PA(*c_pte) == pa) {
   1935         1.7       gwr 			/*
   1936         1.7       gwr 			 * Yes, mark that it does not need to be reinserted
   1937         1.7       gwr 			 * into the PV list.
   1938         1.7       gwr 			 */
   1939        1.95   thorpej 			insert = false;
   1940         1.7       gwr 
   1941         1.7       gwr 			/*
   1942         1.7       gwr 			 * Clear all but the modified, referenced and wired
   1943         1.7       gwr 			 * bits on the PTE.
   1944         1.7       gwr 			 */
   1945         1.7       gwr 			c_pte->attr.raw &= (MMU_SHORT_PTE_M
   1946        1.92   tsutsui 			    | MMU_SHORT_PTE_USED | MMU_SHORT_PTE_WIRED);
   1947         1.1       gwr 		} else {
   1948         1.1       gwr 			/* No, remove the old entry */
   1949         1.1       gwr 			pmap_remove_pte(c_pte);
   1950        1.95   thorpej 			insert = true;
   1951         1.1       gwr 		}
   1952         1.8       gwr 
   1953         1.8       gwr 		/*
   1954         1.8       gwr 		 * TLB flush is only necessary if modifying current map.
   1955         1.8       gwr 		 * However, in pmap_enter(), the pmap almost always IS
   1956         1.8       gwr 		 * the current pmap, so don't even bother to check.
   1957         1.8       gwr 		 */
   1958         1.8       gwr 		TBIS(va);
   1959         1.1       gwr 	} else {
   1960         1.7       gwr 		/*
   1961         1.7       gwr 		 * The PTE is invalid.  Increment the valid entry count in
   1962         1.8       gwr 		 * the C table manager to reflect the addition of a new entry.
   1963         1.7       gwr 		 */
   1964         1.1       gwr 		c_tbl->ct_ecnt++;
   1965         1.8       gwr 
   1966         1.8       gwr 		/* XXX - temporarily make sure the PTE is cleared. */
   1967         1.8       gwr 		c_pte->attr.raw = 0;
   1968         1.1       gwr 
   1969         1.7       gwr 		/* It will also need to be inserted into the PV list. */
   1970        1.95   thorpej 		insert = true;
   1971         1.7       gwr 	}
   1972         1.7       gwr 
   1973         1.7       gwr 	/*
   1974         1.7       gwr 	 * If page is changing from unwired to wired status, set an unused bit
   1975         1.7       gwr 	 * within the PTE to indicate that it is wired.  Also increment the
   1976         1.7       gwr 	 * wired entry count in the C table manager.
   1977         1.7       gwr 	 */
   1978         1.7       gwr 	if (wired) {
   1979         1.1       gwr 		c_pte->attr.raw |= MMU_SHORT_PTE_WIRED;
   1980         1.7       gwr 		c_tbl->ct_wcnt++;
   1981         1.1       gwr 	}
   1982         1.1       gwr 
   1983         1.7       gwr 	/*
   1984         1.7       gwr 	 * Map the page, being careful to preserve modify/reference/wired
   1985         1.7       gwr 	 * bits.  At this point it is assumed that the PTE either has no bits
   1986         1.7       gwr 	 * set, or if there are set bits, they are only modified, reference or
   1987         1.7       gwr 	 * wired bits.  If not, the following statement will cause erratic
   1988         1.7       gwr 	 * behavior.
   1989         1.7       gwr 	 */
   1990         1.8       gwr #ifdef	PMAP_DEBUG
   1991         1.7       gwr 	if (c_pte->attr.raw & ~(MMU_SHORT_PTE_M |
   1992         1.7       gwr 		MMU_SHORT_PTE_USED | MMU_SHORT_PTE_WIRED)) {
   1993         1.7       gwr 		printf("pmap_enter: junk left in PTE at %p\n", c_pte);
   1994         1.7       gwr 		Debugger();
   1995         1.7       gwr 	}
   1996         1.7       gwr #endif
   1997         1.7       gwr 	c_pte->attr.raw |= ((u_long) pa | MMU_DT_PAGE);
   1998         1.7       gwr 
   1999         1.7       gwr 	/*
   2000         1.7       gwr 	 * If the mapping should be read-only, set the write protect
   2001         1.7       gwr 	 * bit in the PTE.
   2002         1.7       gwr 	 */
   2003         1.7       gwr 	if (!(prot & VM_PROT_WRITE))
   2004         1.7       gwr 		c_pte->attr.raw |= MMU_SHORT_PTE_WP;
   2005         1.7       gwr 
   2006         1.7       gwr 	/*
   2007        1.87       chs 	 * Mark the PTE as used and/or modified as specified by the flags arg.
   2008        1.87       chs 	 */
   2009        1.87       chs 	if (flags & VM_PROT_ALL) {
   2010        1.87       chs 		c_pte->attr.raw |= MMU_SHORT_PTE_USED;
   2011        1.87       chs 		if (flags & VM_PROT_WRITE) {
   2012        1.87       chs 			c_pte->attr.raw |= MMU_SHORT_PTE_M;
   2013        1.87       chs 		}
   2014        1.87       chs 	}
   2015        1.87       chs 
   2016        1.87       chs 	/*
   2017         1.7       gwr 	 * If the mapping should be cache inhibited (indicated by the flag
   2018         1.7       gwr 	 * bits found on the lower order of the physical address.)
   2019         1.7       gwr 	 * mark the PTE as a cache inhibited page.
   2020         1.7       gwr 	 */
   2021        1.52    jeremy 	if (mapflags & PMAP_NC)
   2022         1.7       gwr 		c_pte->attr.raw |= MMU_SHORT_PTE_CI;
   2023         1.7       gwr 
   2024         1.7       gwr 	/*
   2025         1.7       gwr 	 * If the physical address being mapped is managed by the PV
   2026         1.7       gwr 	 * system then link the pte into the list of pages mapped to that
   2027         1.7       gwr 	 * address.
   2028         1.7       gwr 	 */
   2029         1.7       gwr 	if (insert && managed) {
   2030         1.7       gwr 		pv = pa2pv(pa);
   2031         1.7       gwr 		nidx = pteidx(c_pte);
   2032         1.7       gwr 
   2033         1.7       gwr 		pvebase[nidx].pve_next = pv->pv_idx;
   2034         1.7       gwr 		pv->pv_idx = nidx;
   2035         1.7       gwr 	}
   2036         1.1       gwr 
   2037        1.91   tsutsui 	/* Move any allocated or unwired tables back into the active pool. */
   2038       1.113   tsutsui 
   2039         1.1       gwr 	switch (llevel) {
   2040         1.1       gwr 		case NEWA:
   2041         1.1       gwr 			TAILQ_INSERT_TAIL(&a_pool, a_tbl, at_link);
   2042         1.1       gwr 			/* FALLTHROUGH */
   2043         1.1       gwr 		case NEWB:
   2044         1.1       gwr 			TAILQ_INSERT_TAIL(&b_pool, b_tbl, bt_link);
   2045         1.1       gwr 			/* FALLTHROUGH */
   2046         1.1       gwr 		case NEWC:
   2047         1.1       gwr 			TAILQ_INSERT_TAIL(&c_pool, c_tbl, ct_link);
   2048         1.1       gwr 			/* FALLTHROUGH */
   2049         1.1       gwr 		default:
   2050         1.1       gwr 			break;
   2051         1.1       gwr 	}
   2052        1.51   thorpej 
   2053        1.61       chs 	return 0;
   2054         1.1       gwr }
   2055         1.1       gwr 
   2056         1.1       gwr /* pmap_enter_kernel			INTERNAL
   2057         1.1       gwr  **
   2058         1.1       gwr  * Map the given virtual address to the given physical address within the
   2059         1.1       gwr  * kernel address space.  This function exists because the kernel map does
   2060         1.1       gwr  * not do dynamic table allocation.  It consists of a contiguous array of ptes
   2061         1.1       gwr  * and can be edited directly without the need to walk through any tables.
   2062       1.113   tsutsui  *
   2063         1.1       gwr  * XXX: "Danger, Will Robinson!"
   2064         1.1       gwr  * Note that the kernel should never take a fault on any page
   2065         1.1       gwr  * between [ KERNBASE .. virtual_avail ] and this is checked in
   2066         1.1       gwr  * trap.c for kernel-mode MMU faults.  This means that mappings
   2067         1.1       gwr  * created in that range must be implicily wired. -gwr
   2068         1.1       gwr  */
   2069       1.113   tsutsui void
   2070        1.86       chs pmap_enter_kernel(vaddr_t va, paddr_t pa, vm_prot_t prot)
   2071         1.1       gwr {
   2072        1.94   thorpej 	bool       was_valid, insert;
   2073        1.32       gwr 	u_short         pte_idx;
   2074        1.69       chs 	int             flags;
   2075         1.1       gwr 	mmu_short_pte_t *pte;
   2076         1.7       gwr 	pv_t            *pv;
   2077        1.69       chs 	paddr_t     old_pa;
   2078         1.7       gwr 
   2079        1.32       gwr 	flags = (pa & ~MMU_PAGE_MASK);
   2080        1.32       gwr 	pa &= MMU_PAGE_MASK;
   2081        1.32       gwr 
   2082        1.32       gwr 	if (is_managed(pa))
   2083       1.113   tsutsui 		insert = true;
   2084        1.32       gwr 	else
   2085        1.95   thorpej 		insert = false;
   2086         1.7       gwr 
   2087         1.7       gwr 	/*
   2088         1.7       gwr 	 * Calculate the index of the PTE being modified.
   2089         1.7       gwr 	 */
   2090       1.111   tsutsui 	pte_idx = (u_long)m68k_btop(va - KERNBASE3X);
   2091         1.1       gwr 
   2092        1.22    jeremy 	/* This array is traditionally named "Sysmap" */
   2093         1.7       gwr 	pte = &kernCbase[pte_idx];
   2094         1.7       gwr 
   2095         1.7       gwr 	if (MMU_VALID_DT(*pte)) {
   2096        1.95   thorpej 		was_valid = true;
   2097         1.7       gwr 		/*
   2098        1.32       gwr 		 * If the PTE already maps a different
   2099        1.32       gwr 		 * physical address, umap and pv_unlink.
   2100        1.24    jeremy 		 */
   2101        1.24    jeremy 		old_pa = MMU_PTE_PA(*pte);
   2102        1.32       gwr 		if (pa != old_pa)
   2103        1.32       gwr 			pmap_remove_pte(pte);
   2104        1.32       gwr 		else {
   2105        1.24    jeremy 		    /*
   2106        1.32       gwr 		     * Old PA and new PA are the same.  No need to
   2107        1.32       gwr 		     * relink the mapping within the PV list.
   2108        1.24    jeremy 		     */
   2109        1.95   thorpej 		     insert = false;
   2110         1.8       gwr 
   2111         1.7       gwr 		    /*
   2112        1.24    jeremy 		     * Save any mod/ref bits on the PTE.
   2113         1.7       gwr 		     */
   2114        1.24    jeremy 		    pte->attr.raw &= (MMU_SHORT_PTE_USED|MMU_SHORT_PTE_M);
   2115         1.7       gwr 		}
   2116         1.7       gwr 	} else {
   2117         1.8       gwr 		pte->attr.raw = MMU_DT_INVALID;
   2118        1.95   thorpej 		was_valid = false;
   2119         1.7       gwr 	}
   2120         1.7       gwr 
   2121         1.7       gwr 	/*
   2122         1.8       gwr 	 * Map the page.  Being careful to preserve modified/referenced bits
   2123         1.8       gwr 	 * on the PTE.
   2124         1.7       gwr 	 */
   2125         1.7       gwr 	pte->attr.raw |= (pa | MMU_DT_PAGE);
   2126         1.1       gwr 
   2127         1.1       gwr 	if (!(prot & VM_PROT_WRITE)) /* If access should be read-only */
   2128         1.1       gwr 		pte->attr.raw |= MMU_SHORT_PTE_WP;
   2129         1.7       gwr 	if (flags & PMAP_NC)
   2130         1.1       gwr 		pte->attr.raw |= MMU_SHORT_PTE_CI;
   2131         1.8       gwr 	if (was_valid)
   2132         1.7       gwr 		TBIS(va);
   2133         1.1       gwr 
   2134         1.7       gwr 	/*
   2135         1.7       gwr 	 * Insert the PTE into the PV system, if need be.
   2136         1.7       gwr 	 */
   2137         1.7       gwr 	if (insert) {
   2138         1.7       gwr 		pv = pa2pv(pa);
   2139         1.7       gwr 		pvebase[pte_idx].pve_next = pv->pv_idx;
   2140         1.7       gwr 		pv->pv_idx = pte_idx;
   2141         1.7       gwr 	}
   2142        1.34       gwr }
   2143        1.34       gwr 
   2144       1.113   tsutsui void
   2145       1.108    cegger pmap_kenter_pa(vaddr_t va, paddr_t pa, vm_prot_t prot, u_int flags)
   2146        1.49       chs {
   2147        1.69       chs 	mmu_short_pte_t	*pte;
   2148        1.69       chs 
   2149        1.69       chs 	/* This array is traditionally named "Sysmap" */
   2150       1.111   tsutsui 	pte = &kernCbase[(u_long)m68k_btop(va - KERNBASE3X)];
   2151        1.69       chs 
   2152        1.69       chs 	KASSERT(!MMU_VALID_DT(*pte));
   2153        1.69       chs 	pte->attr.raw = MMU_DT_INVALID | MMU_DT_PAGE | (pa & MMU_PAGE_MASK);
   2154        1.69       chs 	if (!(prot & VM_PROT_WRITE))
   2155        1.69       chs 		pte->attr.raw |= MMU_SHORT_PTE_WP;
   2156        1.49       chs }
   2157        1.49       chs 
   2158       1.113   tsutsui void
   2159        1.86       chs pmap_kremove(vaddr_t va, vsize_t len)
   2160        1.49       chs {
   2161        1.69       chs 	int idx, eidx;
   2162        1.69       chs 
   2163        1.69       chs #ifdef	PMAP_DEBUG
   2164        1.91   tsutsui 	if ((va & PGOFSET) || (len & PGOFSET))
   2165        1.72   tsutsui 		panic("pmap_kremove: alignment");
   2166        1.69       chs #endif
   2167        1.69       chs 
   2168       1.111   tsutsui 	idx  = m68k_btop(va - KERNBASE3X);
   2169       1.111   tsutsui 	eidx = m68k_btop(va + len - KERNBASE3X);
   2170        1.69       chs 
   2171        1.69       chs 	while (idx < eidx) {
   2172        1.69       chs 		kernCbase[idx++].attr.raw = MMU_DT_INVALID;
   2173        1.69       chs 		TBIS(va);
   2174        1.79   thorpej 		va += PAGE_SIZE;
   2175        1.49       chs 	}
   2176        1.49       chs }
   2177        1.49       chs 
   2178        1.35    jeremy /* pmap_map			INTERNAL
   2179        1.35    jeremy  **
   2180        1.35    jeremy  * Map a contiguous range of physical memory into a contiguous range of
   2181        1.35    jeremy  * the kernel virtual address space.
   2182        1.35    jeremy  *
   2183        1.35    jeremy  * Used for device mappings and early mapping of the kernel text/data/bss.
   2184        1.35    jeremy  * Returns the first virtual address beyond the end of the range.
   2185        1.34       gwr  */
   2186       1.113   tsutsui vaddr_t
   2187        1.86       chs pmap_map(vaddr_t va, paddr_t pa, paddr_t endpa, int prot)
   2188        1.34       gwr {
   2189        1.34       gwr 	int sz;
   2190        1.34       gwr 
   2191        1.34       gwr 	sz = endpa - pa;
   2192        1.34       gwr 	do {
   2193        1.34       gwr 		pmap_enter_kernel(va, pa, prot);
   2194        1.79   thorpej 		va += PAGE_SIZE;
   2195        1.79   thorpej 		pa += PAGE_SIZE;
   2196        1.79   thorpej 		sz -= PAGE_SIZE;
   2197        1.34       gwr 	} while (sz > 0);
   2198        1.73     chris 	pmap_update(pmap_kernel());
   2199        1.92   tsutsui 	return va;
   2200        1.92   tsutsui }
   2201        1.92   tsutsui 
   2202        1.92   tsutsui /* pmap_protect_kernel			INTERNAL
   2203        1.92   tsutsui  **
   2204        1.92   tsutsui  * Apply the given protection code to a kernel address range.
   2205        1.92   tsutsui  */
   2206       1.113   tsutsui static INLINE void
   2207        1.92   tsutsui pmap_protect_kernel(vaddr_t startva, vaddr_t endva, vm_prot_t prot)
   2208        1.92   tsutsui {
   2209        1.92   tsutsui 	vaddr_t va;
   2210        1.92   tsutsui 	mmu_short_pte_t *pte;
   2211        1.92   tsutsui 
   2212       1.111   tsutsui 	pte = &kernCbase[(unsigned long) m68k_btop(startva - KERNBASE3X)];
   2213        1.92   tsutsui 	for (va = startva; va < endva; va += PAGE_SIZE, pte++) {
   2214        1.92   tsutsui 		if (MMU_VALID_DT(*pte)) {
   2215        1.92   tsutsui 		    switch (prot) {
   2216        1.92   tsutsui 		        case VM_PROT_ALL:
   2217        1.92   tsutsui 		            break;
   2218        1.92   tsutsui 		        case VM_PROT_EXECUTE:
   2219        1.92   tsutsui 		        case VM_PROT_READ:
   2220        1.92   tsutsui 		        case VM_PROT_READ|VM_PROT_EXECUTE:
   2221        1.92   tsutsui 		            pte->attr.raw |= MMU_SHORT_PTE_WP;
   2222        1.92   tsutsui 		            break;
   2223        1.92   tsutsui 		        case VM_PROT_NONE:
   2224        1.92   tsutsui 		            /* this is an alias for 'pmap_remove_kernel' */
   2225        1.92   tsutsui 		            pmap_remove_pte(pte);
   2226        1.92   tsutsui 		            break;
   2227        1.92   tsutsui 		        default:
   2228        1.92   tsutsui 		            break;
   2229        1.92   tsutsui 		    }
   2230        1.92   tsutsui 		    /*
   2231        1.92   tsutsui 		     * since this is the kernel, immediately flush any cached
   2232        1.92   tsutsui 		     * descriptors for this address.
   2233        1.92   tsutsui 		     */
   2234        1.92   tsutsui 		    TBIS(va);
   2235        1.92   tsutsui 		}
   2236        1.92   tsutsui 	}
   2237         1.1       gwr }
   2238         1.1       gwr 
   2239         1.1       gwr /* pmap_protect			INTERFACE
   2240         1.1       gwr  **
   2241         1.7       gwr  * Apply the given protection to the given virtual address range within
   2242         1.1       gwr  * the given map.
   2243         1.1       gwr  *
   2244         1.1       gwr  * It is ok for the protection applied to be stronger than what is
   2245         1.1       gwr  * specified.  We use this to our advantage when the given map has no
   2246         1.7       gwr  * mapping for the virtual address.  By skipping a page when this
   2247         1.1       gwr  * is discovered, we are effectively applying a protection of VM_PROT_NONE,
   2248         1.1       gwr  * and therefore do not need to map the page just to apply a protection
   2249         1.1       gwr  * code.  Only pmap_enter() needs to create new mappings if they do not exist.
   2250         1.7       gwr  *
   2251         1.7       gwr  * XXX - This function could be speeded up by using pmap_stroll() for inital
   2252         1.7       gwr  *       setup, and then manual scrolling in the for() loop.
   2253         1.1       gwr  */
   2254       1.113   tsutsui void
   2255        1.86       chs pmap_protect(pmap_t pmap, vaddr_t startva, vaddr_t endva, vm_prot_t prot)
   2256         1.1       gwr {
   2257        1.94   thorpej 	bool iscurpmap;
   2258         1.1       gwr 	int a_idx, b_idx, c_idx;
   2259         1.1       gwr 	a_tmgr_t *a_tbl;
   2260         1.1       gwr 	b_tmgr_t *b_tbl;
   2261         1.1       gwr 	c_tmgr_t *c_tbl;
   2262         1.1       gwr 	mmu_short_pte_t *pte;
   2263         1.1       gwr 
   2264         1.1       gwr 	if (pmap == pmap_kernel()) {
   2265         1.7       gwr 		pmap_protect_kernel(startva, endva, prot);
   2266         1.1       gwr 		return;
   2267         1.1       gwr 	}
   2268         1.1       gwr 
   2269        1.11    jeremy 	/*
   2270        1.12    jeremy 	 * In this particular pmap implementation, there are only three
   2271        1.12    jeremy 	 * types of memory protection: 'all' (read/write/execute),
   2272        1.12    jeremy 	 * 'read-only' (read/execute) and 'none' (no mapping.)
   2273        1.12    jeremy 	 * It is not possible for us to treat 'executable' as a separate
   2274        1.12    jeremy 	 * protection type.  Therefore, protection requests that seek to
   2275        1.12    jeremy 	 * remove execute permission while retaining read or write, and those
   2276        1.12    jeremy 	 * that make little sense (write-only for example) are ignored.
   2277        1.11    jeremy 	 */
   2278        1.12    jeremy 	switch (prot) {
   2279        1.12    jeremy 		case VM_PROT_NONE:
   2280        1.12    jeremy 			/*
   2281        1.12    jeremy 			 * A request to apply the protection code of
   2282        1.12    jeremy 			 * 'VM_PROT_NONE' is a synonym for pmap_remove().
   2283        1.12    jeremy 			 */
   2284        1.12    jeremy 			pmap_remove(pmap, startva, endva);
   2285        1.12    jeremy 			return;
   2286        1.12    jeremy 		case	VM_PROT_EXECUTE:
   2287        1.12    jeremy 		case	VM_PROT_READ:
   2288        1.12    jeremy 		case	VM_PROT_READ|VM_PROT_EXECUTE:
   2289        1.12    jeremy 			/* continue */
   2290        1.12    jeremy 			break;
   2291        1.12    jeremy 		case	VM_PROT_WRITE:
   2292        1.12    jeremy 		case	VM_PROT_WRITE|VM_PROT_READ:
   2293        1.12    jeremy 		case	VM_PROT_WRITE|VM_PROT_EXECUTE:
   2294        1.12    jeremy 		case	VM_PROT_ALL:
   2295        1.12    jeremy 			/* None of these should happen in a sane system. */
   2296        1.12    jeremy 			return;
   2297        1.11    jeremy 	}
   2298        1.11    jeremy 
   2299        1.11    jeremy 	/*
   2300        1.11    jeremy 	 * If the pmap has no A table, it has no mappings and therefore
   2301        1.11    jeremy 	 * there is nothing to protect.
   2302        1.11    jeremy 	 */
   2303        1.11    jeremy 	if ((a_tbl = pmap->pm_a_tmgr) == NULL)
   2304        1.11    jeremy 		return;
   2305        1.11    jeremy 
   2306        1.11    jeremy 	a_idx = MMU_TIA(startva);
   2307        1.11    jeremy 	b_idx = MMU_TIB(startva);
   2308        1.11    jeremy 	c_idx = MMU_TIC(startva);
   2309        1.90     skrll 	b_tbl = NULL;
   2310        1.90     skrll 	c_tbl = NULL;
   2311        1.11    jeremy 
   2312         1.7       gwr 	iscurpmap = (pmap == current_pmap());
   2313        1.11    jeremy 	while (startva < endva) {
   2314        1.11    jeremy 		if (b_tbl || MMU_VALID_DT(a_tbl->at_dtbl[a_idx])) {
   2315        1.11    jeremy 		  if (b_tbl == NULL) {
   2316        1.11    jeremy 		    b_tbl = (b_tmgr_t *) a_tbl->at_dtbl[a_idx].addr.raw;
   2317        1.69       chs 		    b_tbl = mmu_ptov((vaddr_t)b_tbl);
   2318        1.69       chs 		    b_tbl = mmuB2tmgr((mmu_short_dte_t *)b_tbl);
   2319        1.11    jeremy 		  }
   2320        1.11    jeremy 		  if (c_tbl || MMU_VALID_DT(b_tbl->bt_dtbl[b_idx])) {
   2321        1.11    jeremy 		    if (c_tbl == NULL) {
   2322        1.11    jeremy 		      c_tbl = (c_tmgr_t *) MMU_DTE_PA(b_tbl->bt_dtbl[b_idx]);
   2323        1.69       chs 		      c_tbl = mmu_ptov((vaddr_t)c_tbl);
   2324        1.69       chs 		      c_tbl = mmuC2tmgr((mmu_short_pte_t *)c_tbl);
   2325        1.11    jeremy 		    }
   2326        1.11    jeremy 		    if (MMU_VALID_DT(c_tbl->ct_dtbl[c_idx])) {
   2327        1.11    jeremy 		      pte = &c_tbl->ct_dtbl[c_idx];
   2328        1.12    jeremy 		      /* make the mapping read-only */
   2329        1.12    jeremy 		      pte->attr.raw |= MMU_SHORT_PTE_WP;
   2330        1.11    jeremy 		      /*
   2331        1.11    jeremy 		       * If we just modified the current address space,
   2332        1.11    jeremy 		       * flush any translations for the modified page from
   2333        1.11    jeremy 		       * the translation cache and any data from it in the
   2334        1.11    jeremy 		       * data cache.
   2335        1.11    jeremy 		       */
   2336        1.11    jeremy 		      if (iscurpmap)
   2337        1.11    jeremy 		          TBIS(startva);
   2338        1.11    jeremy 		    }
   2339        1.79   thorpej 		    startva += PAGE_SIZE;
   2340         1.1       gwr 
   2341        1.11    jeremy 		    if (++c_idx >= MMU_C_TBL_SIZE) { /* exceeded C table? */
   2342        1.11    jeremy 		      c_tbl = NULL;
   2343        1.11    jeremy 		      c_idx = 0;
   2344        1.11    jeremy 		      if (++b_idx >= MMU_B_TBL_SIZE) { /* exceeded B table? */
   2345        1.11    jeremy 		        b_tbl = NULL;
   2346        1.11    jeremy 		        b_idx = 0;
   2347        1.11    jeremy 		      }
   2348        1.11    jeremy 		    }
   2349        1.11    jeremy 		  } else { /* C table wasn't valid */
   2350        1.11    jeremy 		    c_tbl = NULL;
   2351        1.11    jeremy 		    c_idx = 0;
   2352        1.11    jeremy 		    startva += MMU_TIB_RANGE;
   2353        1.11    jeremy 		    if (++b_idx >= MMU_B_TBL_SIZE) { /* exceeded B table? */
   2354        1.11    jeremy 		      b_tbl = NULL;
   2355        1.11    jeremy 		      b_idx = 0;
   2356        1.11    jeremy 		    }
   2357        1.11    jeremy 		  } /* C table */
   2358        1.11    jeremy 		} else { /* B table wasn't valid */
   2359        1.11    jeremy 		  b_tbl = NULL;
   2360        1.11    jeremy 		  b_idx = 0;
   2361        1.11    jeremy 		  startva += MMU_TIA_RANGE;
   2362        1.11    jeremy 		  a_idx++;
   2363        1.11    jeremy 		} /* B table */
   2364         1.1       gwr 	}
   2365         1.1       gwr }
   2366         1.1       gwr 
   2367        1.47   thorpej /* pmap_unwire				INTERFACE
   2368         1.1       gwr  **
   2369        1.47   thorpej  * Clear the wired attribute of the specified page.
   2370         1.1       gwr  *
   2371         1.1       gwr  * This function is called from vm_fault.c to unwire
   2372        1.47   thorpej  * a mapping.
   2373         1.1       gwr  */
   2374       1.113   tsutsui void
   2375        1.86       chs pmap_unwire(pmap_t pmap, vaddr_t va)
   2376         1.1       gwr {
   2377         1.1       gwr 	int a_idx, b_idx, c_idx;
   2378         1.1       gwr 	a_tmgr_t *a_tbl;
   2379         1.1       gwr 	b_tmgr_t *b_tbl;
   2380         1.1       gwr 	c_tmgr_t *c_tbl;
   2381         1.1       gwr 	mmu_short_pte_t *pte;
   2382       1.113   tsutsui 
   2383         1.1       gwr 	/* Kernel mappings always remain wired. */
   2384         1.1       gwr 	if (pmap == pmap_kernel())
   2385         1.1       gwr 		return;
   2386         1.1       gwr 
   2387         1.7       gwr 	/*
   2388         1.7       gwr 	 * Walk through the tables.  If the walk terminates without
   2389         1.1       gwr 	 * a valid PTE then the address wasn't wired in the first place.
   2390         1.1       gwr 	 * Return immediately.
   2391         1.1       gwr 	 */
   2392         1.1       gwr 	if (pmap_stroll(pmap, va, &a_tbl, &b_tbl, &c_tbl, &pte, &a_idx,
   2393        1.95   thorpej 		&b_idx, &c_idx) == false)
   2394         1.1       gwr 		return;
   2395         1.1       gwr 
   2396         1.1       gwr 
   2397         1.1       gwr 	/* Is the PTE wired?  If not, return. */
   2398         1.1       gwr 	if (!(pte->attr.raw & MMU_SHORT_PTE_WIRED))
   2399         1.1       gwr 		return;
   2400         1.1       gwr 
   2401         1.1       gwr 	/* Remove the wiring bit. */
   2402         1.1       gwr 	pte->attr.raw &= ~(MMU_SHORT_PTE_WIRED);
   2403         1.1       gwr 
   2404         1.7       gwr 	/*
   2405         1.7       gwr 	 * Decrement the wired entry count in the C table.
   2406         1.1       gwr 	 * If it reaches zero the following things happen:
   2407       1.113   tsutsui 	 * 1. The table no longer has any wired entries and is considered
   2408         1.1       gwr 	 *    unwired.
   2409         1.1       gwr 	 * 2. It is placed on the available queue.
   2410         1.1       gwr 	 * 3. The parent table's wired entry count is decremented.
   2411         1.1       gwr 	 * 4. If it reaches zero, this process repeats at step 1 and
   2412         1.1       gwr 	 *    stops at after reaching the A table.
   2413         1.1       gwr 	 */
   2414         1.7       gwr 	if (--c_tbl->ct_wcnt == 0) {
   2415         1.1       gwr 		TAILQ_INSERT_TAIL(&c_pool, c_tbl, ct_link);
   2416         1.7       gwr 		if (--b_tbl->bt_wcnt == 0) {
   2417         1.1       gwr 			TAILQ_INSERT_TAIL(&b_pool, b_tbl, bt_link);
   2418         1.7       gwr 			if (--a_tbl->at_wcnt == 0) {
   2419         1.1       gwr 				TAILQ_INSERT_TAIL(&a_pool, a_tbl, at_link);
   2420         1.1       gwr 			}
   2421         1.1       gwr 		}
   2422         1.1       gwr 	}
   2423         1.1       gwr }
   2424         1.1       gwr 
   2425         1.1       gwr /* pmap_copy				INTERFACE
   2426         1.1       gwr  **
   2427         1.1       gwr  * Copy the mappings of a range of addresses in one pmap, into
   2428         1.1       gwr  * the destination address of another.
   2429         1.1       gwr  *
   2430         1.1       gwr  * This routine is advisory.  Should we one day decide that MMU tables
   2431         1.1       gwr  * may be shared by more than one pmap, this function should be used to
   2432         1.1       gwr  * link them together.  Until that day however, we do nothing.
   2433         1.1       gwr  */
   2434         1.1       gwr void
   2435        1.86       chs pmap_copy(pmap_t pmap_a, pmap_t pmap_b, vaddr_t dst, vsize_t len, vaddr_t src)
   2436         1.1       gwr {
   2437        1.92   tsutsui 
   2438         1.1       gwr 	/* not implemented. */
   2439         1.1       gwr }
   2440         1.1       gwr 
   2441         1.1       gwr /* pmap_copy_page			INTERFACE
   2442         1.1       gwr  **
   2443         1.1       gwr  * Copy the contents of one physical page into another.
   2444         1.1       gwr  *
   2445         1.7       gwr  * This function makes use of two virtual pages allocated in pmap_bootstrap()
   2446        1.24    jeremy  * to map the two specified physical pages into the kernel address space.
   2447         1.7       gwr  *
   2448         1.7       gwr  * Note: We could use the transparent translation registers to make the
   2449         1.7       gwr  * mappings.  If we do so, be sure to disable interrupts before using them.
   2450         1.1       gwr  */
   2451       1.113   tsutsui void
   2452        1.86       chs pmap_copy_page(paddr_t srcpa, paddr_t dstpa)
   2453         1.1       gwr {
   2454        1.69       chs 	vaddr_t srcva, dstva;
   2455        1.23    jeremy 	int s;
   2456        1.24    jeremy 
   2457        1.24    jeremy 	srcva = tmp_vpages[0];
   2458        1.24    jeremy 	dstva = tmp_vpages[1];
   2459         1.1       gwr 
   2460        1.58   thorpej 	s = splvm();
   2461        1.69       chs #ifdef DIAGNOSTIC
   2462        1.24    jeremy 	if (tmp_vpages_inuse++)
   2463        1.24    jeremy 		panic("pmap_copy_page: temporary vpages are in use.");
   2464        1.69       chs #endif
   2465        1.23    jeremy 
   2466        1.23    jeremy 	/* Map pages as non-cacheable to avoid cache polution? */
   2467       1.108    cegger 	pmap_kenter_pa(srcva, srcpa, VM_PROT_READ, 0);
   2468       1.108    cegger 	pmap_kenter_pa(dstva, dstpa, VM_PROT_READ | VM_PROT_WRITE, 0);
   2469         1.7       gwr 
   2470       1.105   tsutsui 	/* Hand-optimized version of memcpy(dst, src, PAGE_SIZE) */
   2471        1.92   tsutsui 	copypage((char *)srcva, (char *)dstva);
   2472        1.24    jeremy 
   2473        1.79   thorpej 	pmap_kremove(srcva, PAGE_SIZE);
   2474        1.79   thorpej 	pmap_kremove(dstva, PAGE_SIZE);
   2475        1.24    jeremy 
   2476        1.69       chs #ifdef DIAGNOSTIC
   2477        1.24    jeremy 	--tmp_vpages_inuse;
   2478        1.69       chs #endif
   2479        1.23    jeremy 	splx(s);
   2480         1.1       gwr }
   2481         1.1       gwr 
   2482         1.1       gwr /* pmap_zero_page			INTERFACE
   2483         1.1       gwr  **
   2484         1.1       gwr  * Zero the contents of the specified physical page.
   2485         1.1       gwr  *
   2486         1.7       gwr  * Uses one of the virtual pages allocated in pmap_boostrap()
   2487        1.24    jeremy  * to map the specified page into the kernel address space.
   2488         1.1       gwr  */
   2489       1.113   tsutsui void
   2490        1.86       chs pmap_zero_page(paddr_t dstpa)
   2491         1.1       gwr {
   2492        1.69       chs 	vaddr_t dstva;
   2493        1.23    jeremy 	int s;
   2494        1.23    jeremy 
   2495        1.24    jeremy 	dstva = tmp_vpages[1];
   2496        1.58   thorpej 	s = splvm();
   2497        1.69       chs #ifdef DIAGNOSTIC
   2498        1.26    jeremy 	if (tmp_vpages_inuse++)
   2499        1.24    jeremy 		panic("pmap_zero_page: temporary vpages are in use.");
   2500        1.69       chs #endif
   2501        1.24    jeremy 
   2502        1.24    jeremy 	/* The comments in pmap_copy_page() above apply here also. */
   2503       1.108    cegger 	pmap_kenter_pa(dstva, dstpa, VM_PROT_READ | VM_PROT_WRITE, 0);
   2504        1.24    jeremy 
   2505       1.102    cegger 	/* Hand-optimized version of memset(ptr, 0, PAGE_SIZE) */
   2506        1.92   tsutsui 	zeropage((char *)dstva);
   2507         1.1       gwr 
   2508        1.79   thorpej 	pmap_kremove(dstva, PAGE_SIZE);
   2509        1.69       chs #ifdef DIAGNOSTIC
   2510        1.24    jeremy 	--tmp_vpages_inuse;
   2511        1.69       chs #endif
   2512        1.23    jeremy 	splx(s);
   2513         1.1       gwr }
   2514         1.1       gwr 
   2515        1.92   tsutsui /* pmap_pinit			INTERNAL
   2516        1.92   tsutsui  **
   2517        1.92   tsutsui  * Initialize a pmap structure.
   2518        1.92   tsutsui  */
   2519       1.113   tsutsui static INLINE void
   2520        1.92   tsutsui pmap_pinit(pmap_t pmap)
   2521        1.92   tsutsui {
   2522        1.92   tsutsui 
   2523        1.92   tsutsui 	memset(pmap, 0, sizeof(struct pmap));
   2524        1.92   tsutsui 	pmap->pm_a_tmgr = NULL;
   2525        1.92   tsutsui 	pmap->pm_a_phys = kernAphys;
   2526        1.92   tsutsui 	pmap->pm_refcount = 1;
   2527        1.92   tsutsui }
   2528        1.92   tsutsui 
   2529         1.1       gwr /* pmap_create			INTERFACE
   2530         1.1       gwr  **
   2531         1.1       gwr  * Create and return a pmap structure.
   2532         1.1       gwr  */
   2533       1.113   tsutsui pmap_t
   2534        1.86       chs pmap_create(void)
   2535         1.1       gwr {
   2536         1.1       gwr 	pmap_t	pmap;
   2537         1.1       gwr 
   2538        1.56   tsutsui 	pmap = pool_get(&pmap_pmap_pool, PR_WAITOK);
   2539         1.1       gwr 	pmap_pinit(pmap);
   2540         1.1       gwr 	return pmap;
   2541         1.1       gwr }
   2542         1.1       gwr 
   2543        1.92   tsutsui /* pmap_release				INTERNAL
   2544         1.1       gwr  **
   2545         1.1       gwr  * Release any resources held by the given pmap.
   2546         1.1       gwr  *
   2547         1.1       gwr  * This is the reverse analog to pmap_pinit.  It does not
   2548         1.1       gwr  * necessarily mean for the pmap structure to be deallocated,
   2549         1.1       gwr  * as in pmap_destroy.
   2550         1.1       gwr  */
   2551       1.113   tsutsui static INLINE void
   2552        1.86       chs pmap_release(pmap_t pmap)
   2553         1.1       gwr {
   2554        1.92   tsutsui 
   2555         1.7       gwr 	/*
   2556         1.7       gwr 	 * As long as the pmap contains no mappings,
   2557         1.1       gwr 	 * which always should be the case whenever
   2558         1.1       gwr 	 * this function is called, there really should
   2559         1.1       gwr 	 * be nothing to do.
   2560         1.1       gwr 	 */
   2561         1.1       gwr #ifdef	PMAP_DEBUG
   2562         1.1       gwr 	if (pmap == pmap_kernel())
   2563         1.9       gwr 		panic("pmap_release: kernel pmap");
   2564         1.1       gwr #endif
   2565         1.9       gwr 	/*
   2566         1.9       gwr 	 * XXX - If this pmap has an A table, give it back.
   2567         1.9       gwr 	 * The pmap SHOULD be empty by now, and pmap_remove
   2568         1.9       gwr 	 * should have already given back the A table...
   2569         1.9       gwr 	 * However, I see:  pmap->pm_a_tmgr->at_ecnt == 1
   2570         1.9       gwr 	 * at this point, which means some mapping was not
   2571         1.9       gwr 	 * removed when it should have been. -gwr
   2572         1.9       gwr 	 */
   2573         1.7       gwr 	if (pmap->pm_a_tmgr != NULL) {
   2574         1.9       gwr 		/* First make sure we are not using it! */
   2575         1.9       gwr 		if (kernel_crp.rp_addr == pmap->pm_a_phys) {
   2576         1.9       gwr 			kernel_crp.rp_addr = kernAphys;
   2577         1.9       gwr 			loadcrp(&kernel_crp);
   2578         1.9       gwr 		}
   2579        1.13       gwr #ifdef	PMAP_DEBUG /* XXX - todo! */
   2580        1.13       gwr 		/* XXX - Now complain... */
   2581        1.13       gwr 		printf("pmap_release: still have table\n");
   2582        1.13       gwr 		Debugger();
   2583        1.13       gwr #endif
   2584        1.95   thorpej 		free_a_table(pmap->pm_a_tmgr, true);
   2585         1.7       gwr 		pmap->pm_a_tmgr = NULL;
   2586         1.7       gwr 		pmap->pm_a_phys = kernAphys;
   2587         1.7       gwr 	}
   2588         1.1       gwr }
   2589         1.1       gwr 
   2590         1.1       gwr /* pmap_reference			INTERFACE
   2591         1.1       gwr  **
   2592         1.1       gwr  * Increment the reference count of a pmap.
   2593         1.1       gwr  */
   2594       1.113   tsutsui void
   2595        1.86       chs pmap_reference(pmap_t pmap)
   2596         1.1       gwr {
   2597       1.112   tsutsui 
   2598       1.112   tsutsui 	atomic_inc_uint(&pmap->pm_refcount);
   2599         1.1       gwr }
   2600         1.1       gwr 
   2601         1.1       gwr /* pmap_dereference			INTERNAL
   2602         1.1       gwr  **
   2603         1.1       gwr  * Decrease the reference count on the given pmap
   2604         1.1       gwr  * by one and return the current count.
   2605         1.1       gwr  */
   2606       1.113   tsutsui static INLINE int
   2607        1.86       chs pmap_dereference(pmap_t pmap)
   2608         1.1       gwr {
   2609         1.1       gwr 	int rtn;
   2610         1.1       gwr 
   2611       1.112   tsutsui 	rtn = atomic_dec_uint_nv(&pmap->pm_refcount);
   2612         1.1       gwr 
   2613         1.1       gwr 	return rtn;
   2614         1.1       gwr }
   2615       1.113   tsutsui 
   2616         1.1       gwr /* pmap_destroy			INTERFACE
   2617         1.1       gwr  **
   2618         1.1       gwr  * Decrement a pmap's reference count and delete
   2619         1.1       gwr  * the pmap if it becomes zero.  Will be called
   2620         1.1       gwr  * only after all mappings have been removed.
   2621         1.1       gwr  */
   2622       1.113   tsutsui void
   2623        1.86       chs pmap_destroy(pmap_t pmap)
   2624         1.1       gwr {
   2625        1.92   tsutsui 
   2626         1.1       gwr 	if (pmap_dereference(pmap) == 0) {
   2627         1.1       gwr 		pmap_release(pmap);
   2628        1.56   tsutsui 		pool_put(&pmap_pmap_pool, pmap);
   2629         1.1       gwr 	}
   2630         1.1       gwr }
   2631         1.1       gwr 
   2632         1.1       gwr /* pmap_is_referenced			INTERFACE
   2633         1.1       gwr  **
   2634         1.1       gwr  * Determine if the given physical page has been
   2635         1.1       gwr  * referenced (read from [or written to.])
   2636         1.1       gwr  */
   2637        1.94   thorpej bool
   2638        1.86       chs pmap_is_referenced(struct vm_page *pg)
   2639         1.1       gwr {
   2640        1.49       chs 	paddr_t   pa = VM_PAGE_TO_PHYS(pg);
   2641         1.1       gwr 	pv_t      *pv;
   2642        1.69       chs 	int       idx;
   2643         1.1       gwr 
   2644         1.7       gwr 	/*
   2645         1.7       gwr 	 * Check the flags on the pv head.  If they are set,
   2646         1.1       gwr 	 * return immediately.  Otherwise a search must be done.
   2647         1.7       gwr 	 */
   2648        1.69       chs 
   2649        1.69       chs 	pv = pa2pv(pa);
   2650         1.1       gwr 	if (pv->pv_flags & PV_FLAGS_USED)
   2651        1.95   thorpej 		return true;
   2652        1.32       gwr 
   2653        1.32       gwr 	/*
   2654        1.32       gwr 	 * Search through all pv elements pointing
   2655        1.32       gwr 	 * to this page and query their reference bits
   2656        1.32       gwr 	 */
   2657        1.32       gwr 
   2658        1.69       chs 	for (idx = pv->pv_idx; idx != PVE_EOL; idx = pvebase[idx].pve_next) {
   2659        1.32       gwr 		if (MMU_PTE_USED(kernCbase[idx])) {
   2660        1.95   thorpej 			return true;
   2661        1.32       gwr 		}
   2662         1.7       gwr 	}
   2663        1.95   thorpej 	return false;
   2664         1.1       gwr }
   2665         1.1       gwr 
   2666         1.1       gwr /* pmap_is_modified			INTERFACE
   2667         1.1       gwr  **
   2668         1.1       gwr  * Determine if the given physical page has been
   2669         1.1       gwr  * modified (written to.)
   2670         1.1       gwr  */
   2671        1.94   thorpej bool
   2672        1.86       chs pmap_is_modified(struct vm_page *pg)
   2673         1.1       gwr {
   2674        1.49       chs 	paddr_t   pa = VM_PAGE_TO_PHYS(pg);
   2675         1.1       gwr 	pv_t      *pv;
   2676        1.69       chs 	int       idx;
   2677         1.1       gwr 
   2678         1.1       gwr 	/* see comments in pmap_is_referenced() */
   2679         1.1       gwr 	pv = pa2pv(pa);
   2680        1.32       gwr 	if (pv->pv_flags & PV_FLAGS_MDFY)
   2681        1.95   thorpej 		return true;
   2682        1.32       gwr 
   2683        1.32       gwr 	for (idx = pv->pv_idx;
   2684        1.32       gwr 		 idx != PVE_EOL;
   2685        1.32       gwr 		 idx = pvebase[idx].pve_next) {
   2686        1.32       gwr 
   2687        1.32       gwr 		if (MMU_PTE_MODIFIED(kernCbase[idx])) {
   2688        1.95   thorpej 			return true;
   2689        1.32       gwr 		}
   2690         1.7       gwr 	}
   2691         1.7       gwr 
   2692        1.95   thorpej 	return false;
   2693         1.1       gwr }
   2694         1.1       gwr 
   2695         1.1       gwr /* pmap_page_protect			INTERFACE
   2696         1.1       gwr  **
   2697         1.1       gwr  * Applies the given protection to all mappings to the given
   2698         1.1       gwr  * physical page.
   2699         1.1       gwr  */
   2700       1.113   tsutsui void
   2701        1.86       chs pmap_page_protect(struct vm_page *pg, vm_prot_t prot)
   2702         1.1       gwr {
   2703        1.49       chs 	paddr_t   pa = VM_PAGE_TO_PHYS(pg);
   2704         1.1       gwr 	pv_t      *pv;
   2705        1.69       chs 	int       idx;
   2706        1.69       chs 	vaddr_t va;
   2707         1.1       gwr 	struct mmu_short_pte_struct *pte;
   2708         1.8       gwr 	c_tmgr_t  *c_tbl;
   2709         1.8       gwr 	pmap_t    pmap, curpmap;
   2710         1.1       gwr 
   2711         1.8       gwr 	curpmap = current_pmap();
   2712         1.1       gwr 	pv = pa2pv(pa);
   2713        1.32       gwr 
   2714        1.69       chs 	for (idx = pv->pv_idx; idx != PVE_EOL; idx = pvebase[idx].pve_next) {
   2715         1.7       gwr 		pte = &kernCbase[idx];
   2716         1.1       gwr 		switch (prot) {
   2717         1.1       gwr 			case VM_PROT_ALL:
   2718         1.1       gwr 				/* do nothing */
   2719         1.1       gwr 				break;
   2720         1.7       gwr 			case VM_PROT_EXECUTE:
   2721         1.1       gwr 			case VM_PROT_READ:
   2722         1.1       gwr 			case VM_PROT_READ|VM_PROT_EXECUTE:
   2723         1.8       gwr 				/*
   2724         1.8       gwr 				 * Determine the virtual address mapped by
   2725         1.8       gwr 				 * the PTE and flush ATC entries if necessary.
   2726         1.8       gwr 				 */
   2727         1.8       gwr 				va = pmap_get_pteinfo(idx, &pmap, &c_tbl);
   2728        1.69       chs 				pte->attr.raw |= MMU_SHORT_PTE_WP;
   2729         1.8       gwr 				if (pmap == curpmap || pmap == pmap_kernel())
   2730         1.8       gwr 					TBIS(va);
   2731         1.1       gwr 				break;
   2732         1.1       gwr 			case VM_PROT_NONE:
   2733         1.7       gwr 				/* Save the mod/ref bits. */
   2734         1.7       gwr 				pv->pv_flags |= pte->attr.raw;
   2735         1.7       gwr 				/* Invalidate the PTE. */
   2736         1.7       gwr 				pte->attr.raw = MMU_DT_INVALID;
   2737         1.8       gwr 
   2738         1.8       gwr 				/*
   2739         1.8       gwr 				 * Update table counts.  And flush ATC entries
   2740         1.8       gwr 				 * if necessary.
   2741         1.8       gwr 				 */
   2742         1.8       gwr 				va = pmap_get_pteinfo(idx, &pmap, &c_tbl);
   2743         1.8       gwr 
   2744         1.8       gwr 				/*
   2745         1.8       gwr 				 * If the PTE belongs to the kernel map,
   2746         1.8       gwr 				 * be sure to flush the page it maps.
   2747         1.8       gwr 				 */
   2748         1.8       gwr 				if (pmap == pmap_kernel()) {
   2749         1.8       gwr 					TBIS(va);
   2750         1.8       gwr 				} else {
   2751         1.8       gwr 					/*
   2752         1.8       gwr 					 * The PTE belongs to a user map.
   2753         1.8       gwr 					 * update the entry count in the C
   2754         1.8       gwr 					 * table to which it belongs and flush
   2755         1.8       gwr 					 * the ATC if the mapping belongs to
   2756         1.8       gwr 					 * the current pmap.
   2757         1.8       gwr 					 */
   2758         1.8       gwr 					c_tbl->ct_ecnt--;
   2759         1.8       gwr 					if (pmap == curpmap)
   2760         1.8       gwr 						TBIS(va);
   2761         1.8       gwr 				}
   2762         1.1       gwr 				break;
   2763         1.1       gwr 			default:
   2764         1.1       gwr 				break;
   2765         1.1       gwr 		}
   2766         1.1       gwr 	}
   2767         1.8       gwr 
   2768         1.8       gwr 	/*
   2769         1.8       gwr 	 * If the protection code indicates that all mappings to the page
   2770         1.8       gwr 	 * be removed, truncate the PV list to zero entries.
   2771         1.8       gwr 	 */
   2772         1.7       gwr 	if (prot == VM_PROT_NONE)
   2773         1.7       gwr 		pv->pv_idx = PVE_EOL;
   2774         1.1       gwr }
   2775         1.1       gwr 
   2776         1.7       gwr /* pmap_get_pteinfo		INTERNAL
   2777         1.1       gwr  **
   2778         1.7       gwr  * Called internally to find the pmap and virtual address within that
   2779         1.8       gwr  * map to which the pte at the given index maps.  Also includes the PTE's C
   2780         1.8       gwr  * table manager.
   2781         1.1       gwr  *
   2782         1.7       gwr  * Returns the pmap in the argument provided, and the virtual address
   2783         1.7       gwr  * by return value.
   2784         1.1       gwr  */
   2785       1.113   tsutsui vaddr_t
   2786        1.86       chs pmap_get_pteinfo(u_int idx, pmap_t *pmap, c_tmgr_t **tbl)
   2787         1.1       gwr {
   2788        1.69       chs 	vaddr_t     va = 0;
   2789         1.1       gwr 
   2790         1.7       gwr 	/*
   2791         1.7       gwr 	 * Determine if the PTE is a kernel PTE or a user PTE.
   2792         1.1       gwr 	 */
   2793         1.8       gwr 	if (idx >= NUM_KERN_PTES) {
   2794         1.7       gwr 		/*
   2795         1.7       gwr 		 * The PTE belongs to a user mapping.
   2796         1.7       gwr 		 */
   2797         1.8       gwr 		/* XXX: Would like an inline for this to validate idx... */
   2798        1.26    jeremy 		*tbl = &Ctmgrbase[(idx - NUM_KERN_PTES) / MMU_C_TBL_SIZE];
   2799        1.26    jeremy 
   2800        1.26    jeremy 		*pmap = (*tbl)->ct_pmap;
   2801        1.26    jeremy 		/*
   2802        1.26    jeremy 		 * To find the va to which the PTE maps, we first take
   2803        1.26    jeremy 		 * the table's base virtual address mapping which is stored
   2804        1.26    jeremy 		 * in ct_va.  We then increment this address by a page for
   2805        1.26    jeremy 		 * every slot skipped until we reach the PTE.
   2806        1.26    jeremy 		 */
   2807        1.92   tsutsui 		va = (*tbl)->ct_va;
   2808        1.26    jeremy 		va += m68k_ptob(idx % MMU_C_TBL_SIZE);
   2809         1.7       gwr 	} else {
   2810         1.7       gwr 		/*
   2811         1.7       gwr 		 * The PTE belongs to the kernel map.
   2812         1.7       gwr 		 */
   2813         1.8       gwr 		*pmap = pmap_kernel();
   2814         1.8       gwr 
   2815        1.25     veego 		va = m68k_ptob(idx);
   2816       1.111   tsutsui 		va += KERNBASE3X;
   2817         1.7       gwr 	}
   2818       1.113   tsutsui 
   2819         1.1       gwr 	return va;
   2820         1.1       gwr }
   2821         1.1       gwr 
   2822         1.1       gwr /* pmap_clear_modify			INTERFACE
   2823         1.1       gwr  **
   2824         1.1       gwr  * Clear the modification bit on the page at the specified
   2825         1.1       gwr  * physical address.
   2826         1.1       gwr  *
   2827         1.1       gwr  */
   2828        1.94   thorpej bool
   2829        1.86       chs pmap_clear_modify(struct vm_page *pg)
   2830         1.1       gwr {
   2831        1.49       chs 	paddr_t pa = VM_PAGE_TO_PHYS(pg);
   2832        1.94   thorpej 	bool rv;
   2833        1.49       chs 
   2834        1.49       chs 	rv = pmap_is_modified(pg);
   2835         1.1       gwr 	pmap_clear_pv(pa, PV_FLAGS_MDFY);
   2836        1.49       chs 	return rv;
   2837         1.1       gwr }
   2838         1.1       gwr 
   2839         1.1       gwr /* pmap_clear_reference			INTERFACE
   2840         1.1       gwr  **
   2841         1.1       gwr  * Clear the referenced bit on the page at the specified
   2842         1.1       gwr  * physical address.
   2843         1.1       gwr  */
   2844        1.94   thorpej bool
   2845        1.86       chs pmap_clear_reference(struct vm_page *pg)
   2846         1.1       gwr {
   2847        1.49       chs 	paddr_t pa = VM_PAGE_TO_PHYS(pg);
   2848        1.94   thorpej 	bool rv;
   2849        1.49       chs 
   2850        1.49       chs 	rv = pmap_is_referenced(pg);
   2851         1.1       gwr 	pmap_clear_pv(pa, PV_FLAGS_USED);
   2852        1.49       chs 	return rv;
   2853         1.1       gwr }
   2854       1.113   tsutsui 
   2855         1.1       gwr /* pmap_clear_pv			INTERNAL
   2856         1.1       gwr  **
   2857         1.1       gwr  * Clears the specified flag from the specified physical address.
   2858         1.1       gwr  * (Used by pmap_clear_modify() and pmap_clear_reference().)
   2859         1.1       gwr  *
   2860         1.1       gwr  * Flag is one of:
   2861         1.1       gwr  *   PV_FLAGS_MDFY - Page modified bit.
   2862         1.1       gwr  *   PV_FLAGS_USED - Page used (referenced) bit.
   2863         1.1       gwr  *
   2864         1.1       gwr  * This routine must not only clear the flag on the pv list
   2865         1.1       gwr  * head.  It must also clear the bit on every pte in the pv
   2866         1.1       gwr  * list associated with the address.
   2867         1.1       gwr  */
   2868       1.113   tsutsui void
   2869        1.86       chs pmap_clear_pv(paddr_t pa, int flag)
   2870         1.1       gwr {
   2871         1.1       gwr 	pv_t      *pv;
   2872        1.69       chs 	int       idx;
   2873        1.69       chs 	vaddr_t   va;
   2874         1.7       gwr 	pmap_t          pmap;
   2875         1.1       gwr 	mmu_short_pte_t *pte;
   2876         1.7       gwr 	c_tmgr_t        *c_tbl;
   2877         1.1       gwr 
   2878         1.1       gwr 	pv = pa2pv(pa);
   2879         1.1       gwr 	pv->pv_flags &= ~(flag);
   2880        1.69       chs 	for (idx = pv->pv_idx; idx != PVE_EOL; idx = pvebase[idx].pve_next) {
   2881         1.7       gwr 		pte = &kernCbase[idx];
   2882         1.1       gwr 		pte->attr.raw &= ~(flag);
   2883        1.69       chs 
   2884         1.7       gwr 		/*
   2885         1.7       gwr 		 * The MC68030 MMU will not set the modified or
   2886         1.7       gwr 		 * referenced bits on any MMU tables for which it has
   2887         1.7       gwr 		 * a cached descriptor with its modify bit set.  To insure
   2888         1.7       gwr 		 * that it will modify these bits on the PTE during the next
   2889         1.7       gwr 		 * time it is written to or read from, we must flush it from
   2890         1.7       gwr 		 * the ATC.
   2891         1.7       gwr 		 *
   2892         1.7       gwr 		 * Ordinarily it is only necessary to flush the descriptor
   2893         1.7       gwr 		 * if it is used in the current address space.  But since I
   2894         1.7       gwr 		 * am not sure that there will always be a notion of
   2895         1.7       gwr 		 * 'the current address space' when this function is called,
   2896         1.7       gwr 		 * I will skip the test and always flush the address.  It
   2897         1.7       gwr 		 * does no harm.
   2898         1.7       gwr 		 */
   2899        1.69       chs 
   2900         1.8       gwr 		va = pmap_get_pteinfo(idx, &pmap, &c_tbl);
   2901         1.7       gwr 		TBIS(va);
   2902         1.1       gwr 	}
   2903         1.1       gwr }
   2904         1.1       gwr 
   2905        1.92   tsutsui /* pmap_extract_kernel		INTERNAL
   2906        1.92   tsutsui  **
   2907        1.92   tsutsui  * Extract a translation from the kernel address space.
   2908        1.92   tsutsui  */
   2909       1.113   tsutsui static INLINE bool
   2910        1.92   tsutsui pmap_extract_kernel(vaddr_t va, paddr_t *pap)
   2911        1.92   tsutsui {
   2912        1.92   tsutsui 	mmu_short_pte_t *pte;
   2913        1.92   tsutsui 
   2914       1.111   tsutsui 	pte = &kernCbase[(u_int)m68k_btop(va - KERNBASE3X)];
   2915        1.92   tsutsui 	if (!MMU_VALID_DT(*pte))
   2916        1.95   thorpej 		return false;
   2917        1.92   tsutsui 	if (pap != NULL)
   2918        1.92   tsutsui 		*pap = MMU_PTE_PA(*pte);
   2919        1.95   thorpej 	return true;
   2920        1.92   tsutsui }
   2921        1.92   tsutsui 
   2922         1.1       gwr /* pmap_extract			INTERFACE
   2923         1.1       gwr  **
   2924         1.1       gwr  * Return the physical address mapped by the virtual address
   2925        1.48   thorpej  * in the specified pmap.
   2926         1.1       gwr  *
   2927         1.1       gwr  * Note: this function should also apply an exclusive lock
   2928         1.1       gwr  * on the pmap system during its duration.
   2929         1.1       gwr  */
   2930       1.113   tsutsui bool
   2931        1.86       chs pmap_extract(pmap_t pmap, vaddr_t va, paddr_t *pap)
   2932         1.1       gwr {
   2933         1.1       gwr 	int a_idx, b_idx, pte_idx;
   2934         1.1       gwr 	a_tmgr_t	*a_tbl;
   2935         1.1       gwr 	b_tmgr_t	*b_tbl;
   2936         1.1       gwr 	c_tmgr_t	*c_tbl;
   2937         1.1       gwr 	mmu_short_pte_t	*c_pte;
   2938         1.1       gwr 
   2939         1.1       gwr 	if (pmap == pmap_kernel())
   2940        1.48   thorpej 		return pmap_extract_kernel(va, pap);
   2941         1.1       gwr 
   2942         1.1       gwr 	if (pmap_stroll(pmap, va, &a_tbl, &b_tbl, &c_tbl,
   2943        1.95   thorpej 		&c_pte, &a_idx, &b_idx, &pte_idx) == false)
   2944        1.95   thorpej 		return false;
   2945         1.1       gwr 
   2946         1.7       gwr 	if (!MMU_VALID_DT(*c_pte))
   2947        1.95   thorpej 		return false;
   2948         1.7       gwr 
   2949        1.48   thorpej 	if (pap != NULL)
   2950        1.48   thorpej 		*pap = MMU_PTE_PA(*c_pte);
   2951        1.95   thorpej 	return true;
   2952         1.1       gwr }
   2953         1.1       gwr 
   2954         1.1       gwr /* pmap_remove_kernel		INTERNAL
   2955         1.1       gwr  **
   2956         1.1       gwr  * Remove the mapping of a range of virtual addresses from the kernel map.
   2957         1.9       gwr  * The arguments are already page-aligned.
   2958         1.1       gwr  */
   2959       1.113   tsutsui static INLINE void
   2960        1.86       chs pmap_remove_kernel(vaddr_t sva, vaddr_t eva)
   2961         1.1       gwr {
   2962         1.9       gwr 	int idx, eidx;
   2963         1.9       gwr 
   2964         1.9       gwr #ifdef	PMAP_DEBUG
   2965         1.9       gwr 	if ((sva & PGOFSET) || (eva & PGOFSET))
   2966         1.9       gwr 		panic("pmap_remove_kernel: alignment");
   2967         1.9       gwr #endif
   2968         1.1       gwr 
   2969       1.111   tsutsui 	idx  = m68k_btop(sva - KERNBASE3X);
   2970       1.111   tsutsui 	eidx = m68k_btop(eva - KERNBASE3X);
   2971         1.9       gwr 
   2972        1.24    jeremy 	while (idx < eidx) {
   2973         1.9       gwr 		pmap_remove_pte(&kernCbase[idx++]);
   2974        1.24    jeremy 		TBIS(sva);
   2975        1.79   thorpej 		sva += PAGE_SIZE;
   2976        1.24    jeremy 	}
   2977         1.1       gwr }
   2978         1.1       gwr 
   2979         1.1       gwr /* pmap_remove			INTERFACE
   2980         1.1       gwr  **
   2981         1.1       gwr  * Remove the mapping of a range of virtual addresses from the given pmap.
   2982         1.7       gwr  *
   2983         1.1       gwr  */
   2984       1.113   tsutsui void
   2985        1.88   tsutsui pmap_remove(pmap_t pmap, vaddr_t sva, vaddr_t eva)
   2986         1.1       gwr {
   2987         1.7       gwr 
   2988         1.1       gwr 	if (pmap == pmap_kernel()) {
   2989        1.88   tsutsui 		pmap_remove_kernel(sva, eva);
   2990         1.1       gwr 		return;
   2991         1.1       gwr 	}
   2992         1.1       gwr 
   2993         1.7       gwr 	/*
   2994         1.7       gwr 	 * If the pmap doesn't have an A table of its own, it has no mappings
   2995         1.7       gwr 	 * that can be removed.
   2996         1.1       gwr 	 */
   2997         1.7       gwr 	if (pmap->pm_a_tmgr == NULL)
   2998         1.7       gwr 		return;
   2999         1.7       gwr 
   3000         1.7       gwr 	/*
   3001         1.7       gwr 	 * Remove the specified range from the pmap.  If the function
   3002         1.7       gwr 	 * returns true, the operation removed all the valid mappings
   3003         1.7       gwr 	 * in the pmap and freed its A table.  If this happened to the
   3004         1.7       gwr 	 * currently loaded pmap, the MMU root pointer must be reloaded
   3005         1.7       gwr 	 * with the default 'kernel' map.
   3006       1.113   tsutsui 	 */
   3007        1.88   tsutsui 	if (pmap_remove_a(pmap->pm_a_tmgr, sva, eva)) {
   3008         1.9       gwr 		if (kernel_crp.rp_addr == pmap->pm_a_phys) {
   3009         1.9       gwr 			kernel_crp.rp_addr = kernAphys;
   3010         1.9       gwr 			loadcrp(&kernel_crp);
   3011         1.9       gwr 			/* will do TLB flush below */
   3012         1.9       gwr 		}
   3013         1.7       gwr 		pmap->pm_a_tmgr = NULL;
   3014         1.7       gwr 		pmap->pm_a_phys = kernAphys;
   3015         1.1       gwr 	}
   3016         1.9       gwr 
   3017         1.9       gwr 	/*
   3018         1.9       gwr 	 * If we just modified the current address space,
   3019         1.9       gwr 	 * make sure to flush the MMU cache.
   3020         1.9       gwr 	 *
   3021         1.9       gwr 	 * XXX - this could be an unecessarily large flush.
   3022         1.9       gwr 	 * XXX - Could decide, based on the size of the VA range
   3023         1.9       gwr 	 * to be removed, whether to flush "by pages" or "all".
   3024         1.9       gwr 	 */
   3025         1.9       gwr 	if (pmap == current_pmap())
   3026         1.9       gwr 		TBIAU();
   3027         1.1       gwr }
   3028         1.1       gwr 
   3029         1.1       gwr /* pmap_remove_a			INTERNAL
   3030         1.1       gwr  **
   3031         1.1       gwr  * This is function number one in a set of three that removes a range
   3032         1.1       gwr  * of memory in the most efficient manner by removing the highest possible
   3033         1.1       gwr  * tables from the memory space.  This particular function attempts to remove
   3034         1.1       gwr  * as many B tables as it can, delegating the remaining fragmented ranges to
   3035         1.1       gwr  * pmap_remove_b().
   3036         1.1       gwr  *
   3037         1.7       gwr  * If the removal operation results in an empty A table, the function returns
   3038        1.95   thorpej  * true.
   3039         1.7       gwr  *
   3040         1.1       gwr  * It's ugly but will do for now.
   3041         1.1       gwr  */
   3042       1.113   tsutsui bool
   3043        1.88   tsutsui pmap_remove_a(a_tmgr_t *a_tbl, vaddr_t sva, vaddr_t eva)
   3044         1.1       gwr {
   3045        1.94   thorpej 	bool empty;
   3046         1.1       gwr 	int idx;
   3047        1.69       chs 	vaddr_t nstart, nend;
   3048         1.1       gwr 	b_tmgr_t *b_tbl;
   3049         1.1       gwr 	mmu_long_dte_t  *a_dte;
   3050         1.1       gwr 	mmu_short_dte_t *b_dte;
   3051        1.91   tsutsui 	uint8_t at_wired, bt_wired;
   3052         1.8       gwr 
   3053         1.7       gwr 	/*
   3054         1.7       gwr 	 * The following code works with what I call a 'granularity
   3055         1.7       gwr 	 * reduction algorithim'.  A range of addresses will always have
   3056         1.7       gwr 	 * the following properties, which are classified according to
   3057         1.7       gwr 	 * how the range relates to the size of the current granularity
   3058         1.7       gwr 	 * - an A table entry:
   3059         1.7       gwr 	 *
   3060         1.7       gwr 	 *            1 2       3 4
   3061         1.7       gwr 	 * -+---+---+---+---+---+---+---+-
   3062         1.7       gwr 	 * -+---+---+---+---+---+---+---+-
   3063         1.7       gwr 	 *
   3064         1.7       gwr 	 * A range will always start on a granularity boundary, illustrated
   3065         1.7       gwr 	 * by '+' signs in the table above, or it will start at some point
   3066         1.7       gwr 	 * inbetween a granularity boundary, as illustrated by point 1.
   3067         1.7       gwr 	 * The first step in removing a range of addresses is to remove the
   3068         1.7       gwr 	 * range between 1 and 2, the nearest granularity boundary.  This
   3069         1.7       gwr 	 * job is handled by the section of code governed by the
   3070         1.7       gwr 	 * 'if (start < nstart)' statement.
   3071       1.113   tsutsui 	 *
   3072         1.7       gwr 	 * A range will always encompass zero or more intergral granules,
   3073         1.7       gwr 	 * illustrated by points 2 and 3.  Integral granules are easy to
   3074         1.7       gwr 	 * remove.  The removal of these granules is the second step, and
   3075         1.7       gwr 	 * is handled by the code block 'if (nstart < nend)'.
   3076         1.7       gwr 	 *
   3077         1.7       gwr 	 * Lastly, a range will always end on a granularity boundary,
   3078         1.7       gwr 	 * ill. by point 3, or it will fall just beyond one, ill. by point
   3079         1.7       gwr 	 * 4.  The last step involves removing this range and is handled by
   3080         1.7       gwr 	 * the code block 'if (nend < end)'.
   3081         1.7       gwr 	 */
   3082        1.88   tsutsui 	nstart = MMU_ROUND_UP_A(sva);
   3083        1.88   tsutsui 	nend = MMU_ROUND_A(eva);
   3084         1.1       gwr 
   3085        1.91   tsutsui 	at_wired = a_tbl->at_wcnt;
   3086        1.91   tsutsui 
   3087        1.88   tsutsui 	if (sva < nstart) {
   3088         1.7       gwr 		/*
   3089         1.7       gwr 		 * This block is executed if the range starts between
   3090         1.7       gwr 		 * a granularity boundary.
   3091         1.7       gwr 		 *
   3092         1.7       gwr 		 * First find the DTE which is responsible for mapping
   3093         1.7       gwr 		 * the start of the range.
   3094         1.7       gwr 		 */
   3095        1.88   tsutsui 		idx = MMU_TIA(sva);
   3096         1.1       gwr 		a_dte = &a_tbl->at_dtbl[idx];
   3097         1.7       gwr 
   3098         1.7       gwr 		/*
   3099         1.7       gwr 		 * If the DTE is valid then delegate the removal of the sub
   3100         1.7       gwr 		 * range to pmap_remove_b(), which can remove addresses at
   3101         1.7       gwr 		 * a finer granularity.
   3102         1.7       gwr 		 */
   3103         1.1       gwr 		if (MMU_VALID_DT(*a_dte)) {
   3104         1.7       gwr 			b_dte = mmu_ptov(a_dte->addr.raw);
   3105         1.1       gwr 			b_tbl = mmuB2tmgr(b_dte);
   3106        1.91   tsutsui 			bt_wired = b_tbl->bt_wcnt;
   3107         1.7       gwr 
   3108         1.7       gwr 			/*
   3109         1.7       gwr 			 * The sub range to be removed starts at the start
   3110         1.7       gwr 			 * of the full range we were asked to remove, and ends
   3111         1.7       gwr 			 * at the greater of:
   3112         1.7       gwr 			 * 1. The end of the full range, -or-
   3113         1.7       gwr 			 * 2. The end of the full range, rounded down to the
   3114         1.7       gwr 			 *    nearest granularity boundary.
   3115         1.7       gwr 			 */
   3116        1.88   tsutsui 			if (eva < nstart)
   3117        1.88   tsutsui 				empty = pmap_remove_b(b_tbl, sva, eva);
   3118         1.7       gwr 			else
   3119        1.88   tsutsui 				empty = pmap_remove_b(b_tbl, sva, nstart);
   3120         1.7       gwr 
   3121         1.7       gwr 			/*
   3122        1.91   tsutsui 			 * If the child table no longer has wired entries,
   3123        1.91   tsutsui 			 * decrement wired entry count.
   3124        1.91   tsutsui 			 */
   3125        1.91   tsutsui 			if (bt_wired && b_tbl->bt_wcnt == 0)
   3126        1.91   tsutsui 				a_tbl->at_wcnt--;
   3127        1.91   tsutsui 
   3128        1.91   tsutsui 			/*
   3129         1.7       gwr 			 * If the removal resulted in an empty B table,
   3130         1.7       gwr 			 * invalidate the DTE that points to it and decrement
   3131         1.7       gwr 			 * the valid entry count of the A table.
   3132         1.7       gwr 			 */
   3133         1.7       gwr 			if (empty) {
   3134         1.7       gwr 				a_dte->attr.raw = MMU_DT_INVALID;
   3135         1.7       gwr 				a_tbl->at_ecnt--;
   3136         1.1       gwr 			}
   3137         1.1       gwr 		}
   3138         1.7       gwr 		/*
   3139         1.7       gwr 		 * If the DTE is invalid, the address range is already non-
   3140        1.68       wiz 		 * existent and can simply be skipped.
   3141         1.7       gwr 		 */
   3142         1.1       gwr 	}
   3143         1.1       gwr 	if (nstart < nend) {
   3144         1.7       gwr 		/*
   3145         1.8       gwr 		 * This block is executed if the range spans a whole number
   3146         1.7       gwr 		 * multiple of granules (A table entries.)
   3147         1.7       gwr 		 *
   3148         1.7       gwr 		 * First find the DTE which is responsible for mapping
   3149         1.7       gwr 		 * the start of the first granule involved.
   3150         1.7       gwr 		 */
   3151         1.1       gwr 		idx = MMU_TIA(nstart);
   3152         1.1       gwr 		a_dte = &a_tbl->at_dtbl[idx];
   3153         1.7       gwr 
   3154         1.7       gwr 		/*
   3155         1.7       gwr 		 * Remove entire sub-granules (B tables) one at a time,
   3156         1.7       gwr 		 * until reaching the end of the range.
   3157         1.7       gwr 		 */
   3158         1.7       gwr 		for (; nstart < nend; a_dte++, nstart += MMU_TIA_RANGE)
   3159         1.1       gwr 			if (MMU_VALID_DT(*a_dte)) {
   3160         1.7       gwr 				/*
   3161         1.7       gwr 				 * Find the B table manager for the
   3162         1.7       gwr 				 * entry and free it.
   3163         1.7       gwr 				 */
   3164         1.7       gwr 				b_dte = mmu_ptov(a_dte->addr.raw);
   3165         1.1       gwr 				b_tbl = mmuB2tmgr(b_dte);
   3166        1.91   tsutsui 				bt_wired = b_tbl->bt_wcnt;
   3167        1.91   tsutsui 
   3168        1.95   thorpej 				free_b_table(b_tbl, true);
   3169         1.7       gwr 
   3170         1.7       gwr 				/*
   3171        1.91   tsutsui 				 * All child entries has been removed.
   3172        1.91   tsutsui 				 * If there were any wired entries in it,
   3173        1.91   tsutsui 				 * decrement wired entry count.
   3174        1.91   tsutsui 				 */
   3175        1.91   tsutsui 				if (bt_wired)
   3176        1.91   tsutsui 					a_tbl->at_wcnt--;
   3177        1.91   tsutsui 
   3178        1.91   tsutsui 				/*
   3179         1.7       gwr 				 * Invalidate the DTE that points to the
   3180         1.7       gwr 				 * B table and decrement the valid entry
   3181         1.7       gwr 				 * count of the A table.
   3182         1.7       gwr 				 */
   3183         1.1       gwr 				a_dte->attr.raw = MMU_DT_INVALID;
   3184         1.1       gwr 				a_tbl->at_ecnt--;
   3185         1.1       gwr 			}
   3186         1.1       gwr 	}
   3187        1.88   tsutsui 	if (nend < eva) {
   3188         1.7       gwr 		/*
   3189         1.7       gwr 		 * This block is executed if the range ends beyond a
   3190         1.7       gwr 		 * granularity boundary.
   3191         1.7       gwr 		 *
   3192         1.7       gwr 		 * First find the DTE which is responsible for mapping
   3193         1.7       gwr 		 * the start of the nearest (rounded down) granularity
   3194         1.7       gwr 		 * boundary.
   3195         1.7       gwr 		 */
   3196         1.1       gwr 		idx = MMU_TIA(nend);
   3197         1.1       gwr 		a_dte = &a_tbl->at_dtbl[idx];
   3198         1.7       gwr 
   3199         1.7       gwr 		/*
   3200         1.7       gwr 		 * If the DTE is valid then delegate the removal of the sub
   3201         1.7       gwr 		 * range to pmap_remove_b(), which can remove addresses at
   3202         1.7       gwr 		 * a finer granularity.
   3203         1.7       gwr 		 */
   3204         1.1       gwr 		if (MMU_VALID_DT(*a_dte)) {
   3205         1.7       gwr 			/*
   3206         1.7       gwr 			 * Find the B table manager for the entry
   3207         1.7       gwr 			 * and hand it to pmap_remove_b() along with
   3208         1.7       gwr 			 * the sub range.
   3209         1.7       gwr 			 */
   3210         1.7       gwr 			b_dte = mmu_ptov(a_dte->addr.raw);
   3211         1.1       gwr 			b_tbl = mmuB2tmgr(b_dte);
   3212        1.91   tsutsui 			bt_wired = b_tbl->bt_wcnt;
   3213         1.7       gwr 
   3214        1.88   tsutsui 			empty = pmap_remove_b(b_tbl, nend, eva);
   3215         1.7       gwr 
   3216         1.7       gwr 			/*
   3217        1.91   tsutsui 			 * If the child table no longer has wired entries,
   3218        1.91   tsutsui 			 * decrement wired entry count.
   3219        1.91   tsutsui 			 */
   3220        1.91   tsutsui 			if (bt_wired && b_tbl->bt_wcnt == 0)
   3221        1.91   tsutsui 				a_tbl->at_wcnt--;
   3222        1.91   tsutsui 			/*
   3223         1.7       gwr 			 * If the removal resulted in an empty B table,
   3224         1.7       gwr 			 * invalidate the DTE that points to it and decrement
   3225         1.7       gwr 			 * the valid entry count of the A table.
   3226         1.7       gwr 			 */
   3227         1.7       gwr 			if (empty) {
   3228         1.7       gwr 				a_dte->attr.raw = MMU_DT_INVALID;
   3229         1.7       gwr 				a_tbl->at_ecnt--;
   3230         1.7       gwr 			}
   3231         1.1       gwr 		}
   3232         1.1       gwr 	}
   3233         1.7       gwr 
   3234         1.7       gwr 	/*
   3235         1.7       gwr 	 * If there are no more entries in the A table, release it
   3236        1.95   thorpej 	 * back to the available pool and return true.
   3237         1.7       gwr 	 */
   3238         1.7       gwr 	if (a_tbl->at_ecnt == 0) {
   3239        1.91   tsutsui 		KASSERT(a_tbl->at_wcnt == 0);
   3240         1.7       gwr 		a_tbl->at_parent = NULL;
   3241        1.91   tsutsui 		if (!at_wired)
   3242        1.91   tsutsui 			TAILQ_REMOVE(&a_pool, a_tbl, at_link);
   3243         1.7       gwr 		TAILQ_INSERT_HEAD(&a_pool, a_tbl, at_link);
   3244        1.95   thorpej 		empty = true;
   3245         1.7       gwr 	} else {
   3246        1.91   tsutsui 		/*
   3247        1.91   tsutsui 		 * If the table doesn't have wired entries any longer
   3248        1.91   tsutsui 		 * but still has unwired entries, put it back into
   3249        1.91   tsutsui 		 * the available queue.
   3250        1.91   tsutsui 		 */
   3251        1.91   tsutsui 		if (at_wired && a_tbl->at_wcnt == 0)
   3252        1.91   tsutsui 			TAILQ_INSERT_TAIL(&a_pool, a_tbl, at_link);
   3253        1.95   thorpej 		empty = false;
   3254         1.7       gwr 	}
   3255         1.7       gwr 
   3256         1.7       gwr 	return empty;
   3257         1.1       gwr }
   3258         1.1       gwr 
   3259         1.1       gwr /* pmap_remove_b			INTERNAL
   3260         1.1       gwr  **
   3261         1.1       gwr  * Remove a range of addresses from an address space, trying to remove entire
   3262         1.1       gwr  * C tables if possible.
   3263         1.7       gwr  *
   3264        1.95   thorpej  * If the operation results in an empty B table, the function returns true.
   3265         1.1       gwr  */
   3266       1.113   tsutsui bool
   3267        1.88   tsutsui pmap_remove_b(b_tmgr_t *b_tbl, vaddr_t sva, vaddr_t eva)
   3268         1.1       gwr {
   3269        1.94   thorpej 	bool empty;
   3270         1.1       gwr 	int idx;
   3271        1.69       chs 	vaddr_t nstart, nend, rstart;
   3272         1.1       gwr 	c_tmgr_t *c_tbl;
   3273         1.1       gwr 	mmu_short_dte_t  *b_dte;
   3274         1.1       gwr 	mmu_short_pte_t  *c_dte;
   3275        1.91   tsutsui 	uint8_t bt_wired, ct_wired;
   3276       1.113   tsutsui 
   3277        1.88   tsutsui 	nstart = MMU_ROUND_UP_B(sva);
   3278        1.88   tsutsui 	nend = MMU_ROUND_B(eva);
   3279         1.1       gwr 
   3280        1.91   tsutsui 	bt_wired = b_tbl->bt_wcnt;
   3281        1.91   tsutsui 
   3282        1.88   tsutsui 	if (sva < nstart) {
   3283        1.88   tsutsui 		idx = MMU_TIB(sva);
   3284         1.1       gwr 		b_dte = &b_tbl->bt_dtbl[idx];
   3285         1.1       gwr 		if (MMU_VALID_DT(*b_dte)) {
   3286         1.7       gwr 			c_dte = mmu_ptov(MMU_DTE_PA(*b_dte));
   3287         1.1       gwr 			c_tbl = mmuC2tmgr(c_dte);
   3288        1.91   tsutsui 			ct_wired = c_tbl->ct_wcnt;
   3289        1.91   tsutsui 
   3290        1.88   tsutsui 			if (eva < nstart)
   3291        1.88   tsutsui 				empty = pmap_remove_c(c_tbl, sva, eva);
   3292         1.7       gwr 			else
   3293        1.88   tsutsui 				empty = pmap_remove_c(c_tbl, sva, nstart);
   3294        1.91   tsutsui 
   3295        1.91   tsutsui 			/*
   3296        1.91   tsutsui 			 * If the child table no longer has wired entries,
   3297        1.91   tsutsui 			 * decrement wired entry count.
   3298        1.91   tsutsui 			 */
   3299        1.91   tsutsui 			if (ct_wired && c_tbl->ct_wcnt == 0)
   3300        1.91   tsutsui 				b_tbl->bt_wcnt--;
   3301        1.91   tsutsui 
   3302         1.7       gwr 			if (empty) {
   3303         1.7       gwr 				b_dte->attr.raw = MMU_DT_INVALID;
   3304         1.7       gwr 				b_tbl->bt_ecnt--;
   3305         1.1       gwr 			}
   3306         1.1       gwr 		}
   3307         1.1       gwr 	}
   3308         1.1       gwr 	if (nstart < nend) {
   3309         1.1       gwr 		idx = MMU_TIB(nstart);
   3310         1.1       gwr 		b_dte = &b_tbl->bt_dtbl[idx];
   3311         1.1       gwr 		rstart = nstart;
   3312         1.1       gwr 		while (rstart < nend) {
   3313         1.1       gwr 			if (MMU_VALID_DT(*b_dte)) {
   3314         1.7       gwr 				c_dte = mmu_ptov(MMU_DTE_PA(*b_dte));
   3315         1.1       gwr 				c_tbl = mmuC2tmgr(c_dte);
   3316        1.91   tsutsui 				ct_wired = c_tbl->ct_wcnt;
   3317        1.91   tsutsui 
   3318        1.95   thorpej 				free_c_table(c_tbl, true);
   3319        1.91   tsutsui 
   3320        1.91   tsutsui 				/*
   3321        1.91   tsutsui 				 * All child entries has been removed.
   3322        1.91   tsutsui 				 * If there were any wired entries in it,
   3323        1.91   tsutsui 				 * decrement wired entry count.
   3324        1.91   tsutsui 				 */
   3325        1.91   tsutsui 				if (ct_wired)
   3326        1.91   tsutsui 					b_tbl->bt_wcnt--;
   3327        1.91   tsutsui 
   3328         1.1       gwr 				b_dte->attr.raw = MMU_DT_INVALID;
   3329         1.1       gwr 				b_tbl->bt_ecnt--;
   3330         1.1       gwr 			}
   3331         1.1       gwr 			b_dte++;
   3332         1.1       gwr 			rstart += MMU_TIB_RANGE;
   3333         1.1       gwr 		}
   3334         1.1       gwr 	}
   3335        1.88   tsutsui 	if (nend < eva) {
   3336         1.1       gwr 		idx = MMU_TIB(nend);
   3337         1.1       gwr 		b_dte = &b_tbl->bt_dtbl[idx];
   3338         1.1       gwr 		if (MMU_VALID_DT(*b_dte)) {
   3339         1.7       gwr 			c_dte = mmu_ptov(MMU_DTE_PA(*b_dte));
   3340         1.1       gwr 			c_tbl = mmuC2tmgr(c_dte);
   3341        1.91   tsutsui 			ct_wired = c_tbl->ct_wcnt;
   3342        1.88   tsutsui 			empty = pmap_remove_c(c_tbl, nend, eva);
   3343        1.91   tsutsui 
   3344        1.91   tsutsui 			/*
   3345        1.91   tsutsui 			 * If the child table no longer has wired entries,
   3346        1.91   tsutsui 			 * decrement wired entry count.
   3347        1.91   tsutsui 			 */
   3348        1.91   tsutsui 			if (ct_wired && c_tbl->ct_wcnt == 0)
   3349        1.91   tsutsui 				b_tbl->bt_wcnt--;
   3350        1.91   tsutsui 
   3351         1.7       gwr 			if (empty) {
   3352         1.7       gwr 				b_dte->attr.raw = MMU_DT_INVALID;
   3353         1.7       gwr 				b_tbl->bt_ecnt--;
   3354         1.7       gwr 			}
   3355         1.1       gwr 		}
   3356         1.1       gwr 	}
   3357         1.7       gwr 
   3358         1.7       gwr 	if (b_tbl->bt_ecnt == 0) {
   3359        1.91   tsutsui 		KASSERT(b_tbl->bt_wcnt == 0);
   3360         1.7       gwr 		b_tbl->bt_parent = NULL;
   3361        1.91   tsutsui 		if (!bt_wired)
   3362        1.91   tsutsui 			TAILQ_REMOVE(&b_pool, b_tbl, bt_link);
   3363         1.7       gwr 		TAILQ_INSERT_HEAD(&b_pool, b_tbl, bt_link);
   3364        1.95   thorpej 		empty = true;
   3365         1.7       gwr 	} else {
   3366        1.91   tsutsui 		/*
   3367        1.91   tsutsui 		 * If the table doesn't have wired entries any longer
   3368        1.91   tsutsui 		 * but still has unwired entries, put it back into
   3369        1.91   tsutsui 		 * the available queue.
   3370        1.91   tsutsui 		 */
   3371        1.91   tsutsui 		if (bt_wired && b_tbl->bt_wcnt == 0)
   3372        1.91   tsutsui 			TAILQ_INSERT_TAIL(&b_pool, b_tbl, bt_link);
   3373        1.91   tsutsui 
   3374        1.95   thorpej 		empty = false;
   3375         1.7       gwr 	}
   3376         1.7       gwr 
   3377         1.7       gwr 	return empty;
   3378         1.1       gwr }
   3379         1.1       gwr 
   3380         1.1       gwr /* pmap_remove_c			INTERNAL
   3381         1.1       gwr  **
   3382         1.1       gwr  * Remove a range of addresses from the given C table.
   3383         1.1       gwr  */
   3384       1.113   tsutsui bool
   3385        1.88   tsutsui pmap_remove_c(c_tmgr_t *c_tbl, vaddr_t sva, vaddr_t eva)
   3386         1.1       gwr {
   3387        1.94   thorpej 	bool empty;
   3388         1.1       gwr 	int idx;
   3389         1.1       gwr 	mmu_short_pte_t *c_pte;
   3390        1.91   tsutsui 	uint8_t ct_wired;
   3391       1.113   tsutsui 
   3392        1.91   tsutsui 	ct_wired = c_tbl->ct_wcnt;
   3393        1.91   tsutsui 
   3394        1.88   tsutsui 	idx = MMU_TIC(sva);
   3395         1.1       gwr 	c_pte = &c_tbl->ct_dtbl[idx];
   3396        1.92   tsutsui 	for (; sva < eva; sva += MMU_PAGE_SIZE, c_pte++) {
   3397         1.7       gwr 		if (MMU_VALID_DT(*c_pte)) {
   3398        1.91   tsutsui 			if (c_pte->attr.raw & MMU_SHORT_PTE_WIRED)
   3399        1.91   tsutsui 				c_tbl->ct_wcnt--;
   3400         1.1       gwr 			pmap_remove_pte(c_pte);
   3401         1.7       gwr 			c_tbl->ct_ecnt--;
   3402         1.7       gwr 		}
   3403         1.1       gwr 	}
   3404         1.7       gwr 
   3405         1.7       gwr 	if (c_tbl->ct_ecnt == 0) {
   3406        1.91   tsutsui 		KASSERT(c_tbl->ct_wcnt == 0);
   3407         1.7       gwr 		c_tbl->ct_parent = NULL;
   3408        1.91   tsutsui 		if (!ct_wired)
   3409        1.91   tsutsui 			TAILQ_REMOVE(&c_pool, c_tbl, ct_link);
   3410         1.9       gwr 		TAILQ_INSERT_HEAD(&c_pool, c_tbl, ct_link);
   3411        1.95   thorpej 		empty = true;
   3412         1.9       gwr 	} else {
   3413        1.91   tsutsui 		/*
   3414        1.91   tsutsui 		 * If the table doesn't have wired entries any longer
   3415        1.91   tsutsui 		 * but still has unwired entries, put it back into
   3416        1.91   tsutsui 		 * the available queue.
   3417        1.91   tsutsui 		 */
   3418        1.91   tsutsui 		if (ct_wired && c_tbl->ct_wcnt == 0)
   3419        1.91   tsutsui 			TAILQ_INSERT_TAIL(&c_pool, c_tbl, ct_link);
   3420        1.95   thorpej 		empty = false;
   3421         1.9       gwr 	}
   3422         1.7       gwr 
   3423         1.9       gwr 	return empty;
   3424         1.1       gwr }
   3425         1.1       gwr 
   3426         1.1       gwr /* pmap_bootstrap_alloc			INTERNAL
   3427         1.1       gwr  **
   3428         1.1       gwr  * Used internally for memory allocation at startup when malloc is not
   3429         1.1       gwr  * available.  This code will fail once it crosses the first memory
   3430         1.1       gwr  * bank boundary on the 3/80.  Hopefully by then however, the VM system
   3431         1.1       gwr  * will be in charge of allocation.
   3432         1.1       gwr  */
   3433         1.1       gwr void *
   3434        1.86       chs pmap_bootstrap_alloc(int size)
   3435         1.1       gwr {
   3436         1.1       gwr 	void *rtn;
   3437         1.1       gwr 
   3438         1.8       gwr #ifdef	PMAP_DEBUG
   3439        1.95   thorpej 	if (bootstrap_alloc_enabled == false) {
   3440         1.7       gwr 		mon_printf("pmap_bootstrap_alloc: disabled\n");
   3441         1.7       gwr 		sunmon_abort();
   3442         1.7       gwr 	}
   3443         1.7       gwr #endif
   3444         1.7       gwr 
   3445         1.1       gwr 	rtn = (void *) virtual_avail;
   3446         1.1       gwr 	virtual_avail += size;
   3447         1.1       gwr 
   3448         1.8       gwr #ifdef	PMAP_DEBUG
   3449         1.7       gwr 	if (virtual_avail > virtual_contig_end) {
   3450         1.7       gwr 		mon_printf("pmap_bootstrap_alloc: out of mem\n");
   3451         1.7       gwr 		sunmon_abort();
   3452         1.1       gwr 	}
   3453         1.7       gwr #endif
   3454         1.1       gwr 
   3455         1.1       gwr 	return rtn;
   3456         1.1       gwr }
   3457         1.1       gwr 
   3458         1.1       gwr /* pmap_bootstap_aalign			INTERNAL
   3459         1.1       gwr  **
   3460         1.7       gwr  * Used to insure that the next call to pmap_bootstrap_alloc() will
   3461         1.7       gwr  * return a chunk of memory aligned to the specified size.
   3462         1.8       gwr  *
   3463         1.8       gwr  * Note: This function will only support alignment sizes that are powers
   3464         1.8       gwr  * of two.
   3465         1.1       gwr  */
   3466       1.113   tsutsui void
   3467        1.86       chs pmap_bootstrap_aalign(int size)
   3468         1.1       gwr {
   3469         1.7       gwr 	int off;
   3470         1.7       gwr 
   3471         1.7       gwr 	off = virtual_avail & (size - 1);
   3472         1.7       gwr 	if (off) {
   3473        1.92   tsutsui 		(void)pmap_bootstrap_alloc(size - off);
   3474         1.1       gwr 	}
   3475         1.1       gwr }
   3476         1.7       gwr 
   3477         1.8       gwr /* pmap_pa_exists
   3478         1.8       gwr  **
   3479         1.8       gwr  * Used by the /dev/mem driver to see if a given PA is memory
   3480         1.8       gwr  * that can be mapped.  (The PA is not in a hole.)
   3481         1.8       gwr  */
   3482       1.113   tsutsui int
   3483        1.86       chs pmap_pa_exists(paddr_t pa)
   3484         1.8       gwr {
   3485        1.69       chs 	int i;
   3486        1.21       gwr 
   3487        1.21       gwr 	for (i = 0; i < SUN3X_NPHYS_RAM_SEGS; i++) {
   3488        1.21       gwr 		if ((pa >= avail_mem[i].pmem_start) &&
   3489        1.21       gwr 			(pa <  avail_mem[i].pmem_end))
   3490        1.92   tsutsui 			return 1;
   3491        1.21       gwr 		if (avail_mem[i].pmem_next == NULL)
   3492        1.21       gwr 			break;
   3493        1.21       gwr 	}
   3494        1.92   tsutsui 	return 0;
   3495         1.8       gwr }
   3496         1.8       gwr 
   3497        1.31       gwr /* Called only from locore.s and pmap.c */
   3498        1.86       chs void	_pmap_switch(pmap_t pmap);
   3499        1.31       gwr 
   3500        1.31       gwr /*
   3501        1.31       gwr  * _pmap_switch			INTERNAL
   3502        1.31       gwr  *
   3503        1.31       gwr  * This is called by locore.s:cpu_switch() when it is
   3504        1.31       gwr  * switching to a new process.  Load new translations.
   3505        1.31       gwr  * Note: done in-line by locore.s unless PMAP_DEBUG
   3506        1.24    jeremy  *
   3507        1.31       gwr  * Note that we do NOT allocate a context here, but
   3508        1.31       gwr  * share the "kernel only" context until we really
   3509        1.31       gwr  * need our own context for user-space mappings in
   3510        1.31       gwr  * pmap_enter_user().  [ s/context/mmu A table/ ]
   3511         1.1       gwr  */
   3512       1.113   tsutsui void
   3513        1.86       chs _pmap_switch(pmap_t pmap)
   3514         1.1       gwr {
   3515         1.7       gwr 	u_long rootpa;
   3516         1.7       gwr 
   3517        1.31       gwr 	/*
   3518        1.31       gwr 	 * Only do reload/flush if we have to.
   3519        1.31       gwr 	 * Note that if the old and new process
   3520        1.31       gwr 	 * were BOTH using the "null" context,
   3521        1.31       gwr 	 * then this will NOT flush the TLB.
   3522        1.31       gwr 	 */
   3523         1.7       gwr 	rootpa = pmap->pm_a_phys;
   3524        1.31       gwr 	if (kernel_crp.rp_addr != rootpa) {
   3525        1.31       gwr 		DPRINT(("pmap_activate(%p)\n", pmap));
   3526         1.7       gwr 		kernel_crp.rp_addr = rootpa;
   3527         1.7       gwr 		loadcrp(&kernel_crp);
   3528         1.8       gwr 		TBIAU();
   3529        1.31       gwr 	}
   3530        1.31       gwr }
   3531        1.31       gwr 
   3532        1.31       gwr /*
   3533        1.31       gwr  * Exported version of pmap_activate().  This is called from the
   3534        1.31       gwr  * machine-independent VM code when a process is given a new pmap.
   3535        1.76   thorpej  * If (p == curlwp) do like cpu_switch would do; otherwise just
   3536        1.31       gwr  * take this as notification that the process has a new pmap.
   3537        1.31       gwr  */
   3538       1.113   tsutsui void
   3539        1.86       chs pmap_activate(struct lwp *l)
   3540        1.31       gwr {
   3541        1.92   tsutsui 
   3542        1.76   thorpej 	if (l->l_proc == curproc) {
   3543        1.76   thorpej 		_pmap_switch(l->l_proc->p_vmspace->vm_map.pmap);
   3544         1.7       gwr 	}
   3545         1.1       gwr }
   3546         1.1       gwr 
   3547        1.30   thorpej /*
   3548        1.30   thorpej  * pmap_deactivate			INTERFACE
   3549        1.30   thorpej  **
   3550        1.30   thorpej  * This is called to deactivate the specified process's address space.
   3551        1.30   thorpej  */
   3552       1.113   tsutsui void
   3553        1.86       chs pmap_deactivate(struct lwp *l)
   3554         1.1       gwr {
   3555        1.92   tsutsui 
   3556        1.69       chs 	/* Nothing to do. */
   3557         1.1       gwr }
   3558         1.1       gwr 
   3559        1.17       gwr /*
   3560        1.28       gwr  * Fill in the sun3x-specific part of the kernel core header
   3561        1.28       gwr  * for dumpsys().  (See machdep.c for the rest.)
   3562        1.17       gwr  */
   3563       1.113   tsutsui void
   3564        1.86       chs pmap_kcore_hdr(struct sun3x_kcore_hdr *sh)
   3565        1.17       gwr {
   3566        1.17       gwr 	u_long spa, len;
   3567        1.17       gwr 	int i;
   3568        1.20   thorpej 
   3569        1.28       gwr 	sh->pg_frame = MMU_SHORT_PTE_BASEADDR;
   3570        1.28       gwr 	sh->pg_valid = MMU_DT_PAGE;
   3571        1.20   thorpej 	sh->contig_end = virtual_contig_end;
   3572        1.69       chs 	sh->kernCbase = (u_long)kernCbase;
   3573        1.20   thorpej 	for (i = 0; i < SUN3X_NPHYS_RAM_SEGS; i++) {
   3574        1.17       gwr 		spa = avail_mem[i].pmem_start;
   3575        1.25     veego 		spa = m68k_trunc_page(spa);
   3576        1.17       gwr 		len = avail_mem[i].pmem_end - spa;
   3577        1.25     veego 		len = m68k_round_page(len);
   3578        1.20   thorpej 		sh->ram_segs[i].start = spa;
   3579        1.20   thorpej 		sh->ram_segs[i].size  = len;
   3580        1.17       gwr 	}
   3581        1.17       gwr }
   3582        1.17       gwr 
   3583        1.81   thorpej 
   3584        1.81   thorpej /* pmap_virtual_space			INTERFACE
   3585        1.81   thorpej  **
   3586        1.81   thorpej  * Return the current available range of virtual addresses in the
   3587        1.81   thorpej  * arguuments provided.  Only really called once.
   3588        1.81   thorpej  */
   3589       1.113   tsutsui void
   3590        1.86       chs pmap_virtual_space(vaddr_t *vstart, vaddr_t *vend)
   3591        1.81   thorpej {
   3592        1.92   tsutsui 
   3593        1.81   thorpej 	*vstart = virtual_avail;
   3594        1.81   thorpej 	*vend = virtual_end;
   3595        1.81   thorpej }
   3596         1.1       gwr 
   3597        1.37       gwr /*
   3598        1.37       gwr  * Provide memory to the VM system.
   3599        1.37       gwr  *
   3600        1.37       gwr  * Assume avail_start is always in the
   3601        1.37       gwr  * first segment as pmap_bootstrap does.
   3602        1.37       gwr  */
   3603       1.113   tsutsui static void
   3604        1.86       chs pmap_page_upload(void)
   3605        1.37       gwr {
   3606        1.69       chs 	paddr_t	a, b;	/* memory range */
   3607        1.37       gwr 	int i;
   3608        1.37       gwr 
   3609        1.37       gwr 	/* Supply the memory in segments. */
   3610        1.37       gwr 	for (i = 0; i < SUN3X_NPHYS_RAM_SEGS; i++) {
   3611        1.37       gwr 		a = atop(avail_mem[i].pmem_start);
   3612        1.37       gwr 		b = atop(avail_mem[i].pmem_end);
   3613        1.37       gwr 		if (i == 0)
   3614        1.37       gwr 			a = atop(avail_start);
   3615        1.60   tsutsui 		if (avail_mem[i].pmem_end > avail_end)
   3616        1.60   tsutsui 			b = atop(avail_end);
   3617        1.37       gwr 
   3618        1.39   thorpej 		uvm_page_physload(a, b, a, b, VM_FREELIST_DEFAULT);
   3619        1.37       gwr 
   3620        1.37       gwr 		if (avail_mem[i].pmem_next == NULL)
   3621        1.37       gwr 			break;
   3622        1.37       gwr 	}
   3623         1.1       gwr }
   3624         1.8       gwr 
   3625         1.8       gwr /* pmap_count			INTERFACE
   3626         1.8       gwr  **
   3627         1.8       gwr  * Return the number of resident (valid) pages in the given pmap.
   3628         1.8       gwr  *
   3629         1.8       gwr  * Note:  If this function is handed the kernel map, it will report
   3630         1.8       gwr  * that it has no mappings.  Hopefully the VM system won't ask for kernel
   3631         1.8       gwr  * map statistics.
   3632         1.8       gwr  */
   3633       1.113   tsutsui segsz_t
   3634        1.86       chs pmap_count(pmap_t pmap, int type)
   3635         1.8       gwr {
   3636         1.8       gwr 	u_int     count;
   3637         1.8       gwr 	int       a_idx, b_idx;
   3638         1.8       gwr 	a_tmgr_t *a_tbl;
   3639         1.8       gwr 	b_tmgr_t *b_tbl;
   3640         1.8       gwr 	c_tmgr_t *c_tbl;
   3641         1.8       gwr 
   3642         1.8       gwr 	/*
   3643         1.8       gwr 	 * If the pmap does not have its own A table manager, it has no
   3644         1.8       gwr 	 * valid entires.
   3645         1.8       gwr 	 */
   3646         1.8       gwr 	if (pmap->pm_a_tmgr == NULL)
   3647         1.8       gwr 		return 0;
   3648         1.8       gwr 
   3649         1.8       gwr 	a_tbl = pmap->pm_a_tmgr;
   3650         1.8       gwr 
   3651         1.8       gwr 	count = 0;
   3652       1.111   tsutsui 	for (a_idx = 0; a_idx < MMU_TIA(KERNBASE3X); a_idx++) {
   3653         1.8       gwr 	    if (MMU_VALID_DT(a_tbl->at_dtbl[a_idx])) {
   3654         1.8       gwr 	        b_tbl = mmuB2tmgr(mmu_ptov(a_tbl->at_dtbl[a_idx].addr.raw));
   3655         1.8       gwr 	        for (b_idx = 0; b_idx < MMU_B_TBL_SIZE; b_idx++) {
   3656         1.8       gwr 	            if (MMU_VALID_DT(b_tbl->bt_dtbl[b_idx])) {
   3657         1.8       gwr 	                c_tbl = mmuC2tmgr(
   3658         1.8       gwr 	                    mmu_ptov(MMU_DTE_PA(b_tbl->bt_dtbl[b_idx])));
   3659         1.8       gwr 	                if (type == 0)
   3660         1.8       gwr 	                    /*
   3661         1.8       gwr 	                     * A resident entry count has been requested.
   3662         1.8       gwr 	                     */
   3663         1.8       gwr 	                    count += c_tbl->ct_ecnt;
   3664         1.8       gwr 	                else
   3665         1.8       gwr 	                    /*
   3666         1.8       gwr 	                     * A wired entry count has been requested.
   3667         1.8       gwr 	                     */
   3668         1.8       gwr 	                    count += c_tbl->ct_wcnt;
   3669         1.8       gwr 	            }
   3670         1.8       gwr 	        }
   3671         1.8       gwr 	    }
   3672         1.8       gwr 	}
   3673         1.8       gwr 
   3674         1.8       gwr 	return count;
   3675         1.8       gwr }
   3676         1.8       gwr 
   3677         1.1       gwr /************************ SUN3 COMPATIBILITY ROUTINES ********************
   3678         1.1       gwr  * The following routines are only used by DDB for tricky kernel text    *
   3679         1.1       gwr  * text operations in db_memrw.c.  They are provided for sun3            *
   3680         1.1       gwr  * compatibility.                                                        *
   3681         1.1       gwr  *************************************************************************/
   3682         1.1       gwr /* get_pte			INTERNAL
   3683         1.1       gwr  **
   3684         1.1       gwr  * Return the page descriptor the describes the kernel mapping
   3685         1.1       gwr  * of the given virtual address.
   3686         1.1       gwr  */
   3687        1.86       chs extern u_long ptest_addr(u_long);	/* XXX: locore.s */
   3688       1.113   tsutsui u_int
   3689        1.86       chs get_pte(vaddr_t va)
   3690        1.13       gwr {
   3691        1.13       gwr 	u_long pte_pa;
   3692        1.13       gwr 	mmu_short_pte_t *pte;
   3693        1.13       gwr 
   3694        1.13       gwr 	/* Get the physical address of the PTE */
   3695        1.13       gwr 	pte_pa = ptest_addr(va & ~PGOFSET);
   3696        1.13       gwr 
   3697        1.13       gwr 	/* Convert to a virtual address... */
   3698       1.111   tsutsui 	pte = (mmu_short_pte_t *) (KERNBASE3X + pte_pa);
   3699        1.13       gwr 
   3700        1.13       gwr 	/* Make sure it is in our level-C tables... */
   3701        1.13       gwr 	if ((pte < kernCbase) ||
   3702        1.13       gwr 		(pte >= &mmuCbase[NUM_USER_PTES]))
   3703        1.13       gwr 		return 0;
   3704        1.13       gwr 
   3705        1.13       gwr 	/* ... and just return its contents. */
   3706        1.13       gwr 	return (pte->attr.raw);
   3707        1.13       gwr }
   3708        1.13       gwr 
   3709         1.1       gwr 
   3710         1.1       gwr /* set_pte			INTERNAL
   3711         1.1       gwr  **
   3712         1.1       gwr  * Set the page descriptor that describes the kernel mapping
   3713         1.1       gwr  * of the given virtual address.
   3714         1.1       gwr  */
   3715       1.113   tsutsui void
   3716        1.86       chs set_pte(vaddr_t va, u_int pte)
   3717         1.1       gwr {
   3718         1.1       gwr 	u_long idx;
   3719         1.1       gwr 
   3720       1.111   tsutsui 	if (va < KERNBASE3X)
   3721         1.7       gwr 		return;
   3722         1.7       gwr 
   3723       1.111   tsutsui 	idx = (unsigned long) m68k_btop(va - KERNBASE3X);
   3724         1.1       gwr 	kernCbase[idx].attr.raw = pte;
   3725        1.33       gwr 	TBIS(va);
   3726         1.1       gwr }
   3727        1.42        is 
   3728        1.42        is /*
   3729        1.42        is  *	Routine:        pmap_procwr
   3730       1.113   tsutsui  *
   3731        1.42        is  *	Function:
   3732        1.42        is  *		Synchronize caches corresponding to [addr, addr+len) in p.
   3733       1.113   tsutsui  */
   3734       1.113   tsutsui void
   3735        1.86       chs pmap_procwr(struct proc *p, vaddr_t va, size_t len)
   3736        1.42        is {
   3737        1.92   tsutsui 
   3738        1.42        is 	(void)cachectl1(0x80000004, va, len, p);
   3739        1.42        is }
   3740        1.42        is 
   3741         1.7       gwr 
   3742         1.8       gwr #ifdef	PMAP_DEBUG
   3743         1.7       gwr /************************** DEBUGGING ROUTINES **************************
   3744         1.7       gwr  * The following routines are meant to be an aid to debugging the pmap  *
   3745         1.7       gwr  * system.  They are callable from the DDB command line and should be   *
   3746         1.7       gwr  * prepared to be handed unstable or incomplete states of the system.   *
   3747         1.7       gwr  ************************************************************************/
   3748         1.7       gwr 
   3749         1.7       gwr /* pv_list
   3750         1.7       gwr  **
   3751         1.7       gwr  * List all pages found on the pv list for the given physical page.
   3752         1.8       gwr  * To avoid endless loops, the listing will stop at the end of the list
   3753         1.7       gwr  * or after 'n' entries - whichever comes first.
   3754         1.7       gwr  */
   3755       1.113   tsutsui void
   3756        1.86       chs pv_list(paddr_t pa, int n)
   3757         1.7       gwr {
   3758         1.7       gwr 	int  idx;
   3759        1.69       chs 	vaddr_t va;
   3760         1.7       gwr 	pv_t *pv;
   3761         1.7       gwr 	c_tmgr_t *c_tbl;
   3762         1.7       gwr 	pmap_t pmap;
   3763       1.113   tsutsui 
   3764         1.7       gwr 	pv = pa2pv(pa);
   3765         1.7       gwr 	idx = pv->pv_idx;
   3766        1.69       chs 	for (; idx != PVE_EOL && n > 0; idx = pvebase[idx].pve_next, n--) {
   3767         1.8       gwr 		va = pmap_get_pteinfo(idx, &pmap, &c_tbl);
   3768         1.7       gwr 		printf("idx %d, pmap 0x%x, va 0x%x, c_tbl %x\n",
   3769         1.7       gwr 			idx, (u_int) pmap, (u_int) va, (u_int) c_tbl);
   3770         1.7       gwr 	}
   3771         1.7       gwr }
   3772         1.8       gwr #endif	/* PMAP_DEBUG */
   3773         1.1       gwr 
   3774         1.1       gwr #ifdef NOT_YET
   3775         1.1       gwr /* and maybe not ever */
   3776         1.1       gwr /************************** LOW-LEVEL ROUTINES **************************
   3777        1.78       wiz  * These routines will eventually be re-written into assembly and placed*
   3778         1.1       gwr  * in locore.s.  They are here now as stubs so that the pmap module can *
   3779         1.1       gwr  * be linked as a standalone user program for testing.                  *
   3780         1.1       gwr  ************************************************************************/
   3781         1.1       gwr /* flush_atc_crp			INTERNAL
   3782         1.1       gwr  **
   3783         1.1       gwr  * Flush all page descriptors derived from the given CPU Root Pointer
   3784         1.1       gwr  * (CRP), or 'A' table as it is known here, from the 68851's automatic
   3785         1.1       gwr  * cache.
   3786         1.1       gwr  */
   3787       1.113   tsutsui void
   3788        1.86       chs flush_atc_crp(int a_tbl)
   3789         1.1       gwr {
   3790         1.1       gwr 	mmu_long_rp_t rp;
   3791         1.1       gwr 
   3792         1.1       gwr 	/* Create a temporary root table pointer that points to the
   3793         1.1       gwr 	 * given A table.
   3794         1.1       gwr 	 */
   3795         1.1       gwr 	rp.attr.raw = ~MMU_LONG_RP_LU;
   3796         1.1       gwr 	rp.addr.raw = (unsigned int) a_tbl;
   3797         1.1       gwr 
   3798         1.1       gwr 	mmu_pflushr(&rp);
   3799         1.1       gwr 	/* mmu_pflushr:
   3800         1.1       gwr 	 * 	movel   sp(4)@,a0
   3801         1.1       gwr 	 * 	pflushr a0@
   3802         1.1       gwr 	 *	rts
   3803         1.1       gwr 	 */
   3804         1.1       gwr }
   3805         1.1       gwr #endif /* NOT_YET */
   3806