Home | History | Annotate | Line # | Download | only in sun3x
pmap.c revision 1.50.2.5
      1  1.50.2.5   bouyer /*	$NetBSD: pmap.c,v 1.50.2.5 2001/02/11 19:12:53 bouyer Exp $	*/
      2       1.1      gwr 
      3       1.1      gwr /*-
      4      1.10   jeremy  * Copyright (c) 1996, 1997 The NetBSD Foundation, Inc.
      5       1.1      gwr  * All rights reserved.
      6       1.1      gwr  *
      7       1.1      gwr  * This code is derived from software contributed to The NetBSD Foundation
      8       1.1      gwr  * by Jeremy Cooper.
      9       1.1      gwr  *
     10       1.1      gwr  * Redistribution and use in source and binary forms, with or without
     11       1.1      gwr  * modification, are permitted provided that the following conditions
     12       1.1      gwr  * are met:
     13       1.1      gwr  * 1. Redistributions of source code must retain the above copyright
     14       1.1      gwr  *    notice, this list of conditions and the following disclaimer.
     15       1.1      gwr  * 2. Redistributions in binary form must reproduce the above copyright
     16       1.1      gwr  *    notice, this list of conditions and the following disclaimer in the
     17       1.1      gwr  *    documentation and/or other materials provided with the distribution.
     18       1.1      gwr  * 3. All advertising materials mentioning features or use of this software
     19       1.1      gwr  *    must display the following acknowledgement:
     20       1.1      gwr  *        This product includes software developed by the NetBSD
     21       1.1      gwr  *        Foundation, Inc. and its contributors.
     22       1.1      gwr  * 4. Neither the name of The NetBSD Foundation nor the names of its
     23       1.1      gwr  *    contributors may be used to endorse or promote products derived
     24       1.1      gwr  *    from this software without specific prior written permission.
     25       1.1      gwr  *
     26       1.1      gwr  * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
     27       1.1      gwr  * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
     28       1.1      gwr  * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
     29       1.1      gwr  * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
     30       1.1      gwr  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
     31       1.1      gwr  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
     32       1.1      gwr  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
     33       1.1      gwr  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
     34       1.1      gwr  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
     35       1.1      gwr  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
     36       1.1      gwr  * POSSIBILITY OF SUCH DAMAGE.
     37       1.1      gwr  */
     38       1.1      gwr 
     39       1.1      gwr /*
     40       1.1      gwr  * XXX These comments aren't quite accurate.  Need to change.
     41       1.1      gwr  * The sun3x uses the MC68851 Memory Management Unit, which is built
     42       1.1      gwr  * into the CPU.  The 68851 maps virtual to physical addresses using
     43       1.1      gwr  * a multi-level table lookup, which is stored in the very memory that
     44       1.1      gwr  * it maps.  The number of levels of lookup is configurable from one
     45       1.1      gwr  * to four.  In this implementation, we use three, named 'A' through 'C'.
     46       1.1      gwr  *
     47       1.1      gwr  * The MMU translates virtual addresses into physical addresses by
     48       1.1      gwr  * traversing these tables in a proccess called a 'table walk'.  The most
     49       1.1      gwr  * significant 7 bits of the Virtual Address ('VA') being translated are
     50       1.1      gwr  * used as an index into the level A table, whose base in physical memory
     51       1.1      gwr  * is stored in a special MMU register, the 'CPU Root Pointer' or CRP.  The
     52       1.1      gwr  * address found at that index in the A table is used as the base
     53       1.1      gwr  * address for the next table, the B table.  The next six bits of the VA are
     54       1.1      gwr  * used as an index into the B table, which in turn gives the base address
     55       1.1      gwr  * of the third and final C table.
     56       1.1      gwr  *
     57       1.1      gwr  * The next six bits of the VA are used as an index into the C table to
     58       1.1      gwr  * locate a Page Table Entry (PTE).  The PTE is a physical address in memory
     59       1.1      gwr  * to which the remaining 13 bits of the VA are added, producing the
     60       1.1      gwr  * mapped physical address.
     61       1.1      gwr  *
     62       1.1      gwr  * To map the entire memory space in this manner would require 2114296 bytes
     63       1.1      gwr  * of page tables per process - quite expensive.  Instead we will
     64       1.1      gwr  * allocate a fixed but considerably smaller space for the page tables at
     65       1.1      gwr  * the time the VM system is initialized.  When the pmap code is asked by
     66       1.1      gwr  * the kernel to map a VA to a PA, it allocates tables as needed from this
     67       1.1      gwr  * pool.  When there are no more tables in the pool, tables are stolen
     68       1.1      gwr  * from the oldest mapped entries in the tree.  This is only possible
     69       1.1      gwr  * because all memory mappings are stored in the kernel memory map
     70       1.1      gwr  * structures, independent of the pmap structures.  A VA which references
     71       1.1      gwr  * one of these invalidated maps will cause a page fault.  The kernel
     72       1.1      gwr  * will determine that the page fault was caused by a task using a valid
     73       1.1      gwr  * VA, but for some reason (which does not concern it), that address was
     74       1.1      gwr  * not mapped.  It will ask the pmap code to re-map the entry and then
     75       1.1      gwr  * it will resume executing the faulting task.
     76       1.1      gwr  *
     77       1.1      gwr  * In this manner the most efficient use of the page table space is
     78       1.1      gwr  * achieved.  Tasks which do not execute often will have their tables
     79       1.1      gwr  * stolen and reused by tasks which execute more frequently.  The best
     80       1.1      gwr  * size for the page table pool will probably be determined by
     81       1.1      gwr  * experimentation.
     82       1.1      gwr  *
     83       1.1      gwr  * You read all of the comments so far.  Good for you.
     84       1.1      gwr  * Now go play!
     85       1.1      gwr  */
     86       1.1      gwr 
     87       1.1      gwr /*** A Note About the 68851 Address Translation Cache
     88       1.1      gwr  * The MC68851 has a 64 entry cache, called the Address Translation Cache
     89       1.1      gwr  * or 'ATC'.  This cache stores the most recently used page descriptors
     90       1.1      gwr  * accessed by the MMU when it does translations.  Using a marker called a
     91       1.1      gwr  * 'task alias' the MMU can store the descriptors from 8 different table
     92       1.1      gwr  * spaces concurrently.  The task alias is associated with the base
     93       1.1      gwr  * address of the level A table of that address space.  When an address
     94       1.1      gwr  * space is currently active (the CRP currently points to its A table)
     95       1.1      gwr  * the only cached descriptors that will be obeyed are ones which have a
     96       1.1      gwr  * matching task alias of the current space associated with them.
     97       1.1      gwr  *
     98       1.1      gwr  * Since the cache is always consulted before any table lookups are done,
     99       1.1      gwr  * it is important that it accurately reflect the state of the MMU tables.
    100       1.1      gwr  * Whenever a change has been made to a table that has been loaded into
    101       1.1      gwr  * the MMU, the code must be sure to flush any cached entries that are
    102       1.1      gwr  * affected by the change.  These instances are documented in the code at
    103       1.1      gwr  * various points.
    104       1.1      gwr  */
    105       1.1      gwr /*** A Note About the Note About the 68851 Address Translation Cache
    106       1.1      gwr  * 4 months into this code I discovered that the sun3x does not have
    107       1.1      gwr  * a MC68851 chip. Instead, it has a version of this MMU that is part of the
    108       1.1      gwr  * the 68030 CPU.
    109       1.1      gwr  * All though it behaves very similarly to the 68851, it only has 1 task
    110       1.8      gwr  * alias and a 22 entry cache.  So sadly (or happily), the first paragraph
    111       1.8      gwr  * of the previous note does not apply to the sun3x pmap.
    112       1.1      gwr  */
    113      1.45      gwr 
    114      1.45      gwr #include "opt_ddb.h"
    115       1.1      gwr 
    116       1.1      gwr #include <sys/param.h>
    117       1.1      gwr #include <sys/systm.h>
    118       1.1      gwr #include <sys/proc.h>
    119       1.1      gwr #include <sys/malloc.h>
    120  1.50.2.2   bouyer #include <sys/pool.h>
    121       1.1      gwr #include <sys/user.h>
    122       1.1      gwr #include <sys/queue.h>
    123      1.20  thorpej #include <sys/kcore.h>
    124       1.1      gwr 
    125      1.38      gwr #include <uvm/uvm.h>
    126      1.43      mrg 
    127      1.40      gwr #define PAGER_SVA (uvm.pager_sva)
    128      1.40      gwr #define PAGER_EVA (uvm.pager_eva)
    129       1.1      gwr 
    130       1.1      gwr #include <machine/cpu.h>
    131      1.17      gwr #include <machine/kcore.h>
    132      1.33      gwr #include <machine/mon.h>
    133       1.1      gwr #include <machine/pmap.h>
    134       1.1      gwr #include <machine/pte.h>
    135      1.37      gwr #include <machine/vmparam.h>
    136      1.33      gwr 
    137      1.33      gwr #include <sun3/sun3/cache.h>
    138      1.33      gwr #include <sun3/sun3/machdep.h>
    139       1.1      gwr 
    140       1.1      gwr #include "pmap_pvt.h"
    141       1.1      gwr 
    142       1.1      gwr /* XXX - What headers declare these? */
    143       1.1      gwr extern struct pcb *curpcb;
    144       1.1      gwr extern int physmem;
    145       1.7      gwr 
    146       1.1      gwr /* Defined in locore.s */
    147       1.1      gwr extern char kernel_text[];
    148       1.1      gwr 
    149       1.1      gwr /* Defined by the linker */
    150       1.1      gwr extern char etext[], edata[], end[];
    151       1.1      gwr extern char *esym;	/* DDB */
    152       1.1      gwr 
    153       1.7      gwr /*************************** DEBUGGING DEFINITIONS ***********************
    154       1.7      gwr  * Macros, preprocessor defines and variables used in debugging can make *
    155       1.7      gwr  * code hard to read.  Anything used exclusively for debugging purposes  *
    156       1.7      gwr  * is defined here to avoid having such mess scattered around the file.  *
    157       1.7      gwr  *************************************************************************/
    158       1.8      gwr #ifdef	PMAP_DEBUG
    159       1.7      gwr /*
    160       1.7      gwr  * To aid the debugging process, macros should be expanded into smaller steps
    161       1.7      gwr  * that accomplish the same goal, yet provide convenient places for placing
    162       1.8      gwr  * breakpoints.  When this code is compiled with PMAP_DEBUG mode defined, the
    163       1.7      gwr  * 'INLINE' keyword is defined to an empty string.  This way, any function
    164       1.7      gwr  * defined to be a 'static INLINE' will become 'outlined' and compiled as
    165       1.7      gwr  * a separate function, which is much easier to debug.
    166       1.7      gwr  */
    167       1.7      gwr #define	INLINE	/* nothing */
    168       1.7      gwr 
    169       1.1      gwr /*
    170       1.7      gwr  * It is sometimes convenient to watch the activity of a particular table
    171       1.7      gwr  * in the system.  The following variables are used for that purpose.
    172       1.1      gwr  */
    173       1.7      gwr a_tmgr_t *pmap_watch_atbl = 0;
    174       1.7      gwr b_tmgr_t *pmap_watch_btbl = 0;
    175       1.7      gwr c_tmgr_t *pmap_watch_ctbl = 0;
    176       1.1      gwr 
    177       1.7      gwr int pmap_debug = 0;
    178       1.7      gwr #define DPRINT(args) if (pmap_debug) printf args
    179       1.7      gwr 
    180       1.7      gwr #else	/********** Stuff below is defined if NOT debugging **************/
    181       1.7      gwr 
    182       1.7      gwr #define	INLINE	inline
    183      1.10   jeremy #define DPRINT(args)  /* nada */
    184       1.7      gwr 
    185      1.10   jeremy #endif	/* PMAP_DEBUG */
    186       1.7      gwr /*********************** END OF DEBUGGING DEFINITIONS ********************/
    187       1.1      gwr 
    188       1.1      gwr /*** Management Structure - Memory Layout
    189       1.1      gwr  * For every MMU table in the sun3x pmap system there must be a way to
    190       1.1      gwr  * manage it; we must know which process is using it, what other tables
    191       1.1      gwr  * depend on it, and whether or not it contains any locked pages.  This
    192       1.1      gwr  * is solved by the creation of 'table management'  or 'tmgr'
    193       1.1      gwr  * structures.  One for each MMU table in the system.
    194       1.1      gwr  *
    195       1.1      gwr  *                        MAP OF MEMORY USED BY THE PMAP SYSTEM
    196       1.1      gwr  *
    197       1.1      gwr  *      towards lower memory
    198       1.1      gwr  * kernAbase -> +-------------------------------------------------------+
    199       1.1      gwr  *              | Kernel     MMU A level table                          |
    200       1.1      gwr  * kernBbase -> +-------------------------------------------------------+
    201       1.1      gwr  *              | Kernel     MMU B level tables                         |
    202       1.1      gwr  * kernCbase -> +-------------------------------------------------------+
    203       1.1      gwr  *              |                                                       |
    204       1.1      gwr  *              | Kernel     MMU C level tables                         |
    205       1.1      gwr  *              |                                                       |
    206       1.7      gwr  * mmuCbase  -> +-------------------------------------------------------+
    207       1.7      gwr  *              | User       MMU C level tables                         |
    208       1.1      gwr  * mmuAbase  -> +-------------------------------------------------------+
    209       1.1      gwr  *              |                                                       |
    210       1.1      gwr  *              | User       MMU A level tables                         |
    211       1.1      gwr  *              |                                                       |
    212       1.1      gwr  * mmuBbase  -> +-------------------------------------------------------+
    213       1.1      gwr  *              | User       MMU B level tables                         |
    214       1.1      gwr  * tmgrAbase -> +-------------------------------------------------------+
    215       1.1      gwr  *              |  TMGR A level table structures                        |
    216       1.1      gwr  * tmgrBbase -> +-------------------------------------------------------+
    217       1.1      gwr  *              |  TMGR B level table structures                        |
    218       1.1      gwr  * tmgrCbase -> +-------------------------------------------------------+
    219       1.1      gwr  *              |  TMGR C level table structures                        |
    220       1.1      gwr  * pvbase    -> +-------------------------------------------------------+
    221       1.1      gwr  *              |  Physical to Virtual mapping table (list heads)       |
    222       1.1      gwr  * pvebase   -> +-------------------------------------------------------+
    223       1.1      gwr  *              |  Physical to Virtual mapping table (list elements)    |
    224       1.1      gwr  *              |                                                       |
    225       1.1      gwr  *              +-------------------------------------------------------+
    226       1.1      gwr  *      towards higher memory
    227       1.1      gwr  *
    228       1.1      gwr  * For every A table in the MMU A area, there will be a corresponding
    229       1.1      gwr  * a_tmgr structure in the TMGR A area.  The same will be true for
    230       1.1      gwr  * the B and C tables.  This arrangement will make it easy to find the
    231       1.1      gwr  * controling tmgr structure for any table in the system by use of
    232       1.1      gwr  * (relatively) simple macros.
    233       1.1      gwr  */
    234       1.7      gwr 
    235       1.7      gwr /*
    236       1.8      gwr  * Global variables for storing the base addresses for the areas
    237       1.1      gwr  * labeled above.
    238       1.1      gwr  */
    239       1.7      gwr static vm_offset_t  	kernAphys;
    240       1.1      gwr static mmu_long_dte_t	*kernAbase;
    241       1.1      gwr static mmu_short_dte_t	*kernBbase;
    242       1.1      gwr static mmu_short_pte_t	*kernCbase;
    243      1.15      gwr static mmu_short_pte_t	*mmuCbase;
    244      1.15      gwr static mmu_short_dte_t	*mmuBbase;
    245       1.1      gwr static mmu_long_dte_t	*mmuAbase;
    246       1.1      gwr static a_tmgr_t		*Atmgrbase;
    247       1.1      gwr static b_tmgr_t		*Btmgrbase;
    248       1.1      gwr static c_tmgr_t		*Ctmgrbase;
    249      1.15      gwr static pv_t 		*pvbase;
    250       1.1      gwr static pv_elem_t	*pvebase;
    251      1.15      gwr struct pmap 		kernel_pmap;
    252       1.1      gwr 
    253       1.8      gwr /*
    254       1.8      gwr  * This holds the CRP currently loaded into the MMU.
    255       1.8      gwr  */
    256       1.8      gwr struct mmu_rootptr kernel_crp;
    257       1.8      gwr 
    258       1.8      gwr /*
    259       1.8      gwr  * Just all around global variables.
    260       1.1      gwr  */
    261       1.1      gwr static TAILQ_HEAD(a_pool_head_struct, a_tmgr_struct) a_pool;
    262       1.1      gwr static TAILQ_HEAD(b_pool_head_struct, b_tmgr_struct) b_pool;
    263       1.1      gwr static TAILQ_HEAD(c_pool_head_struct, c_tmgr_struct) c_pool;
    264       1.7      gwr 
    265       1.7      gwr 
    266       1.7      gwr /*
    267       1.7      gwr  * Flags used to mark the safety/availability of certain operations or
    268       1.7      gwr  * resources.
    269       1.7      gwr  */
    270      1.23   jeremy static boolean_t pv_initialized = FALSE, /* PV system has been initialized. */
    271      1.23   jeremy        bootstrap_alloc_enabled = FALSE; /*Safe to use pmap_bootstrap_alloc().*/
    272      1.24   jeremy int tmp_vpages_inuse;	/* Temporary virtual pages are in use */
    273       1.1      gwr 
    274       1.1      gwr /*
    275       1.1      gwr  * XXX:  For now, retain the traditional variables that were
    276       1.1      gwr  * used in the old pmap/vm interface (without NONCONTIG).
    277       1.1      gwr  */
    278       1.1      gwr /* Kernel virtual address space available: */
    279       1.1      gwr vm_offset_t	virtual_avail, virtual_end;
    280       1.1      gwr /* Physical address space available: */
    281       1.1      gwr vm_offset_t	avail_start, avail_end;
    282       1.1      gwr 
    283       1.7      gwr /* This keep track of the end of the contiguously mapped range. */
    284       1.7      gwr vm_offset_t virtual_contig_end;
    285       1.7      gwr 
    286       1.7      gwr /* Physical address used by pmap_next_page() */
    287       1.7      gwr vm_offset_t avail_next;
    288       1.7      gwr 
    289       1.7      gwr /* These are used by pmap_copy_page(), etc. */
    290      1.24   jeremy vm_offset_t tmp_vpages[2];
    291       1.1      gwr 
    292  1.50.2.2   bouyer /* memory pool for pmap structures */
    293  1.50.2.2   bouyer struct pool	pmap_pmap_pool;
    294  1.50.2.2   bouyer 
    295       1.7      gwr /*
    296       1.7      gwr  * The 3/80 is the only member of the sun3x family that has non-contiguous
    297       1.1      gwr  * physical memory.  Memory is divided into 4 banks which are physically
    298       1.1      gwr  * locatable on the system board.  Although the size of these banks varies
    299       1.1      gwr  * with the size of memory they contain, their base addresses are
    300       1.1      gwr  * permenently fixed.  The following structure, which describes these
    301       1.1      gwr  * banks, is initialized by pmap_bootstrap() after it reads from a similar
    302       1.1      gwr  * structure provided by the ROM Monitor.
    303       1.1      gwr  *
    304       1.1      gwr  * For the other machines in the sun3x architecture which do have contiguous
    305       1.1      gwr  * RAM, this list will have only one entry, which will describe the entire
    306       1.1      gwr  * range of available memory.
    307       1.1      gwr  */
    308      1.20  thorpej struct pmap_physmem_struct avail_mem[SUN3X_NPHYS_RAM_SEGS];
    309       1.1      gwr u_int total_phys_mem;
    310       1.1      gwr 
    311       1.7      gwr /*************************************************************************/
    312       1.7      gwr 
    313       1.7      gwr /*
    314       1.7      gwr  * XXX - Should "tune" these based on statistics.
    315       1.7      gwr  *
    316       1.7      gwr  * My first guess about the relative numbers of these needed is
    317       1.7      gwr  * based on the fact that a "typical" process will have several
    318       1.7      gwr  * pages mapped at low virtual addresses (text, data, bss), then
    319       1.7      gwr  * some mapped shared libraries, and then some stack pages mapped
    320       1.7      gwr  * near the high end of the VA space.  Each process can use only
    321       1.7      gwr  * one A table, and most will use only two B tables (maybe three)
    322       1.7      gwr  * and probably about four C tables.  Therefore, the first guess
    323       1.7      gwr  * at the relative numbers of these needed is 1:2:4 -gwr
    324       1.7      gwr  *
    325       1.7      gwr  * The number of C tables needed is closely related to the amount
    326       1.7      gwr  * of physical memory available plus a certain amount attributable
    327       1.7      gwr  * to the use of double mappings.  With a few simulation statistics
    328       1.7      gwr  * we can find a reasonably good estimation of this unknown value.
    329       1.7      gwr  * Armed with that and the above ratios, we have a good idea of what
    330       1.7      gwr  * is needed at each level. -j
    331       1.7      gwr  *
    332       1.7      gwr  * Note: It is not physical memory memory size, but the total mapped
    333       1.7      gwr  * virtual space required by the combined working sets of all the
    334       1.7      gwr  * currently _runnable_ processes.  (Sleeping ones don't count.)
    335       1.7      gwr  * The amount of physical memory should be irrelevant. -gwr
    336       1.7      gwr  */
    337      1.22   jeremy #ifdef	FIXED_NTABLES
    338       1.7      gwr #define NUM_A_TABLES	16
    339       1.7      gwr #define NUM_B_TABLES	32
    340       1.7      gwr #define NUM_C_TABLES	64
    341      1.22   jeremy #else
    342      1.22   jeremy unsigned int	NUM_A_TABLES, NUM_B_TABLES, NUM_C_TABLES;
    343      1.22   jeremy #endif	/* FIXED_NTABLES */
    344       1.7      gwr 
    345       1.7      gwr /*
    346       1.7      gwr  * This determines our total virtual mapping capacity.
    347       1.7      gwr  * Yes, it is a FIXED value so we can pre-allocate.
    348       1.7      gwr  */
    349       1.7      gwr #define NUM_USER_PTES	(NUM_C_TABLES * MMU_C_TBL_SIZE)
    350      1.15      gwr 
    351      1.15      gwr /*
    352      1.15      gwr  * The size of the Kernel Virtual Address Space (KVAS)
    353      1.15      gwr  * for purposes of MMU table allocation is -KERNBASE
    354      1.15      gwr  * (length from KERNBASE to 0xFFFFffff)
    355      1.15      gwr  */
    356      1.15      gwr #define	KVAS_SIZE		(-KERNBASE)
    357      1.15      gwr 
    358      1.15      gwr /* Numbers of kernel MMU tables to support KVAS_SIZE. */
    359      1.15      gwr #define KERN_B_TABLES	(KVAS_SIZE >> MMU_TIA_SHIFT)
    360      1.15      gwr #define KERN_C_TABLES	(KVAS_SIZE >> MMU_TIB_SHIFT)
    361      1.15      gwr #define	NUM_KERN_PTES	(KVAS_SIZE >> MMU_TIC_SHIFT)
    362       1.7      gwr 
    363       1.7      gwr /*************************** MISCELANEOUS MACROS *************************/
    364  1.50.2.1   bouyer #define pmap_lock(pmap) simple_lock(&pmap->pm_lock)
    365  1.50.2.1   bouyer #define pmap_unlock(pmap) simple_unlock(&pmap->pm_lock)
    366  1.50.2.1   bouyer #define pmap_add_ref(pmap) ++pmap->pm_refcount
    367  1.50.2.1   bouyer #define pmap_del_ref(pmap) --pmap->pm_refcount
    368  1.50.2.1   bouyer #define pmap_refcount(pmap) pmap->pm_refcount
    369       1.7      gwr 
    370       1.7      gwr static INLINE void *      mmu_ptov __P((vm_offset_t pa));
    371       1.7      gwr static INLINE vm_offset_t mmu_vtop __P((void * va));
    372       1.7      gwr 
    373       1.7      gwr #if	0
    374       1.7      gwr static INLINE a_tmgr_t * mmuA2tmgr __P((mmu_long_dte_t *));
    375      1.26   jeremy #endif /* 0 */
    376       1.7      gwr static INLINE b_tmgr_t * mmuB2tmgr __P((mmu_short_dte_t *));
    377       1.7      gwr static INLINE c_tmgr_t * mmuC2tmgr __P((mmu_short_pte_t *));
    378       1.7      gwr 
    379       1.7      gwr static INLINE pv_t *pa2pv __P((vm_offset_t pa));
    380       1.7      gwr static INLINE int   pteidx __P((mmu_short_pte_t *));
    381       1.7      gwr static INLINE pmap_t current_pmap __P((void));
    382       1.7      gwr 
    383       1.7      gwr /*
    384       1.7      gwr  * We can always convert between virtual and physical addresses
    385       1.7      gwr  * for anything in the range [KERNBASE ... avail_start] because
    386       1.7      gwr  * that range is GUARANTEED to be mapped linearly.
    387       1.7      gwr  * We rely heavily upon this feature!
    388       1.7      gwr  */
    389       1.7      gwr static INLINE void *
    390       1.7      gwr mmu_ptov(pa)
    391       1.7      gwr 	vm_offset_t pa;
    392       1.7      gwr {
    393       1.7      gwr 	register vm_offset_t va;
    394       1.7      gwr 
    395       1.7      gwr 	va = (pa + KERNBASE);
    396       1.8      gwr #ifdef	PMAP_DEBUG
    397       1.7      gwr 	if ((va < KERNBASE) || (va >= virtual_contig_end))
    398       1.7      gwr 		panic("mmu_ptov");
    399       1.7      gwr #endif
    400       1.7      gwr 	return ((void*)va);
    401       1.7      gwr }
    402       1.7      gwr static INLINE vm_offset_t
    403       1.7      gwr mmu_vtop(vva)
    404       1.7      gwr 	void *vva;
    405       1.7      gwr {
    406       1.7      gwr 	register vm_offset_t va;
    407       1.7      gwr 
    408       1.7      gwr 	va = (vm_offset_t)vva;
    409       1.8      gwr #ifdef	PMAP_DEBUG
    410       1.7      gwr 	if ((va < KERNBASE) || (va >= virtual_contig_end))
    411       1.7      gwr 		panic("mmu_ptov");
    412       1.7      gwr #endif
    413       1.7      gwr 	return (va - KERNBASE);
    414       1.7      gwr }
    415       1.7      gwr 
    416       1.7      gwr /*
    417       1.7      gwr  * These macros map MMU tables to their corresponding manager structures.
    418       1.1      gwr  * They are needed quite often because many of the pointers in the pmap
    419       1.1      gwr  * system reference MMU tables and not the structures that control them.
    420       1.1      gwr  * There needs to be a way to find one when given the other and these
    421       1.1      gwr  * macros do so by taking advantage of the memory layout described above.
    422       1.1      gwr  * Here's a quick step through the first macro, mmuA2tmgr():
    423       1.1      gwr  *
    424       1.1      gwr  * 1) find the offset of the given MMU A table from the base of its table
    425       1.1      gwr  *    pool (table - mmuAbase).
    426       1.1      gwr  * 2) convert this offset into a table index by dividing it by the
    427       1.1      gwr  *    size of one MMU 'A' table. (sizeof(mmu_long_dte_t) * MMU_A_TBL_SIZE)
    428       1.1      gwr  * 3) use this index to select the corresponding 'A' table manager
    429       1.1      gwr  *    structure from the 'A' table manager pool (Atmgrbase[index]).
    430       1.1      gwr  */
    431       1.7      gwr /*  This function is not currently used. */
    432       1.7      gwr #if	0
    433       1.7      gwr static INLINE a_tmgr_t *
    434       1.7      gwr mmuA2tmgr(mmuAtbl)
    435       1.7      gwr 	mmu_long_dte_t *mmuAtbl;
    436       1.7      gwr {
    437       1.7      gwr 	register int idx;
    438       1.7      gwr 
    439       1.7      gwr 	/* Which table is this in? */
    440       1.7      gwr 	idx = (mmuAtbl - mmuAbase) / MMU_A_TBL_SIZE;
    441       1.8      gwr #ifdef	PMAP_DEBUG
    442       1.7      gwr 	if ((idx < 0) || (idx >= NUM_A_TABLES))
    443       1.7      gwr 		panic("mmuA2tmgr");
    444       1.7      gwr #endif
    445       1.7      gwr 	return (&Atmgrbase[idx]);
    446       1.7      gwr }
    447       1.7      gwr #endif	/* 0 */
    448       1.7      gwr 
    449       1.7      gwr static INLINE b_tmgr_t *
    450       1.7      gwr mmuB2tmgr(mmuBtbl)
    451       1.7      gwr 	mmu_short_dte_t *mmuBtbl;
    452       1.7      gwr {
    453       1.7      gwr 	register int idx;
    454       1.7      gwr 
    455       1.7      gwr 	/* Which table is this in? */
    456       1.7      gwr 	idx = (mmuBtbl - mmuBbase) / MMU_B_TBL_SIZE;
    457       1.8      gwr #ifdef	PMAP_DEBUG
    458       1.7      gwr 	if ((idx < 0) || (idx >= NUM_B_TABLES))
    459       1.7      gwr 		panic("mmuB2tmgr");
    460       1.7      gwr #endif
    461       1.7      gwr 	return (&Btmgrbase[idx]);
    462       1.7      gwr }
    463       1.7      gwr 
    464       1.7      gwr /* mmuC2tmgr			INTERNAL
    465       1.7      gwr  **
    466       1.7      gwr  * Given a pte known to belong to a C table, return the address of
    467       1.7      gwr  * that table's management structure.
    468       1.7      gwr  */
    469       1.7      gwr static INLINE c_tmgr_t *
    470       1.7      gwr mmuC2tmgr(mmuCtbl)
    471       1.7      gwr 	mmu_short_pte_t *mmuCtbl;
    472       1.7      gwr {
    473       1.7      gwr 	register int idx;
    474       1.7      gwr 
    475       1.7      gwr 	/* Which table is this in? */
    476       1.7      gwr 	idx = (mmuCtbl - mmuCbase) / MMU_C_TBL_SIZE;
    477       1.8      gwr #ifdef	PMAP_DEBUG
    478       1.7      gwr 	if ((idx < 0) || (idx >= NUM_C_TABLES))
    479       1.7      gwr 		panic("mmuC2tmgr");
    480       1.7      gwr #endif
    481       1.7      gwr 	return (&Ctmgrbase[idx]);
    482       1.7      gwr }
    483       1.7      gwr 
    484       1.8      gwr /* This is now a function call below.
    485       1.1      gwr  * #define pa2pv(pa) \
    486       1.1      gwr  *	(&pvbase[(unsigned long)\
    487      1.25    veego  *		m68k_btop(pa)\
    488       1.1      gwr  *	])
    489       1.1      gwr  */
    490       1.1      gwr 
    491       1.7      gwr /* pa2pv			INTERNAL
    492       1.7      gwr  **
    493       1.7      gwr  * Return the pv_list_head element which manages the given physical
    494       1.7      gwr  * address.
    495       1.7      gwr  */
    496       1.7      gwr static INLINE pv_t *
    497       1.7      gwr pa2pv(pa)
    498       1.7      gwr 	vm_offset_t pa;
    499       1.7      gwr {
    500       1.7      gwr 	register struct pmap_physmem_struct *bank;
    501       1.7      gwr 	register int idx;
    502       1.7      gwr 
    503       1.7      gwr 	bank = &avail_mem[0];
    504       1.7      gwr 	while (pa >= bank->pmem_end)
    505       1.7      gwr 		bank = bank->pmem_next;
    506       1.7      gwr 
    507       1.7      gwr 	pa -= bank->pmem_start;
    508      1.25    veego 	idx = bank->pmem_pvbase + m68k_btop(pa);
    509       1.8      gwr #ifdef	PMAP_DEBUG
    510       1.7      gwr 	if ((idx < 0) || (idx >= physmem))
    511       1.7      gwr 		panic("pa2pv");
    512       1.7      gwr #endif
    513       1.7      gwr 	return &pvbase[idx];
    514       1.7      gwr }
    515       1.7      gwr 
    516       1.7      gwr /* pteidx			INTERNAL
    517       1.7      gwr  **
    518       1.7      gwr  * Return the index of the given PTE within the entire fixed table of
    519       1.7      gwr  * PTEs.
    520       1.7      gwr  */
    521       1.7      gwr static INLINE int
    522       1.7      gwr pteidx(pte)
    523       1.7      gwr 	mmu_short_pte_t *pte;
    524       1.7      gwr {
    525       1.7      gwr 	return (pte - kernCbase);
    526       1.7      gwr }
    527       1.7      gwr 
    528       1.7      gwr /*
    529       1.8      gwr  * This just offers a place to put some debugging checks,
    530       1.8      gwr  * and reduces the number of places "curproc" appears...
    531       1.7      gwr  */
    532       1.7      gwr static INLINE pmap_t
    533       1.7      gwr current_pmap()
    534       1.7      gwr {
    535       1.7      gwr 	struct proc *p;
    536       1.7      gwr 	struct vmspace *vm;
    537       1.7      gwr 	vm_map_t	map;
    538       1.7      gwr 	pmap_t	pmap;
    539       1.7      gwr 
    540       1.7      gwr 	p = curproc;	/* XXX */
    541       1.9      gwr 	if (p == NULL)
    542       1.9      gwr 		pmap = &kernel_pmap;
    543       1.9      gwr 	else {
    544       1.9      gwr 		vm = p->p_vmspace;
    545       1.9      gwr 		map = &vm->vm_map;
    546       1.9      gwr 		pmap = vm_map_pmap(map);
    547       1.9      gwr 	}
    548       1.7      gwr 
    549       1.7      gwr 	return (pmap);
    550       1.7      gwr }
    551       1.7      gwr 
    552       1.7      gwr 
    553       1.1      gwr /*************************** FUNCTION DEFINITIONS ************************
    554       1.1      gwr  * These appear here merely for the compiler to enforce type checking on *
    555       1.1      gwr  * all function calls.                                                   *
    556       1.7      gwr  *************************************************************************/
    557       1.1      gwr 
    558       1.1      gwr /** External functions
    559       1.1      gwr  ** - functions used within this module but written elsewhere.
    560       1.1      gwr  **   both of these functions are in locore.s
    561       1.7      gwr  ** XXX - These functions were later replaced with their more cryptic
    562       1.7      gwr  **       hp300 counterparts.  They may be removed now.
    563       1.7      gwr  **/
    564       1.7      gwr #if	0	/* deprecated mmu */
    565       1.1      gwr void   mmu_seturp __P((vm_offset_t));
    566       1.1      gwr void   mmu_flush __P((int, vm_offset_t));
    567       1.1      gwr void   mmu_flusha __P((void));
    568       1.7      gwr #endif	/* 0 */
    569       1.1      gwr 
    570       1.1      gwr /** Internal functions
    571      1.37      gwr  ** Most functions used only within this module are defined in
    572      1.37      gwr  **   pmap_pvt.h (why not here if used only here?)
    573       1.1      gwr  **/
    574      1.37      gwr static void pmap_page_upload __P((void));
    575       1.1      gwr 
    576       1.1      gwr /** Interface functions
    577       1.1      gwr  ** - functions required by the Mach VM Pmap interface, with MACHINE_CONTIG
    578       1.1      gwr  **   defined.
    579       1.1      gwr  **/
    580      1.40      gwr int    pmap_page_index __P((vm_offset_t));
    581      1.36  thorpej void pmap_pinit __P((pmap_t));
    582      1.36  thorpej void pmap_release __P((pmap_t));
    583       1.1      gwr 
    584       1.1      gwr /********************************** CODE ********************************
    585       1.1      gwr  * Functions that are called from other parts of the kernel are labeled *
    586       1.1      gwr  * as 'INTERFACE' functions.  Functions that are only called from       *
    587       1.1      gwr  * within the pmap module are labeled as 'INTERNAL' functions.          *
    588       1.1      gwr  * Functions that are internal, but are not (currently) used at all are *
    589       1.1      gwr  * labeled 'INTERNAL_X'.                                                *
    590       1.1      gwr  ************************************************************************/
    591       1.1      gwr 
    592       1.1      gwr /* pmap_bootstrap			INTERNAL
    593       1.1      gwr  **
    594      1.33      gwr  * Initializes the pmap system.  Called at boot time from
    595      1.33      gwr  * locore2.c:_vm_init()
    596       1.1      gwr  *
    597       1.1      gwr  * Reminder: having a pmap_bootstrap_alloc() and also having the VM
    598       1.1      gwr  *           system implement pmap_steal_memory() is redundant.
    599       1.1      gwr  *           Don't release this code without removing one or the other!
    600       1.1      gwr  */
    601       1.1      gwr void
    602       1.1      gwr pmap_bootstrap(nextva)
    603       1.1      gwr 	vm_offset_t nextva;
    604       1.1      gwr {
    605       1.1      gwr 	struct physmemory *membank;
    606       1.1      gwr 	struct pmap_physmem_struct *pmap_membank;
    607       1.1      gwr 	vm_offset_t va, pa, eva;
    608       1.1      gwr 	int b, c, i, j;	/* running table counts */
    609      1.40      gwr 	int size, resvmem;
    610       1.1      gwr 
    611       1.1      gwr 	/*
    612       1.1      gwr 	 * This function is called by __bootstrap after it has
    613       1.1      gwr 	 * determined the type of machine and made the appropriate
    614       1.1      gwr 	 * patches to the ROM vectors (XXX- I don't quite know what I meant
    615       1.1      gwr 	 * by that.)  It allocates and sets up enough of the pmap system
    616       1.1      gwr 	 * to manage the kernel's address space.
    617       1.1      gwr 	 */
    618       1.1      gwr 
    619       1.1      gwr 	/*
    620       1.7      gwr 	 * Determine the range of kernel virtual and physical
    621       1.7      gwr 	 * space available. Note that we ABSOLUTELY DEPEND on
    622       1.7      gwr 	 * the fact that the first bank of memory (4MB) is
    623       1.7      gwr 	 * mapped linearly to KERNBASE (which we guaranteed in
    624       1.7      gwr 	 * the first instructions of locore.s).
    625       1.7      gwr 	 * That is plenty for our bootstrap work.
    626       1.1      gwr 	 */
    627      1.25    veego 	virtual_avail = m68k_round_page(nextva);
    628       1.7      gwr 	virtual_contig_end = KERNBASE + 0x400000; /* +4MB */
    629       1.1      gwr 	virtual_end = VM_MAX_KERNEL_ADDRESS;
    630       1.7      gwr 	/* Don't need avail_start til later. */
    631       1.1      gwr 
    632       1.7      gwr 	/* We may now call pmap_bootstrap_alloc(). */
    633       1.7      gwr 	bootstrap_alloc_enabled = TRUE;
    634       1.1      gwr 
    635       1.1      gwr 	/*
    636       1.1      gwr 	 * This is a somewhat unwrapped loop to deal with
    637       1.1      gwr 	 * copying the PROM's 'phsymem' banks into the pmap's
    638       1.1      gwr 	 * banks.  The following is always assumed:
    639       1.1      gwr 	 * 1. There is always at least one bank of memory.
    640       1.1      gwr 	 * 2. There is always a last bank of memory, and its
    641       1.1      gwr 	 *    pmem_next member must be set to NULL.
    642       1.1      gwr 	 */
    643       1.1      gwr 	membank = romVectorPtr->v_physmemory;
    644       1.1      gwr 	pmap_membank = avail_mem;
    645       1.1      gwr 	total_phys_mem = 0;
    646       1.1      gwr 
    647      1.40      gwr 	for (;;) { /* break on !membank */
    648       1.1      gwr 		pmap_membank->pmem_start = membank->address;
    649       1.1      gwr 		pmap_membank->pmem_end = membank->address + membank->size;
    650       1.1      gwr 		total_phys_mem += membank->size;
    651      1.40      gwr 		membank = membank->next;
    652      1.40      gwr 		if (!membank)
    653      1.40      gwr 			break;
    654       1.1      gwr 		/* This silly syntax arises because pmap_membank
    655       1.1      gwr 		 * is really a pre-allocated array, but it is put into
    656       1.1      gwr 		 * use as a linked list.
    657       1.1      gwr 		 */
    658       1.1      gwr 		pmap_membank->pmem_next = pmap_membank + 1;
    659       1.1      gwr 		pmap_membank = pmap_membank->pmem_next;
    660       1.1      gwr 	}
    661      1.40      gwr 	/* This is the last element. */
    662      1.40      gwr 	pmap_membank->pmem_next = NULL;
    663       1.1      gwr 
    664       1.1      gwr 	/*
    665      1.40      gwr 	 * Note: total_phys_mem, physmem represent
    666      1.40      gwr 	 * actual physical memory, including that
    667      1.40      gwr 	 * reserved for the PROM monitor.
    668       1.1      gwr 	 */
    669      1.40      gwr 	physmem = btoc(total_phys_mem);
    670       1.1      gwr 
    671       1.1      gwr 	/*
    672      1.40      gwr 	 * The last bank of memory should be reduced to prevent the
    673      1.40      gwr 	 * physical pages needed by the PROM monitor from being used
    674      1.40      gwr 	 * in the VM system.
    675       1.1      gwr 	 */
    676      1.40      gwr 	resvmem = total_phys_mem - *(romVectorPtr->memoryAvail);
    677      1.40      gwr 	resvmem = m68k_round_page(resvmem);
    678      1.40      gwr 	pmap_membank->pmem_end -= resvmem;
    679       1.7      gwr 
    680       1.7      gwr 	/*
    681       1.7      gwr 	 * Avail_end is set to the first byte of physical memory
    682       1.7      gwr 	 * after the end of the last bank.  We use this only to
    683       1.7      gwr 	 * determine if a physical address is "managed" memory.
    684       1.7      gwr 	 */
    685      1.40      gwr 	avail_end = pmap_membank->pmem_end;
    686       1.1      gwr 
    687       1.1      gwr 	/*
    688      1.15      gwr 	 * First allocate enough kernel MMU tables to map all
    689      1.15      gwr 	 * of kernel virtual space from KERNBASE to 0xFFFFFFFF.
    690       1.1      gwr 	 * Note: All must be aligned on 256 byte boundaries.
    691      1.15      gwr 	 * Start with the level-A table (one of those).
    692       1.1      gwr 	 */
    693      1.15      gwr 	size = sizeof(mmu_long_dte_t)  * MMU_A_TBL_SIZE;
    694       1.7      gwr 	kernAbase = pmap_bootstrap_alloc(size);
    695       1.1      gwr 	bzero(kernAbase, size);
    696       1.1      gwr 
    697      1.15      gwr 	/* Now the level-B kernel tables... */
    698      1.15      gwr 	size = sizeof(mmu_short_dte_t) * MMU_B_TBL_SIZE * KERN_B_TABLES;
    699       1.7      gwr 	kernBbase = pmap_bootstrap_alloc(size);
    700       1.1      gwr 	bzero(kernBbase, size);
    701       1.1      gwr 
    702      1.15      gwr 	/* Now the level-C kernel tables... */
    703      1.15      gwr 	size = sizeof(mmu_short_pte_t) * MMU_C_TBL_SIZE * KERN_C_TABLES;
    704      1.15      gwr 	kernCbase = pmap_bootstrap_alloc(size);
    705      1.15      gwr 	bzero(kernCbase, size);
    706       1.7      gwr 	/*
    707       1.7      gwr 	 * Note: In order for the PV system to work correctly, the kernel
    708       1.7      gwr 	 * and user-level C tables must be allocated contiguously.
    709       1.7      gwr 	 * Nothing should be allocated between here and the allocation of
    710       1.7      gwr 	 * mmuCbase below.  XXX: Should do this as one allocation, and
    711       1.7      gwr 	 * then compute a pointer for mmuCbase instead of this...
    712      1.15      gwr 	 *
    713      1.15      gwr 	 * Allocate user MMU tables.
    714      1.15      gwr 	 * These must be contiguous with the preceeding.
    715       1.7      gwr 	 */
    716      1.22   jeremy 
    717      1.22   jeremy #ifndef	FIXED_NTABLES
    718      1.22   jeremy 	/*
    719      1.22   jeremy 	 * The number of user-level C tables that should be allocated is
    720      1.22   jeremy 	 * related to the size of physical memory.  In general, there should
    721      1.22   jeremy 	 * be enough tables to map four times the amount of available RAM.
    722      1.22   jeremy 	 * The extra amount is needed because some table space is wasted by
    723      1.22   jeremy 	 * fragmentation.
    724      1.22   jeremy 	 */
    725      1.22   jeremy 	NUM_C_TABLES = (total_phys_mem * 4) / (MMU_C_TBL_SIZE * MMU_PAGE_SIZE);
    726      1.22   jeremy 	NUM_B_TABLES = NUM_C_TABLES / 2;
    727      1.22   jeremy 	NUM_A_TABLES = NUM_B_TABLES / 2;
    728      1.22   jeremy #endif	/* !FIXED_NTABLES */
    729      1.22   jeremy 
    730      1.15      gwr 	size = sizeof(mmu_short_pte_t) * MMU_C_TBL_SIZE	* NUM_C_TABLES;
    731      1.15      gwr 	mmuCbase = pmap_bootstrap_alloc(size);
    732      1.15      gwr 
    733      1.15      gwr 	size = sizeof(mmu_short_dte_t) * MMU_B_TBL_SIZE	* NUM_B_TABLES;
    734      1.15      gwr 	mmuBbase = pmap_bootstrap_alloc(size);
    735       1.1      gwr 
    736      1.15      gwr 	size = sizeof(mmu_long_dte_t)  * MMU_A_TBL_SIZE * NUM_A_TABLES;
    737      1.15      gwr 	mmuAbase = pmap_bootstrap_alloc(size);
    738       1.7      gwr 
    739       1.7      gwr 	/*
    740       1.7      gwr 	 * Fill in the never-changing part of the kernel tables.
    741       1.7      gwr 	 * For simplicity, the kernel's mappings will be editable as a
    742       1.1      gwr 	 * flat array of page table entries at kernCbase.  The
    743       1.1      gwr 	 * higher level 'A' and 'B' tables must be initialized to point
    744       1.1      gwr 	 * to this lower one.
    745       1.1      gwr 	 */
    746       1.1      gwr 	b = c = 0;
    747       1.1      gwr 
    748       1.7      gwr 	/*
    749       1.7      gwr 	 * Invalidate all mappings below KERNBASE in the A table.
    750       1.1      gwr 	 * This area has already been zeroed out, but it is good
    751       1.1      gwr 	 * practice to explicitly show that we are interpreting
    752       1.1      gwr 	 * it as a list of A table descriptors.
    753       1.1      gwr 	 */
    754       1.1      gwr 	for (i = 0; i < MMU_TIA(KERNBASE); i++) {
    755       1.1      gwr 		kernAbase[i].addr.raw = 0;
    756       1.1      gwr 	}
    757       1.1      gwr 
    758       1.7      gwr 	/*
    759       1.7      gwr 	 * Set up the kernel A and B tables so that they will reference the
    760       1.1      gwr 	 * correct spots in the contiguous table of PTEs allocated for the
    761       1.1      gwr 	 * kernel's virtual memory space.
    762       1.1      gwr 	 */
    763       1.1      gwr 	for (i = MMU_TIA(KERNBASE); i < MMU_A_TBL_SIZE; i++) {
    764       1.1      gwr 		kernAbase[i].attr.raw =
    765       1.1      gwr 			MMU_LONG_DTE_LU | MMU_LONG_DTE_SUPV | MMU_DT_SHORT;
    766       1.7      gwr 		kernAbase[i].addr.raw = mmu_vtop(&kernBbase[b]);
    767       1.1      gwr 
    768       1.1      gwr 		for (j=0; j < MMU_B_TBL_SIZE; j++) {
    769       1.7      gwr 			kernBbase[b + j].attr.raw = mmu_vtop(&kernCbase[c])
    770       1.1      gwr 				| MMU_DT_SHORT;
    771       1.1      gwr 			c += MMU_C_TBL_SIZE;
    772       1.1      gwr 		}
    773       1.1      gwr 		b += MMU_B_TBL_SIZE;
    774       1.1      gwr 	}
    775       1.1      gwr 
    776       1.8      gwr 	/* XXX - Doing kernel_pmap a little further down. */
    777       1.8      gwr 
    778       1.7      gwr 	pmap_alloc_usermmu();	/* Allocate user MMU tables.        */
    779       1.7      gwr 	pmap_alloc_usertmgr();	/* Allocate user MMU table managers.*/
    780       1.7      gwr 	pmap_alloc_pv();	/* Allocate physical->virtual map.  */
    781       1.7      gwr 
    782       1.7      gwr 	/*
    783       1.7      gwr 	 * We are now done with pmap_bootstrap_alloc().  Round up
    784       1.7      gwr 	 * `virtual_avail' to the nearest page, and set the flag
    785       1.7      gwr 	 * to prevent use of pmap_bootstrap_alloc() hereafter.
    786       1.7      gwr 	 */
    787       1.7      gwr 	pmap_bootstrap_aalign(NBPG);
    788       1.7      gwr 	bootstrap_alloc_enabled = FALSE;
    789       1.7      gwr 
    790       1.7      gwr 	/*
    791       1.7      gwr 	 * Now that we are done with pmap_bootstrap_alloc(), we
    792       1.7      gwr 	 * must save the virtual and physical addresses of the
    793       1.7      gwr 	 * end of the linearly mapped range, which are stored in
    794       1.7      gwr 	 * virtual_contig_end and avail_start, respectively.
    795       1.7      gwr 	 * These variables will never change after this point.
    796       1.7      gwr 	 */
    797       1.7      gwr 	virtual_contig_end = virtual_avail;
    798       1.7      gwr 	avail_start = virtual_avail - KERNBASE;
    799       1.7      gwr 
    800       1.7      gwr 	/*
    801       1.7      gwr 	 * `avail_next' is a running pointer used by pmap_next_page() to
    802       1.7      gwr 	 * keep track of the next available physical page to be handed
    803       1.7      gwr 	 * to the VM system during its initialization, in which it
    804       1.7      gwr 	 * asks for physical pages, one at a time.
    805       1.7      gwr 	 */
    806       1.7      gwr 	avail_next = avail_start;
    807       1.7      gwr 
    808       1.7      gwr 	/*
    809       1.7      gwr 	 * Now allocate some virtual addresses, but not the physical pages
    810       1.7      gwr 	 * behind them.  Note that virtual_avail is already page-aligned.
    811       1.7      gwr 	 *
    812       1.7      gwr 	 * tmp_vpages[] is an array of two virtual pages used for temporary
    813       1.7      gwr 	 * kernel mappings in the pmap module to facilitate various physical
    814       1.7      gwr 	 * address-oritented operations.
    815       1.7      gwr 	 */
    816       1.7      gwr 	tmp_vpages[0] = virtual_avail;
    817       1.7      gwr 	virtual_avail += NBPG;
    818       1.7      gwr 	tmp_vpages[1] = virtual_avail;
    819       1.7      gwr 	virtual_avail += NBPG;
    820       1.7      gwr 
    821       1.7      gwr 	/** Initialize the PV system **/
    822       1.7      gwr 	pmap_init_pv();
    823       1.7      gwr 
    824       1.7      gwr 	/*
    825       1.7      gwr 	 * Fill in the kernel_pmap structure and kernel_crp.
    826       1.7      gwr 	 */
    827       1.7      gwr 	kernAphys = mmu_vtop(kernAbase);
    828       1.7      gwr 	kernel_pmap.pm_a_tmgr = NULL;
    829       1.7      gwr 	kernel_pmap.pm_a_phys = kernAphys;
    830       1.7      gwr 	kernel_pmap.pm_refcount = 1; /* always in use */
    831  1.50.2.1   bouyer 	simple_lock_init(&kernel_pmap.pm_lock);
    832       1.7      gwr 
    833       1.7      gwr 	kernel_crp.rp_attr = MMU_LONG_DTE_LU | MMU_DT_LONG;
    834       1.7      gwr 	kernel_crp.rp_addr = kernAphys;
    835       1.7      gwr 
    836       1.1      gwr 	/*
    837       1.1      gwr 	 * Now pmap_enter_kernel() may be used safely and will be
    838       1.7      gwr 	 * the main interface used hereafter to modify the kernel's
    839       1.7      gwr 	 * virtual address space.  Note that since we are still running
    840       1.7      gwr 	 * under the PROM's address table, none of these table modifications
    841       1.7      gwr 	 * actually take effect until pmap_takeover_mmu() is called.
    842       1.1      gwr 	 *
    843       1.7      gwr 	 * Note: Our tables do NOT have the PROM linear mappings!
    844       1.7      gwr 	 * Only the mappings created here exist in our tables, so
    845       1.7      gwr 	 * remember to map anything we expect to use.
    846       1.1      gwr 	 */
    847       1.1      gwr 	va = (vm_offset_t) KERNBASE;
    848       1.7      gwr 	pa = 0;
    849       1.1      gwr 
    850       1.1      gwr 	/*
    851       1.7      gwr 	 * The first page of the kernel virtual address space is the msgbuf
    852       1.7      gwr 	 * page.  The page attributes (data, non-cached) are set here, while
    853       1.7      gwr 	 * the address is assigned to this global pointer in cpu_startup().
    854      1.29      gwr 	 * It is non-cached, mostly due to paranoia.
    855       1.1      gwr 	 */
    856      1.29      gwr 	pmap_enter_kernel(va, pa|PMAP_NC, VM_PROT_ALL);
    857      1.29      gwr 	va += NBPG; pa += NBPG;
    858       1.1      gwr 
    859       1.7      gwr 	/* Next page is used as the temporary stack. */
    860       1.1      gwr 	pmap_enter_kernel(va, pa, VM_PROT_ALL);
    861       1.1      gwr 	va += NBPG; pa += NBPG;
    862       1.1      gwr 
    863       1.1      gwr 	/*
    864       1.1      gwr 	 * Map all of the kernel's text segment as read-only and cacheable.
    865       1.1      gwr 	 * (Cacheable is implied by default).  Unfortunately, the last bytes
    866       1.1      gwr 	 * of kernel text and the first bytes of kernel data will often be
    867       1.1      gwr 	 * sharing the same page.  Therefore, the last page of kernel text
    868       1.1      gwr 	 * has to be mapped as read/write, to accomodate the data.
    869       1.1      gwr 	 */
    870      1.25    veego 	eva = m68k_trunc_page((vm_offset_t)etext);
    871       1.7      gwr 	for (; va < eva; va += NBPG, pa += NBPG)
    872       1.1      gwr 		pmap_enter_kernel(va, pa, VM_PROT_READ|VM_PROT_EXECUTE);
    873       1.1      gwr 
    874       1.7      gwr 	/*
    875       1.7      gwr 	 * Map all of the kernel's data as read/write and cacheable.
    876       1.7      gwr 	 * This includes: data, BSS, symbols, and everything in the
    877       1.7      gwr 	 * contiguous memory used by pmap_bootstrap_alloc()
    878       1.1      gwr 	 */
    879       1.7      gwr 	for (; pa < avail_start; va += NBPG, pa += NBPG)
    880       1.1      gwr 		pmap_enter_kernel(va, pa, VM_PROT_READ|VM_PROT_WRITE);
    881       1.1      gwr 
    882       1.7      gwr 	/*
    883       1.7      gwr 	 * At this point we are almost ready to take over the MMU.  But first
    884       1.7      gwr 	 * we must save the PROM's address space in our map, as we call its
    885       1.7      gwr 	 * routines and make references to its data later in the kernel.
    886       1.1      gwr 	 */
    887       1.7      gwr 	pmap_bootstrap_copyprom();
    888       1.7      gwr 	pmap_takeover_mmu();
    889      1.13      gwr 	pmap_bootstrap_setprom();
    890       1.1      gwr 
    891       1.1      gwr 	/* Notify the VM system of our page size. */
    892  1.50.2.3   bouyer 	uvmexp.pagesize = NBPG;
    893      1.43      mrg 	uvm_setpagesize();
    894      1.37      gwr 
    895      1.37      gwr 	pmap_page_upload();
    896       1.1      gwr }
    897       1.1      gwr 
    898       1.1      gwr 
    899       1.1      gwr /* pmap_alloc_usermmu			INTERNAL
    900       1.1      gwr  **
    901       1.1      gwr  * Called from pmap_bootstrap() to allocate MMU tables that will
    902       1.1      gwr  * eventually be used for user mappings.
    903       1.1      gwr  */
    904       1.1      gwr void
    905       1.1      gwr pmap_alloc_usermmu()
    906       1.1      gwr {
    907       1.7      gwr 	/* XXX: Moved into caller. */
    908       1.1      gwr }
    909       1.1      gwr 
    910       1.1      gwr /* pmap_alloc_pv			INTERNAL
    911       1.1      gwr  **
    912       1.1      gwr  * Called from pmap_bootstrap() to allocate the physical
    913       1.1      gwr  * to virtual mapping list.  Each physical page of memory
    914       1.1      gwr  * in the system has a corresponding element in this list.
    915       1.1      gwr  */
    916       1.1      gwr void
    917       1.1      gwr pmap_alloc_pv()
    918       1.1      gwr {
    919       1.1      gwr 	int	i;
    920       1.1      gwr 	unsigned int	total_mem;
    921       1.1      gwr 
    922       1.7      gwr 	/*
    923       1.7      gwr 	 * Allocate a pv_head structure for every page of physical
    924       1.1      gwr 	 * memory that will be managed by the system.  Since memory on
    925       1.1      gwr 	 * the 3/80 is non-contiguous, we cannot arrive at a total page
    926       1.1      gwr 	 * count by subtraction of the lowest available address from the
    927       1.1      gwr 	 * highest, but rather we have to step through each memory
    928       1.1      gwr 	 * bank and add the number of pages in each to the total.
    929       1.1      gwr 	 *
    930       1.1      gwr 	 * At this time we also initialize the offset of each bank's
    931       1.1      gwr 	 * starting pv_head within the pv_head list so that the physical
    932       1.1      gwr 	 * memory state routines (pmap_is_referenced(),
    933       1.1      gwr 	 * pmap_is_modified(), et al.) can quickly find coresponding
    934       1.1      gwr 	 * pv_heads in spite of the non-contiguity.
    935       1.1      gwr 	 */
    936       1.1      gwr 	total_mem = 0;
    937      1.20  thorpej 	for (i = 0; i < SUN3X_NPHYS_RAM_SEGS; i++) {
    938      1.25    veego 		avail_mem[i].pmem_pvbase = m68k_btop(total_mem);
    939       1.1      gwr 		total_mem += avail_mem[i].pmem_end -
    940       1.1      gwr 			avail_mem[i].pmem_start;
    941       1.1      gwr 		if (avail_mem[i].pmem_next == NULL)
    942       1.1      gwr 			break;
    943       1.1      gwr 	}
    944       1.1      gwr 	pvbase = (pv_t *) pmap_bootstrap_alloc(sizeof(pv_t) *
    945      1.25    veego 		m68k_btop(total_phys_mem));
    946       1.1      gwr }
    947       1.1      gwr 
    948       1.1      gwr /* pmap_alloc_usertmgr			INTERNAL
    949       1.1      gwr  **
    950       1.1      gwr  * Called from pmap_bootstrap() to allocate the structures which
    951       1.1      gwr  * facilitate management of user MMU tables.  Each user MMU table
    952       1.1      gwr  * in the system has one such structure associated with it.
    953       1.1      gwr  */
    954       1.1      gwr void
    955       1.1      gwr pmap_alloc_usertmgr()
    956       1.1      gwr {
    957       1.1      gwr 	/* Allocate user MMU table managers */
    958       1.7      gwr 	/* It would be a lot simpler to just make these BSS, but */
    959       1.7      gwr 	/* we may want to change their size at boot time... -j */
    960       1.1      gwr 	Atmgrbase = (a_tmgr_t *) pmap_bootstrap_alloc(sizeof(a_tmgr_t)
    961       1.1      gwr 		* NUM_A_TABLES);
    962       1.1      gwr 	Btmgrbase = (b_tmgr_t *) pmap_bootstrap_alloc(sizeof(b_tmgr_t)
    963       1.1      gwr 		* NUM_B_TABLES);
    964       1.1      gwr 	Ctmgrbase = (c_tmgr_t *) pmap_bootstrap_alloc(sizeof(c_tmgr_t)
    965       1.1      gwr 		* NUM_C_TABLES);
    966       1.1      gwr 
    967       1.7      gwr 	/*
    968       1.7      gwr 	 * Allocate PV list elements for the physical to virtual
    969       1.1      gwr 	 * mapping system.
    970       1.1      gwr 	 */
    971       1.1      gwr 	pvebase = (pv_elem_t *) pmap_bootstrap_alloc(
    972       1.7      gwr 		sizeof(pv_elem_t) * (NUM_USER_PTES + NUM_KERN_PTES));
    973       1.1      gwr }
    974       1.1      gwr 
    975       1.1      gwr /* pmap_bootstrap_copyprom()			INTERNAL
    976       1.1      gwr  **
    977       1.1      gwr  * Copy the PROM mappings into our own tables.  Note, we
    978       1.1      gwr  * can use physical addresses until __bootstrap returns.
    979       1.1      gwr  */
    980       1.1      gwr void
    981       1.1      gwr pmap_bootstrap_copyprom()
    982       1.1      gwr {
    983      1.33      gwr 	struct sunromvec *romp;
    984       1.1      gwr 	int *mon_ctbl;
    985       1.1      gwr 	mmu_short_pte_t *kpte;
    986       1.1      gwr 	int i, len;
    987       1.1      gwr 
    988       1.1      gwr 	romp = romVectorPtr;
    989       1.1      gwr 
    990       1.1      gwr 	/*
    991      1.33      gwr 	 * Copy the mappings in SUN3X_MON_KDB_BASE...SUN3X_MONEND
    992      1.33      gwr 	 * Note: mon_ctbl[0] maps SUN3X_MON_KDB_BASE
    993       1.1      gwr 	 */
    994       1.1      gwr 	mon_ctbl = *romp->monptaddr;
    995      1.33      gwr 	i = m68k_btop(SUN3X_MON_KDB_BASE - KERNBASE);
    996       1.1      gwr 	kpte = &kernCbase[i];
    997      1.33      gwr 	len = m68k_btop(SUN3X_MONEND - SUN3X_MON_KDB_BASE);
    998       1.1      gwr 
    999       1.1      gwr 	for (i = 0; i < len; i++) {
   1000       1.1      gwr 		kpte[i].attr.raw = mon_ctbl[i];
   1001       1.1      gwr 	}
   1002       1.1      gwr 
   1003       1.1      gwr 	/*
   1004       1.1      gwr 	 * Copy the mappings at MON_DVMA_BASE (to the end).
   1005       1.1      gwr 	 * Note, in here, mon_ctbl[0] maps MON_DVMA_BASE.
   1006      1.32      gwr 	 * Actually, we only want the last page, which the
   1007      1.32      gwr 	 * PROM has set up for use by the "ie" driver.
   1008      1.32      gwr 	 * (The i82686 needs its SCP there.)
   1009      1.32      gwr 	 * If we copy all the mappings, pmap_enter_kernel
   1010      1.32      gwr 	 * may complain about finding valid PTEs that are
   1011      1.32      gwr 	 * not recorded in our PV lists...
   1012       1.1      gwr 	 */
   1013       1.1      gwr 	mon_ctbl = *romp->shadowpteaddr;
   1014      1.33      gwr 	i = m68k_btop(SUN3X_MON_DVMA_BASE - KERNBASE);
   1015       1.1      gwr 	kpte = &kernCbase[i];
   1016      1.33      gwr 	len = m68k_btop(SUN3X_MON_DVMA_SIZE);
   1017      1.32      gwr 	for (i = (len-1); i < len; i++) {
   1018       1.1      gwr 		kpte[i].attr.raw = mon_ctbl[i];
   1019       1.1      gwr 	}
   1020       1.1      gwr }
   1021       1.1      gwr 
   1022       1.1      gwr /* pmap_takeover_mmu			INTERNAL
   1023       1.1      gwr  **
   1024       1.1      gwr  * Called from pmap_bootstrap() after it has copied enough of the
   1025       1.1      gwr  * PROM mappings into the kernel map so that we can use our own
   1026       1.1      gwr  * MMU table.
   1027       1.1      gwr  */
   1028       1.1      gwr void
   1029       1.1      gwr pmap_takeover_mmu()
   1030       1.1      gwr {
   1031       1.1      gwr 
   1032      1.13      gwr 	loadcrp(&kernel_crp);
   1033       1.1      gwr }
   1034       1.1      gwr 
   1035      1.13      gwr /* pmap_bootstrap_setprom()			INTERNAL
   1036      1.13      gwr  **
   1037      1.13      gwr  * Set the PROM mappings so it can see kernel space.
   1038      1.13      gwr  * Note that physical addresses are used here, which
   1039      1.13      gwr  * we can get away with because this runs with the
   1040      1.13      gwr  * low 1GB set for transparent translation.
   1041      1.13      gwr  */
   1042      1.13      gwr void
   1043      1.13      gwr pmap_bootstrap_setprom()
   1044      1.13      gwr {
   1045      1.13      gwr 	mmu_long_dte_t *mon_dte;
   1046      1.13      gwr 	extern struct mmu_rootptr mon_crp;
   1047      1.13      gwr 	int i;
   1048      1.13      gwr 
   1049      1.13      gwr 	mon_dte = (mmu_long_dte_t *) mon_crp.rp_addr;
   1050      1.13      gwr 	for (i = MMU_TIA(KERNBASE); i < MMU_TIA(KERN_END); i++) {
   1051      1.13      gwr 		mon_dte[i].attr.raw = kernAbase[i].attr.raw;
   1052      1.13      gwr 		mon_dte[i].addr.raw = kernAbase[i].addr.raw;
   1053      1.13      gwr 	}
   1054      1.13      gwr }
   1055      1.13      gwr 
   1056      1.13      gwr 
   1057       1.1      gwr /* pmap_init			INTERFACE
   1058       1.1      gwr  **
   1059       1.1      gwr  * Called at the end of vm_init() to set up the pmap system to go
   1060       1.7      gwr  * into full time operation.  All initialization of kernel_pmap
   1061       1.7      gwr  * should be already done by now, so this should just do things
   1062       1.7      gwr  * needed for user-level pmaps to work.
   1063       1.1      gwr  */
   1064       1.1      gwr void
   1065       1.1      gwr pmap_init()
   1066       1.1      gwr {
   1067       1.1      gwr 	/** Initialize the manager pools **/
   1068       1.1      gwr 	TAILQ_INIT(&a_pool);
   1069       1.1      gwr 	TAILQ_INIT(&b_pool);
   1070       1.1      gwr 	TAILQ_INIT(&c_pool);
   1071       1.1      gwr 
   1072       1.1      gwr 	/**************************************************************
   1073       1.1      gwr 	 * Initialize all tmgr structures and MMU tables they manage. *
   1074       1.1      gwr 	 **************************************************************/
   1075       1.1      gwr 	/** Initialize A tables **/
   1076       1.1      gwr 	pmap_init_a_tables();
   1077       1.1      gwr 	/** Initialize B tables **/
   1078       1.1      gwr 	pmap_init_b_tables();
   1079       1.1      gwr 	/** Initialize C tables **/
   1080       1.1      gwr 	pmap_init_c_tables();
   1081  1.50.2.2   bouyer 
   1082  1.50.2.2   bouyer 	/** Initialize the pmap pools **/
   1083  1.50.2.2   bouyer 	pool_init(&pmap_pmap_pool, sizeof(struct pmap), 0, 0, 0, "pmappl",
   1084  1.50.2.2   bouyer 	    0, pool_page_alloc_nointr, pool_page_free_nointr, M_VMPMAP);
   1085       1.1      gwr }
   1086       1.1      gwr 
   1087       1.1      gwr /* pmap_init_a_tables()			INTERNAL
   1088       1.1      gwr  **
   1089       1.1      gwr  * Initializes all A managers, their MMU A tables, and inserts
   1090       1.1      gwr  * them into the A manager pool for use by the system.
   1091       1.1      gwr  */
   1092       1.1      gwr void
   1093       1.1      gwr pmap_init_a_tables()
   1094       1.1      gwr {
   1095       1.1      gwr 	int i;
   1096       1.1      gwr 	a_tmgr_t *a_tbl;
   1097       1.1      gwr 
   1098       1.1      gwr 	for (i=0; i < NUM_A_TABLES; i++) {
   1099       1.1      gwr 		/* Select the next available A manager from the pool */
   1100       1.1      gwr 		a_tbl = &Atmgrbase[i];
   1101       1.1      gwr 
   1102       1.7      gwr 		/*
   1103       1.7      gwr 		 * Clear its parent entry.  Set its wired and valid
   1104       1.1      gwr 		 * entry count to zero.
   1105       1.1      gwr 		 */
   1106       1.1      gwr 		a_tbl->at_parent = NULL;
   1107       1.1      gwr 		a_tbl->at_wcnt = a_tbl->at_ecnt = 0;
   1108       1.1      gwr 
   1109       1.1      gwr 		/* Assign it the next available MMU A table from the pool */
   1110       1.1      gwr 		a_tbl->at_dtbl = &mmuAbase[i * MMU_A_TBL_SIZE];
   1111       1.1      gwr 
   1112       1.7      gwr 		/*
   1113       1.7      gwr 		 * Initialize the MMU A table with the table in the `proc0',
   1114       1.1      gwr 		 * or kernel, mapping.  This ensures that every process has
   1115       1.1      gwr 		 * the kernel mapped in the top part of its address space.
   1116       1.1      gwr 		 */
   1117       1.1      gwr 		bcopy(kernAbase, a_tbl->at_dtbl, MMU_A_TBL_SIZE *
   1118       1.1      gwr 			sizeof(mmu_long_dte_t));
   1119       1.1      gwr 
   1120       1.7      gwr 		/*
   1121       1.7      gwr 		 * Finally, insert the manager into the A pool,
   1122       1.1      gwr 		 * making it ready to be used by the system.
   1123       1.1      gwr 		 */
   1124       1.1      gwr 		TAILQ_INSERT_TAIL(&a_pool, a_tbl, at_link);
   1125       1.1      gwr     }
   1126       1.1      gwr }
   1127       1.1      gwr 
   1128       1.1      gwr /* pmap_init_b_tables()			INTERNAL
   1129       1.1      gwr  **
   1130       1.1      gwr  * Initializes all B table managers, their MMU B tables, and
   1131       1.1      gwr  * inserts them into the B manager pool for use by the system.
   1132       1.1      gwr  */
   1133       1.1      gwr void
   1134       1.1      gwr pmap_init_b_tables()
   1135       1.1      gwr {
   1136       1.1      gwr 	int i,j;
   1137       1.1      gwr 	b_tmgr_t *b_tbl;
   1138       1.1      gwr 
   1139       1.1      gwr 	for (i=0; i < NUM_B_TABLES; i++) {
   1140       1.1      gwr 		/* Select the next available B manager from the pool */
   1141       1.1      gwr 		b_tbl = &Btmgrbase[i];
   1142       1.1      gwr 
   1143       1.1      gwr 		b_tbl->bt_parent = NULL;	/* clear its parent,  */
   1144       1.1      gwr 		b_tbl->bt_pidx = 0;		/* parent index,      */
   1145       1.1      gwr 		b_tbl->bt_wcnt = 0;		/* wired entry count, */
   1146       1.1      gwr 		b_tbl->bt_ecnt = 0;		/* valid entry count. */
   1147       1.1      gwr 
   1148       1.1      gwr 		/* Assign it the next available MMU B table from the pool */
   1149       1.1      gwr 		b_tbl->bt_dtbl = &mmuBbase[i * MMU_B_TBL_SIZE];
   1150       1.1      gwr 
   1151       1.1      gwr 		/* Invalidate every descriptor in the table */
   1152       1.1      gwr 		for (j=0; j < MMU_B_TBL_SIZE; j++)
   1153       1.1      gwr 			b_tbl->bt_dtbl[j].attr.raw = MMU_DT_INVALID;
   1154       1.1      gwr 
   1155       1.1      gwr 		/* Insert the manager into the B pool */
   1156       1.1      gwr 		TAILQ_INSERT_TAIL(&b_pool, b_tbl, bt_link);
   1157       1.1      gwr 	}
   1158       1.1      gwr }
   1159       1.1      gwr 
   1160       1.1      gwr /* pmap_init_c_tables()			INTERNAL
   1161       1.1      gwr  **
   1162       1.1      gwr  * Initializes all C table managers, their MMU C tables, and
   1163       1.1      gwr  * inserts them into the C manager pool for use by the system.
   1164       1.1      gwr  */
   1165       1.1      gwr void
   1166       1.1      gwr pmap_init_c_tables()
   1167       1.1      gwr {
   1168       1.1      gwr 	int i,j;
   1169       1.1      gwr 	c_tmgr_t *c_tbl;
   1170       1.1      gwr 
   1171       1.1      gwr 	for (i=0; i < NUM_C_TABLES; i++) {
   1172       1.1      gwr 		/* Select the next available C manager from the pool */
   1173       1.1      gwr 		c_tbl = &Ctmgrbase[i];
   1174       1.1      gwr 
   1175       1.1      gwr 		c_tbl->ct_parent = NULL;	/* clear its parent,  */
   1176       1.1      gwr 		c_tbl->ct_pidx = 0;		/* parent index,      */
   1177       1.1      gwr 		c_tbl->ct_wcnt = 0;		/* wired entry count, */
   1178      1.26   jeremy 		c_tbl->ct_ecnt = 0;		/* valid entry count, */
   1179      1.26   jeremy 		c_tbl->ct_pmap = NULL;		/* parent pmap,       */
   1180      1.26   jeremy 		c_tbl->ct_va = 0;		/* base of managed range */
   1181       1.1      gwr 
   1182       1.1      gwr 		/* Assign it the next available MMU C table from the pool */
   1183       1.1      gwr 		c_tbl->ct_dtbl = &mmuCbase[i * MMU_C_TBL_SIZE];
   1184       1.1      gwr 
   1185       1.1      gwr 		for (j=0; j < MMU_C_TBL_SIZE; j++)
   1186       1.1      gwr 			c_tbl->ct_dtbl[j].attr.raw = MMU_DT_INVALID;
   1187       1.1      gwr 
   1188       1.1      gwr 		TAILQ_INSERT_TAIL(&c_pool, c_tbl, ct_link);
   1189       1.1      gwr 	}
   1190       1.1      gwr }
   1191       1.1      gwr 
   1192       1.1      gwr /* pmap_init_pv()			INTERNAL
   1193       1.1      gwr  **
   1194       1.1      gwr  * Initializes the Physical to Virtual mapping system.
   1195       1.1      gwr  */
   1196       1.1      gwr void
   1197       1.1      gwr pmap_init_pv()
   1198       1.1      gwr {
   1199       1.7      gwr 	int	i;
   1200       1.7      gwr 
   1201       1.7      gwr 	/* Initialize every PV head. */
   1202      1.25    veego 	for (i = 0; i < m68k_btop(total_phys_mem); i++) {
   1203       1.7      gwr 		pvbase[i].pv_idx = PVE_EOL;	/* Indicate no mappings */
   1204       1.7      gwr 		pvbase[i].pv_flags = 0;		/* Zero out page flags  */
   1205       1.7      gwr 	}
   1206       1.7      gwr 
   1207       1.1      gwr 	pv_initialized = TRUE;
   1208       1.1      gwr }
   1209       1.1      gwr 
   1210       1.1      gwr /* get_a_table			INTERNAL
   1211       1.1      gwr  **
   1212       1.1      gwr  * Retrieve and return a level A table for use in a user map.
   1213       1.1      gwr  */
   1214       1.1      gwr a_tmgr_t *
   1215       1.1      gwr get_a_table()
   1216       1.1      gwr {
   1217       1.1      gwr 	a_tmgr_t *tbl;
   1218       1.7      gwr 	pmap_t pmap;
   1219       1.1      gwr 
   1220       1.1      gwr 	/* Get the top A table in the pool */
   1221       1.1      gwr 	tbl = a_pool.tqh_first;
   1222       1.7      gwr 	if (tbl == NULL) {
   1223       1.7      gwr 		/*
   1224       1.7      gwr 		 * XXX - Instead of panicing here and in other get_x_table
   1225       1.7      gwr 		 * functions, we do have the option of sleeping on the head of
   1226       1.7      gwr 		 * the table pool.  Any function which updates the table pool
   1227       1.7      gwr 		 * would then issue a wakeup() on the head, thus waking up any
   1228       1.7      gwr 		 * processes waiting for a table.
   1229       1.7      gwr 		 *
   1230       1.7      gwr 		 * Actually, the place to sleep would be when some process
   1231       1.7      gwr 		 * asks for a "wired" mapping that would run us short of
   1232       1.7      gwr 		 * mapping resources.  This design DEPENDS on always having
   1233       1.7      gwr 		 * some mapping resources in the pool for stealing, so we
   1234       1.7      gwr 		 * must make sure we NEVER let the pool become empty. -gwr
   1235       1.7      gwr 		 */
   1236       1.1      gwr 		panic("get_a_table: out of A tables.");
   1237       1.7      gwr 	}
   1238       1.7      gwr 
   1239       1.1      gwr 	TAILQ_REMOVE(&a_pool, tbl, at_link);
   1240       1.7      gwr 	/*
   1241       1.7      gwr 	 * If the table has a non-null parent pointer then it is in use.
   1242       1.1      gwr 	 * Forcibly abduct it from its parent and clear its entries.
   1243       1.1      gwr 	 * No re-entrancy worries here.  This table would not be in the
   1244       1.1      gwr 	 * table pool unless it was available for use.
   1245       1.7      gwr 	 *
   1246       1.7      gwr 	 * Note that the second argument to free_a_table() is FALSE.  This
   1247       1.7      gwr 	 * indicates that the table should not be relinked into the A table
   1248       1.7      gwr 	 * pool.  That is a job for the function that called us.
   1249       1.1      gwr 	 */
   1250       1.1      gwr 	if (tbl->at_parent) {
   1251       1.7      gwr 		pmap = tbl->at_parent;
   1252       1.8      gwr 		free_a_table(tbl, FALSE);
   1253       1.7      gwr 		pmap->pm_a_tmgr = NULL;
   1254       1.7      gwr 		pmap->pm_a_phys = kernAphys;
   1255       1.1      gwr 	}
   1256       1.1      gwr #ifdef  NON_REENTRANT
   1257       1.7      gwr 	/*
   1258       1.7      gwr 	 * If the table isn't to be wired down, re-insert it at the
   1259       1.1      gwr 	 * end of the pool.
   1260       1.1      gwr 	 */
   1261       1.1      gwr 	if (!wired)
   1262       1.7      gwr 		/*
   1263       1.7      gwr 		 * Quandary - XXX
   1264       1.1      gwr 		 * Would it be better to let the calling function insert this
   1265       1.1      gwr 		 * table into the queue?  By inserting it here, we are allowing
   1266       1.1      gwr 		 * it to be stolen immediately.  The calling function is
   1267       1.1      gwr 		 * probably not expecting to use a table that it is not
   1268       1.1      gwr 		 * assured full control of.
   1269       1.1      gwr 		 * Answer - In the intrest of re-entrancy, it is best to let
   1270       1.1      gwr 		 * the calling function determine when a table is available
   1271       1.1      gwr 		 * for use.  Therefore this code block is not used.
   1272       1.1      gwr 		 */
   1273       1.1      gwr 		TAILQ_INSERT_TAIL(&a_pool, tbl, at_link);
   1274       1.1      gwr #endif	/* NON_REENTRANT */
   1275       1.1      gwr 	return tbl;
   1276       1.1      gwr }
   1277       1.1      gwr 
   1278       1.1      gwr /* get_b_table			INTERNAL
   1279       1.1      gwr  **
   1280       1.1      gwr  * Return a level B table for use.
   1281       1.1      gwr  */
   1282       1.1      gwr b_tmgr_t *
   1283       1.1      gwr get_b_table()
   1284       1.1      gwr {
   1285       1.1      gwr 	b_tmgr_t *tbl;
   1286       1.1      gwr 
   1287       1.1      gwr 	/* See 'get_a_table' for comments. */
   1288       1.1      gwr 	tbl = b_pool.tqh_first;
   1289       1.1      gwr 	if (tbl == NULL)
   1290       1.1      gwr 		panic("get_b_table: out of B tables.");
   1291       1.1      gwr 	TAILQ_REMOVE(&b_pool, tbl, bt_link);
   1292       1.1      gwr 	if (tbl->bt_parent) {
   1293       1.1      gwr 		tbl->bt_parent->at_dtbl[tbl->bt_pidx].attr.raw = MMU_DT_INVALID;
   1294       1.1      gwr 		tbl->bt_parent->at_ecnt--;
   1295       1.8      gwr 		free_b_table(tbl, FALSE);
   1296       1.1      gwr 	}
   1297       1.1      gwr #ifdef	NON_REENTRANT
   1298       1.1      gwr 	if (!wired)
   1299       1.1      gwr 		/* XXX see quandary in get_b_table */
   1300       1.1      gwr 		/* XXX start lock */
   1301       1.1      gwr 		TAILQ_INSERT_TAIL(&b_pool, tbl, bt_link);
   1302       1.1      gwr 		/* XXX end lock */
   1303       1.1      gwr #endif	/* NON_REENTRANT */
   1304       1.1      gwr 	return tbl;
   1305       1.1      gwr }
   1306       1.1      gwr 
   1307       1.1      gwr /* get_c_table			INTERNAL
   1308       1.1      gwr  **
   1309       1.1      gwr  * Return a level C table for use.
   1310       1.1      gwr  */
   1311       1.1      gwr c_tmgr_t *
   1312       1.1      gwr get_c_table()
   1313       1.1      gwr {
   1314       1.1      gwr 	c_tmgr_t *tbl;
   1315       1.1      gwr 
   1316       1.1      gwr 	/* See 'get_a_table' for comments */
   1317       1.1      gwr 	tbl = c_pool.tqh_first;
   1318       1.1      gwr 	if (tbl == NULL)
   1319       1.1      gwr 		panic("get_c_table: out of C tables.");
   1320       1.1      gwr 	TAILQ_REMOVE(&c_pool, tbl, ct_link);
   1321       1.1      gwr 	if (tbl->ct_parent) {
   1322       1.1      gwr 		tbl->ct_parent->bt_dtbl[tbl->ct_pidx].attr.raw = MMU_DT_INVALID;
   1323       1.1      gwr 		tbl->ct_parent->bt_ecnt--;
   1324       1.8      gwr 		free_c_table(tbl, FALSE);
   1325       1.1      gwr 	}
   1326       1.1      gwr #ifdef	NON_REENTRANT
   1327       1.1      gwr 	if (!wired)
   1328       1.1      gwr 		/* XXX See quandary in get_a_table */
   1329       1.1      gwr 		/* XXX start lock */
   1330       1.1      gwr 		TAILQ_INSERT_TAIL(&c_pool, tbl, c_link);
   1331       1.1      gwr 		/* XXX end lock */
   1332       1.1      gwr #endif	/* NON_REENTRANT */
   1333       1.1      gwr 
   1334       1.1      gwr 	return tbl;
   1335       1.1      gwr }
   1336       1.1      gwr 
   1337       1.7      gwr /*
   1338       1.7      gwr  * The following 'free_table' and 'steal_table' functions are called to
   1339       1.1      gwr  * detach tables from their current obligations (parents and children) and
   1340       1.1      gwr  * prepare them for reuse in another mapping.
   1341       1.1      gwr  *
   1342       1.1      gwr  * Free_table is used when the calling function will handle the fate
   1343       1.1      gwr  * of the parent table, such as returning it to the free pool when it has
   1344       1.1      gwr  * no valid entries.  Functions that do not want to handle this should
   1345       1.1      gwr  * call steal_table, in which the parent table's descriptors and entry
   1346       1.1      gwr  * count are automatically modified when this table is removed.
   1347       1.1      gwr  */
   1348       1.1      gwr 
   1349       1.1      gwr /* free_a_table			INTERNAL
   1350       1.1      gwr  **
   1351       1.1      gwr  * Unmaps the given A table and all child tables from their current
   1352       1.1      gwr  * mappings.  Returns the number of pages that were invalidated.
   1353       1.7      gwr  * If 'relink' is true, the function will return the table to the head
   1354       1.7      gwr  * of the available table pool.
   1355       1.1      gwr  *
   1356       1.1      gwr  * Cache note: The MC68851 will automatically flush all
   1357       1.1      gwr  * descriptors derived from a given A table from its
   1358       1.1      gwr  * Automatic Translation Cache (ATC) if we issue a
   1359       1.1      gwr  * 'PFLUSHR' instruction with the base address of the
   1360       1.1      gwr  * table.  This function should do, and does so.
   1361       1.1      gwr  * Note note: We are using an MC68030 - there is no
   1362       1.1      gwr  * PFLUSHR.
   1363       1.1      gwr  */
   1364       1.1      gwr int
   1365       1.7      gwr free_a_table(a_tbl, relink)
   1366       1.1      gwr 	a_tmgr_t *a_tbl;
   1367       1.7      gwr 	boolean_t relink;
   1368       1.1      gwr {
   1369       1.1      gwr 	int i, removed_cnt;
   1370       1.1      gwr 	mmu_long_dte_t	*dte;
   1371       1.1      gwr 	mmu_short_dte_t *dtbl;
   1372       1.1      gwr 	b_tmgr_t	*tmgr;
   1373       1.1      gwr 
   1374       1.7      gwr 	/*
   1375       1.7      gwr 	 * Flush the ATC cache of all cached descriptors derived
   1376       1.1      gwr 	 * from this table.
   1377      1.22   jeremy 	 * Sun3x does not use 68851's cached table feature
   1378       1.1      gwr 	 * flush_atc_crp(mmu_vtop(a_tbl->dte));
   1379       1.1      gwr 	 */
   1380       1.1      gwr 
   1381       1.7      gwr 	/*
   1382       1.7      gwr 	 * Remove any pending cache flushes that were designated
   1383       1.1      gwr 	 * for the pmap this A table belongs to.
   1384       1.1      gwr 	 * a_tbl->parent->atc_flushq[0] = 0;
   1385      1.22   jeremy 	 * Not implemented in sun3x.
   1386       1.1      gwr 	 */
   1387       1.1      gwr 
   1388       1.7      gwr 	/*
   1389       1.7      gwr 	 * All A tables in the system should retain a map for the
   1390       1.1      gwr 	 * kernel. If the table contains any valid descriptors
   1391       1.1      gwr 	 * (other than those for the kernel area), invalidate them all,
   1392       1.1      gwr 	 * stopping short of the kernel's entries.
   1393       1.1      gwr 	 */
   1394       1.1      gwr 	removed_cnt = 0;
   1395       1.1      gwr 	if (a_tbl->at_ecnt) {
   1396       1.1      gwr 		dte = a_tbl->at_dtbl;
   1397       1.8      gwr 		for (i=0; i < MMU_TIA(KERNBASE); i++) {
   1398       1.7      gwr 			/*
   1399       1.7      gwr 			 * If a table entry points to a valid B table, free
   1400       1.1      gwr 			 * it and its children.
   1401       1.1      gwr 			 */
   1402       1.1      gwr 			if (MMU_VALID_DT(dte[i])) {
   1403       1.7      gwr 				/*
   1404       1.7      gwr 				 * The following block does several things,
   1405       1.1      gwr 				 * from innermost expression to the
   1406       1.1      gwr 				 * outermost:
   1407       1.1      gwr 				 * 1) It extracts the base (cc 1996)
   1408       1.1      gwr 				 *    address of the B table pointed
   1409       1.1      gwr 				 *    to in the A table entry dte[i].
   1410       1.1      gwr 				 * 2) It converts this base address into
   1411       1.1      gwr 				 *    the virtual address it can be
   1412       1.1      gwr 				 *    accessed with. (all MMU tables point
   1413       1.1      gwr 				 *    to physical addresses.)
   1414       1.1      gwr 				 * 3) It finds the corresponding manager
   1415       1.1      gwr 				 *    structure which manages this MMU table.
   1416       1.1      gwr 				 * 4) It frees the manager structure.
   1417       1.1      gwr 				 *    (This frees the MMU table and all
   1418       1.1      gwr 				 *    child tables. See 'free_b_table' for
   1419       1.1      gwr 				 *    details.)
   1420       1.1      gwr 				 */
   1421       1.7      gwr 				dtbl = mmu_ptov(dte[i].addr.raw);
   1422       1.1      gwr 				tmgr = mmuB2tmgr(dtbl);
   1423       1.7      gwr 				removed_cnt += free_b_table(tmgr, TRUE);
   1424       1.8      gwr 				dte[i].attr.raw = MMU_DT_INVALID;
   1425       1.1      gwr 			}
   1426       1.8      gwr 		}
   1427       1.8      gwr 		a_tbl->at_ecnt = 0;
   1428       1.1      gwr 	}
   1429       1.7      gwr 	if (relink) {
   1430       1.7      gwr 		a_tbl->at_parent = NULL;
   1431       1.7      gwr 		TAILQ_REMOVE(&a_pool, a_tbl, at_link);
   1432       1.7      gwr 		TAILQ_INSERT_HEAD(&a_pool, a_tbl, at_link);
   1433       1.7      gwr 	}
   1434       1.1      gwr 	return removed_cnt;
   1435       1.1      gwr }
   1436       1.1      gwr 
   1437       1.1      gwr /* free_b_table			INTERNAL
   1438       1.1      gwr  **
   1439       1.1      gwr  * Unmaps the given B table and all its children from their current
   1440       1.1      gwr  * mappings.  Returns the number of pages that were invalidated.
   1441       1.1      gwr  * (For comments, see 'free_a_table()').
   1442       1.1      gwr  */
   1443       1.1      gwr int
   1444       1.7      gwr free_b_table(b_tbl, relink)
   1445       1.1      gwr 	b_tmgr_t *b_tbl;
   1446       1.7      gwr 	boolean_t relink;
   1447       1.1      gwr {
   1448       1.1      gwr 	int i, removed_cnt;
   1449       1.1      gwr 	mmu_short_dte_t *dte;
   1450       1.1      gwr 	mmu_short_pte_t	*dtbl;
   1451       1.1      gwr 	c_tmgr_t	*tmgr;
   1452       1.1      gwr 
   1453       1.1      gwr 	removed_cnt = 0;
   1454       1.1      gwr 	if (b_tbl->bt_ecnt) {
   1455       1.1      gwr 		dte = b_tbl->bt_dtbl;
   1456       1.8      gwr 		for (i=0; i < MMU_B_TBL_SIZE; i++) {
   1457       1.1      gwr 			if (MMU_VALID_DT(dte[i])) {
   1458       1.7      gwr 				dtbl = mmu_ptov(MMU_DTE_PA(dte[i]));
   1459       1.1      gwr 				tmgr = mmuC2tmgr(dtbl);
   1460       1.7      gwr 				removed_cnt += free_c_table(tmgr, TRUE);
   1461       1.8      gwr 				dte[i].attr.raw = MMU_DT_INVALID;
   1462       1.1      gwr 			}
   1463       1.8      gwr 		}
   1464       1.8      gwr 		b_tbl->bt_ecnt = 0;
   1465       1.1      gwr 	}
   1466       1.1      gwr 
   1467       1.7      gwr 	if (relink) {
   1468       1.7      gwr 		b_tbl->bt_parent = NULL;
   1469       1.7      gwr 		TAILQ_REMOVE(&b_pool, b_tbl, bt_link);
   1470       1.7      gwr 		TAILQ_INSERT_HEAD(&b_pool, b_tbl, bt_link);
   1471       1.7      gwr 	}
   1472       1.1      gwr 	return removed_cnt;
   1473       1.1      gwr }
   1474       1.1      gwr 
   1475       1.1      gwr /* free_c_table			INTERNAL
   1476       1.1      gwr  **
   1477       1.1      gwr  * Unmaps the given C table from use and returns it to the pool for
   1478       1.1      gwr  * re-use.  Returns the number of pages that were invalidated.
   1479       1.1      gwr  *
   1480       1.1      gwr  * This function preserves any physical page modification information
   1481       1.1      gwr  * contained in the page descriptors within the C table by calling
   1482       1.1      gwr  * 'pmap_remove_pte().'
   1483       1.1      gwr  */
   1484       1.1      gwr int
   1485       1.7      gwr free_c_table(c_tbl, relink)
   1486       1.1      gwr 	c_tmgr_t *c_tbl;
   1487       1.7      gwr 	boolean_t relink;
   1488       1.1      gwr {
   1489       1.1      gwr 	int i, removed_cnt;
   1490       1.1      gwr 
   1491       1.1      gwr 	removed_cnt = 0;
   1492       1.8      gwr 	if (c_tbl->ct_ecnt) {
   1493       1.8      gwr 		for (i=0; i < MMU_C_TBL_SIZE; i++) {
   1494       1.1      gwr 			if (MMU_VALID_DT(c_tbl->ct_dtbl[i])) {
   1495       1.1      gwr 				pmap_remove_pte(&c_tbl->ct_dtbl[i]);
   1496       1.1      gwr 				removed_cnt++;
   1497       1.1      gwr 			}
   1498       1.8      gwr 		}
   1499       1.8      gwr 		c_tbl->ct_ecnt = 0;
   1500       1.8      gwr 	}
   1501       1.8      gwr 
   1502       1.7      gwr 	if (relink) {
   1503       1.7      gwr 		c_tbl->ct_parent = NULL;
   1504       1.7      gwr 		TAILQ_REMOVE(&c_pool, c_tbl, ct_link);
   1505       1.7      gwr 		TAILQ_INSERT_HEAD(&c_pool, c_tbl, ct_link);
   1506       1.7      gwr 	}
   1507       1.1      gwr 	return removed_cnt;
   1508       1.1      gwr }
   1509       1.1      gwr 
   1510       1.8      gwr #if 0
   1511       1.1      gwr /* free_c_table_novalid			INTERNAL
   1512       1.1      gwr  **
   1513       1.1      gwr  * Frees the given C table manager without checking to see whether
   1514       1.1      gwr  * or not it contains any valid page descriptors as it is assumed
   1515       1.1      gwr  * that it does not.
   1516       1.1      gwr  */
   1517       1.1      gwr void
   1518       1.1      gwr free_c_table_novalid(c_tbl)
   1519       1.1      gwr 	c_tmgr_t *c_tbl;
   1520       1.1      gwr {
   1521       1.1      gwr 	TAILQ_REMOVE(&c_pool, c_tbl, ct_link);
   1522       1.1      gwr 	TAILQ_INSERT_HEAD(&c_pool, c_tbl, ct_link);
   1523       1.1      gwr 	c_tbl->ct_parent->bt_dtbl[c_tbl->ct_pidx].attr.raw = MMU_DT_INVALID;
   1524       1.7      gwr 	c_tbl->ct_parent->bt_ecnt--;
   1525       1.7      gwr 	/*
   1526       1.7      gwr 	 * XXX - Should call equiv. of 'free_b_table_novalid' here if
   1527       1.7      gwr 	 * we just removed the last entry of the parent B table.
   1528       1.7      gwr 	 * But I want to insure that this will not endanger pmap_enter()
   1529       1.7      gwr 	 * with sudden removal of tables it is working with.
   1530       1.7      gwr 	 *
   1531       1.7      gwr 	 * We should probably add another field to each table, indicating
   1532       1.7      gwr 	 * whether or not it is 'locked', ie. in the process of being
   1533       1.7      gwr 	 * modified.
   1534       1.7      gwr 	 */
   1535       1.7      gwr 	c_tbl->ct_parent = NULL;
   1536       1.1      gwr }
   1537       1.8      gwr #endif
   1538       1.1      gwr 
   1539       1.1      gwr /* pmap_remove_pte			INTERNAL
   1540       1.1      gwr  **
   1541       1.1      gwr  * Unmap the given pte and preserve any page modification
   1542       1.1      gwr  * information by transfering it to the pv head of the
   1543       1.1      gwr  * physical page it maps to.  This function does not update
   1544       1.1      gwr  * any reference counts because it is assumed that the calling
   1545       1.8      gwr  * function will do so.
   1546       1.1      gwr  */
   1547       1.1      gwr void
   1548       1.1      gwr pmap_remove_pte(pte)
   1549       1.1      gwr 	mmu_short_pte_t *pte;
   1550       1.1      gwr {
   1551       1.7      gwr 	u_short     pv_idx, targ_idx;
   1552       1.7      gwr 	int         s;
   1553       1.1      gwr 	vm_offset_t pa;
   1554       1.1      gwr 	pv_t       *pv;
   1555       1.1      gwr 
   1556       1.1      gwr 	pa = MMU_PTE_PA(*pte);
   1557       1.1      gwr 	if (is_managed(pa)) {
   1558       1.1      gwr 		pv = pa2pv(pa);
   1559       1.7      gwr 		targ_idx = pteidx(pte);	/* Index of PTE being removed    */
   1560       1.7      gwr 
   1561       1.7      gwr 		/*
   1562       1.7      gwr 		 * If the PTE being removed is the first (or only) PTE in
   1563       1.7      gwr 		 * the list of PTEs currently mapped to this page, remove the
   1564       1.7      gwr 		 * PTE by changing the index found on the PV head.  Otherwise
   1565       1.7      gwr 		 * a linear search through the list will have to be executed
   1566       1.7      gwr 		 * in order to find the PVE which points to the PTE being
   1567       1.7      gwr 		 * removed, so that it may be modified to point to its new
   1568       1.7      gwr 		 * neighbor.
   1569       1.7      gwr 		 */
   1570  1.50.2.4   bouyer 		s = splvm();
   1571       1.7      gwr 		pv_idx = pv->pv_idx;	/* Index of first PTE in PV list */
   1572       1.7      gwr 		if (pv_idx == targ_idx) {
   1573       1.7      gwr 			pv->pv_idx = pvebase[targ_idx].pve_next;
   1574       1.7      gwr 		} else {
   1575       1.7      gwr 			/*
   1576      1.32      gwr 			 * Find the PV element pointing to the target
   1577      1.32      gwr 			 * element.  Note: may have pv_idx==PVE_EOL
   1578       1.7      gwr 			 */
   1579      1.32      gwr 			for (;;) {
   1580      1.32      gwr 				if (pv_idx == PVE_EOL) {
   1581      1.32      gwr #ifdef	PMAP_DEBUG
   1582      1.32      gwr 					printf("pmap_remove_pte: PVE_EOL\n");
   1583      1.32      gwr 					Debugger();
   1584      1.32      gwr #endif
   1585      1.32      gwr 					goto pv_not_found;
   1586      1.32      gwr 				}
   1587      1.32      gwr 				if (pvebase[pv_idx].pve_next == targ_idx)
   1588      1.32      gwr 					break;
   1589       1.7      gwr 				pv_idx = pvebase[pv_idx].pve_next;
   1590       1.7      gwr 			}
   1591       1.7      gwr 			/*
   1592       1.7      gwr 			 * At this point, pv_idx is the index of the PV
   1593       1.7      gwr 			 * element just before the target element in the list.
   1594       1.7      gwr 			 * Unlink the target.
   1595       1.7      gwr 			 */
   1596       1.7      gwr 			pvebase[pv_idx].pve_next = pvebase[targ_idx].pve_next;
   1597      1.32      gwr 		pv_not_found:
   1598       1.7      gwr 		}
   1599       1.7      gwr 		/*
   1600       1.7      gwr 		 * Save the mod/ref bits of the pte by simply
   1601       1.1      gwr 		 * ORing the entire pte onto the pv_flags member
   1602       1.1      gwr 		 * of the pv structure.
   1603       1.1      gwr 		 * There is no need to use a separate bit pattern
   1604       1.1      gwr 		 * for usage information on the pv head than that
   1605       1.1      gwr 		 * which is used on the MMU ptes.
   1606       1.1      gwr 		 */
   1607       1.7      gwr 		pv->pv_flags |= (u_short) pte->attr.raw;
   1608       1.7      gwr 		splx(s);
   1609       1.1      gwr 	}
   1610       1.1      gwr 
   1611       1.1      gwr 	pte->attr.raw = MMU_DT_INVALID;
   1612       1.1      gwr }
   1613       1.1      gwr 
   1614       1.1      gwr /* pmap_stroll			INTERNAL
   1615       1.1      gwr  **
   1616       1.1      gwr  * Retrieve the addresses of all table managers involved in the mapping of
   1617       1.1      gwr  * the given virtual address.  If the table walk completed sucessfully,
   1618       1.7      gwr  * return TRUE.  If it was only partially sucessful, return FALSE.
   1619       1.1      gwr  * The table walk performed by this function is important to many other
   1620       1.1      gwr  * functions in this module.
   1621       1.7      gwr  *
   1622       1.7      gwr  * Note: This function ought to be easier to read.
   1623       1.1      gwr  */
   1624       1.1      gwr boolean_t
   1625       1.1      gwr pmap_stroll(pmap, va, a_tbl, b_tbl, c_tbl, pte, a_idx, b_idx, pte_idx)
   1626       1.1      gwr 	pmap_t pmap;
   1627       1.1      gwr 	vm_offset_t va;
   1628       1.1      gwr 	a_tmgr_t **a_tbl;
   1629       1.1      gwr 	b_tmgr_t **b_tbl;
   1630       1.1      gwr 	c_tmgr_t **c_tbl;
   1631       1.1      gwr 	mmu_short_pte_t **pte;
   1632       1.1      gwr 	int *a_idx, *b_idx, *pte_idx;
   1633       1.1      gwr {
   1634       1.1      gwr 	mmu_long_dte_t *a_dte;   /* A: long descriptor table          */
   1635       1.1      gwr 	mmu_short_dte_t *b_dte;  /* B: short descriptor table         */
   1636       1.1      gwr 
   1637       1.1      gwr 	if (pmap == pmap_kernel())
   1638       1.1      gwr 		return FALSE;
   1639       1.1      gwr 
   1640       1.7      gwr 	/* Does the given pmap have its own A table? */
   1641       1.7      gwr 	*a_tbl = pmap->pm_a_tmgr;
   1642       1.1      gwr 	if (*a_tbl == NULL)
   1643       1.1      gwr 		return FALSE; /* No.  Return unknown. */
   1644       1.1      gwr 	/* Does the A table have a valid B table
   1645       1.1      gwr 	 * under the corresponding table entry?
   1646       1.1      gwr 	 */
   1647       1.1      gwr 	*a_idx = MMU_TIA(va);
   1648       1.1      gwr 	a_dte = &((*a_tbl)->at_dtbl[*a_idx]);
   1649       1.1      gwr 	if (!MMU_VALID_DT(*a_dte))
   1650       1.1      gwr 		return FALSE; /* No. Return unknown. */
   1651       1.1      gwr 	/* Yes. Extract B table from the A table. */
   1652       1.7      gwr 	*b_tbl = mmuB2tmgr(mmu_ptov(a_dte->addr.raw));
   1653       1.1      gwr 	/* Does the B table have a valid C table
   1654       1.1      gwr 	 * under the corresponding table entry?
   1655       1.1      gwr 	 */
   1656       1.1      gwr 	*b_idx = MMU_TIB(va);
   1657       1.1      gwr 	b_dte = &((*b_tbl)->bt_dtbl[*b_idx]);
   1658       1.1      gwr 	if (!MMU_VALID_DT(*b_dte))
   1659       1.1      gwr 		return FALSE; /* No. Return unknown. */
   1660       1.1      gwr 	/* Yes. Extract C table from the B table. */
   1661       1.7      gwr 	*c_tbl = mmuC2tmgr(mmu_ptov(MMU_DTE_PA(*b_dte)));
   1662       1.1      gwr 	*pte_idx = MMU_TIC(va);
   1663       1.1      gwr 	*pte = &((*c_tbl)->ct_dtbl[*pte_idx]);
   1664       1.1      gwr 
   1665       1.1      gwr 	return	TRUE;
   1666       1.1      gwr }
   1667       1.1      gwr 
   1668       1.1      gwr /* pmap_enter			INTERFACE
   1669       1.1      gwr  **
   1670       1.1      gwr  * Called by the kernel to map a virtual address
   1671       1.1      gwr  * to a physical address in the given process map.
   1672       1.1      gwr  *
   1673       1.1      gwr  * Note: this function should apply an exclusive lock
   1674       1.1      gwr  * on the pmap system for its duration.  (it certainly
   1675       1.1      gwr  * would save my hair!!)
   1676       1.7      gwr  * This function ought to be easier to read.
   1677       1.1      gwr  */
   1678  1.50.2.1   bouyer int
   1679  1.50.2.1   bouyer pmap_enter(pmap, va, pa, prot, flags)
   1680       1.1      gwr 	pmap_t	pmap;
   1681       1.1      gwr 	vm_offset_t va;
   1682       1.1      gwr 	vm_offset_t pa;
   1683       1.1      gwr 	vm_prot_t prot;
   1684  1.50.2.1   bouyer 	int flags;
   1685       1.1      gwr {
   1686       1.7      gwr 	boolean_t insert, managed; /* Marks the need for PV insertion.*/
   1687       1.7      gwr 	u_short nidx;            /* PV list index                     */
   1688  1.50.2.4   bouyer 	int s;                   /* Used for splvm()/splx()           */
   1689  1.50.2.1   bouyer 	int mapflags;            /* Flags for the mapping (see NOTE1) */
   1690       1.8      gwr 	u_int a_idx, b_idx, pte_idx; /* table indices                 */
   1691       1.1      gwr 	a_tmgr_t *a_tbl;         /* A: long descriptor table manager  */
   1692       1.1      gwr 	b_tmgr_t *b_tbl;         /* B: short descriptor table manager */
   1693       1.1      gwr 	c_tmgr_t *c_tbl;         /* C: short page table manager       */
   1694       1.1      gwr 	mmu_long_dte_t *a_dte;   /* A: long descriptor table          */
   1695       1.1      gwr 	mmu_short_dte_t *b_dte;  /* B: short descriptor table         */
   1696       1.1      gwr 	mmu_short_pte_t *c_pte;  /* C: short page descriptor table    */
   1697       1.1      gwr 	pv_t      *pv;           /* pv list head                      */
   1698  1.50.2.1   bouyer 	boolean_t wired;         /* is the mapping to be wired?       */
   1699       1.1      gwr 	enum {NONE, NEWA, NEWB, NEWC} llevel; /* used at end   */
   1700       1.1      gwr 
   1701       1.1      gwr 	if (pmap == NULL)
   1702  1.50.2.1   bouyer 		return (KERN_SUCCESS);
   1703       1.1      gwr 	if (pmap == pmap_kernel()) {
   1704       1.1      gwr 		pmap_enter_kernel(va, pa, prot);
   1705  1.50.2.1   bouyer 		return (KERN_SUCCESS);
   1706       1.1      gwr 	}
   1707       1.7      gwr 
   1708  1.50.2.1   bouyer 	/*
   1709  1.50.2.1   bouyer 	 * Determine if the mapping should be wired.
   1710  1.50.2.1   bouyer 	 */
   1711  1.50.2.1   bouyer 	wired = ((flags & PMAP_WIRED) != 0);
   1712  1.50.2.1   bouyer 
   1713  1.50.2.1   bouyer 	/*
   1714  1.50.2.1   bouyer 	 * NOTE1:
   1715  1.50.2.1   bouyer 	 *
   1716  1.50.2.1   bouyer 	 * On November 13, 1999, someone changed the pmap_enter() API such
   1717  1.50.2.1   bouyer 	 * that it now accepts a 'flags' argument.  This new argument
   1718  1.50.2.1   bouyer 	 * contains bit-flags for the architecture-independent (UVM) system to
   1719  1.50.2.1   bouyer 	 * use in signalling certain mapping requirements to the architecture-
   1720  1.50.2.1   bouyer 	 * dependent (pmap) system.  The argument it replaces, 'wired', is now
   1721  1.50.2.1   bouyer 	 * one of the flags within it.
   1722  1.50.2.1   bouyer 	 *
   1723  1.50.2.1   bouyer 	 * In addition to flags signaled by the architecture-independent
   1724  1.50.2.1   bouyer 	 * system, parts of the architecture-dependent section of the sun3x
   1725  1.50.2.1   bouyer 	 * kernel pass their own flags in the lower, unused bits of the
   1726  1.50.2.1   bouyer 	 * physical address supplied to this function.  These flags are
   1727  1.50.2.1   bouyer 	 * extracted and stored in the temporary variable 'mapflags'.
   1728  1.50.2.1   bouyer 	 *
   1729  1.50.2.1   bouyer 	 * Extract sun3x specific flags from the physical address.
   1730  1.50.2.1   bouyer 	 */
   1731  1.50.2.1   bouyer 	mapflags  = (pa & ~MMU_PAGE_MASK);
   1732  1.50.2.1   bouyer 	pa       &= MMU_PAGE_MASK;
   1733       1.7      gwr 
   1734       1.7      gwr 	/*
   1735      1.22   jeremy 	 * Determine if the physical address being mapped is on-board RAM.
   1736      1.22   jeremy 	 * Any other area of the address space is likely to belong to a
   1737      1.22   jeremy 	 * device and hence it would be disasterous to cache its contents.
   1738       1.7      gwr 	 */
   1739       1.7      gwr 	if ((managed = is_managed(pa)) == FALSE)
   1740  1.50.2.1   bouyer 		mapflags |= PMAP_NC;
   1741       1.7      gwr 
   1742       1.7      gwr 	/*
   1743       1.7      gwr 	 * For user mappings we walk along the MMU tables of the given
   1744       1.1      gwr 	 * pmap, reaching a PTE which describes the virtual page being
   1745       1.1      gwr 	 * mapped or changed.  If any level of the walk ends in an invalid
   1746       1.1      gwr 	 * entry, a table must be allocated and the entry must be updated
   1747       1.1      gwr 	 * to point to it.
   1748       1.1      gwr 	 * There is a bit of confusion as to whether this code must be
   1749       1.1      gwr 	 * re-entrant.  For now we will assume it is.  To support
   1750       1.1      gwr 	 * re-entrancy we must unlink tables from the table pool before
   1751       1.1      gwr 	 * we assume we may use them.  Tables are re-linked into the pool
   1752       1.1      gwr 	 * when we are finished with them at the end of the function.
   1753       1.1      gwr 	 * But I don't feel like doing that until we have proof that this
   1754       1.1      gwr 	 * needs to be re-entrant.
   1755       1.1      gwr 	 * 'llevel' records which tables need to be relinked.
   1756       1.1      gwr 	 */
   1757       1.1      gwr 	llevel = NONE;
   1758       1.1      gwr 
   1759       1.7      gwr 	/*
   1760       1.7      gwr 	 * Step 1 - Retrieve the A table from the pmap.  If it has no
   1761       1.7      gwr 	 * A table, allocate a new one from the available pool.
   1762       1.1      gwr 	 */
   1763       1.1      gwr 
   1764       1.7      gwr 	a_tbl = pmap->pm_a_tmgr;
   1765       1.7      gwr 	if (a_tbl == NULL) {
   1766       1.7      gwr 		/*
   1767       1.7      gwr 		 * This pmap does not currently have an A table.  Allocate
   1768       1.7      gwr 		 * a new one.
   1769       1.7      gwr 		 */
   1770       1.7      gwr 		a_tbl = get_a_table();
   1771       1.7      gwr 		a_tbl->at_parent = pmap;
   1772       1.7      gwr 
   1773       1.7      gwr 		/*
   1774       1.7      gwr 		 * Assign this new A table to the pmap, and calculate its
   1775       1.7      gwr 		 * physical address so that loadcrp() can be used to make
   1776       1.7      gwr 		 * the table active.
   1777       1.7      gwr 		 */
   1778       1.7      gwr 		pmap->pm_a_tmgr = a_tbl;
   1779       1.7      gwr 		pmap->pm_a_phys = mmu_vtop(a_tbl->at_dtbl);
   1780       1.7      gwr 
   1781       1.7      gwr 		/*
   1782       1.7      gwr 		 * If the process receiving a new A table is the current
   1783       1.7      gwr 		 * process, we are responsible for setting the MMU so that
   1784       1.9      gwr 		 * it becomes the current address space.  This only adds
   1785       1.9      gwr 		 * new mappings, so no need to flush anything.
   1786       1.7      gwr 		 */
   1787       1.9      gwr 		if (pmap == current_pmap()) {
   1788       1.9      gwr 			kernel_crp.rp_addr = pmap->pm_a_phys;
   1789       1.9      gwr 			loadcrp(&kernel_crp);
   1790       1.9      gwr 		}
   1791       1.7      gwr 
   1792       1.1      gwr 		if (!wired)
   1793       1.1      gwr 			llevel = NEWA;
   1794       1.1      gwr 	} else {
   1795       1.7      gwr 		/*
   1796       1.7      gwr 		 * Use the A table already allocated for this pmap.
   1797       1.1      gwr 		 * Unlink it from the A table pool if necessary.
   1798       1.1      gwr 		 */
   1799       1.1      gwr 		if (wired && !a_tbl->at_wcnt)
   1800       1.1      gwr 			TAILQ_REMOVE(&a_pool, a_tbl, at_link);
   1801       1.1      gwr 	}
   1802       1.1      gwr 
   1803       1.7      gwr 	/*
   1804       1.7      gwr 	 * Step 2 - Walk into the B table.  If there is no valid B table,
   1805       1.1      gwr 	 * allocate one.
   1806       1.1      gwr 	 */
   1807       1.1      gwr 
   1808       1.1      gwr 	a_idx = MMU_TIA(va);            /* Calculate the TIA of the VA. */
   1809       1.1      gwr 	a_dte = &a_tbl->at_dtbl[a_idx]; /* Retrieve descriptor from table */
   1810       1.1      gwr 	if (MMU_VALID_DT(*a_dte)) {     /* Is the descriptor valid? */
   1811       1.7      gwr 		/* The descriptor is valid.  Use the B table it points to. */
   1812       1.1      gwr 		/*************************************
   1813       1.1      gwr 		 *               a_idx               *
   1814       1.1      gwr 		 *                 v                 *
   1815       1.1      gwr 		 * a_tbl -> +-+-+-+-+-+-+-+-+-+-+-+- *
   1816       1.1      gwr 		 *          | | | | | | | | | | | |  *
   1817       1.1      gwr 		 *          +-+-+-+-+-+-+-+-+-+-+-+- *
   1818       1.1      gwr 		 *                 |                 *
   1819       1.1      gwr 		 *                 \- b_tbl -> +-+-  *
   1820       1.1      gwr 		 *                             | |   *
   1821       1.1      gwr 		 *                             +-+-  *
   1822       1.1      gwr 		 *************************************/
   1823       1.7      gwr 		b_dte = mmu_ptov(a_dte->addr.raw);
   1824       1.1      gwr 		b_tbl = mmuB2tmgr(b_dte);
   1825       1.7      gwr 
   1826       1.7      gwr 		/*
   1827       1.7      gwr 		 * If the requested mapping must be wired, but this table
   1828       1.7      gwr 		 * being used to map it is not, the table must be removed
   1829       1.7      gwr 		 * from the available pool and its wired entry count
   1830       1.7      gwr 		 * incremented.
   1831       1.7      gwr 		 */
   1832       1.1      gwr 		if (wired && !b_tbl->bt_wcnt) {
   1833       1.1      gwr 			TAILQ_REMOVE(&b_pool, b_tbl, bt_link);
   1834       1.7      gwr 			a_tbl->at_wcnt++;
   1835       1.1      gwr 		}
   1836       1.1      gwr 	} else {
   1837       1.7      gwr 		/* The descriptor is invalid.  Allocate a new B table. */
   1838       1.7      gwr 		b_tbl = get_b_table();
   1839       1.7      gwr 
   1840       1.1      gwr 		/* Point the parent A table descriptor to this new B table. */
   1841       1.7      gwr 		a_dte->addr.raw = mmu_vtop(b_tbl->bt_dtbl);
   1842       1.7      gwr 		a_dte->attr.raw = MMU_LONG_DTE_LU | MMU_DT_SHORT;
   1843       1.7      gwr 		a_tbl->at_ecnt++; /* Update parent's valid entry count */
   1844       1.7      gwr 
   1845       1.1      gwr 		/* Create the necessary back references to the parent table */
   1846       1.1      gwr 		b_tbl->bt_parent = a_tbl;
   1847       1.1      gwr 		b_tbl->bt_pidx = a_idx;
   1848       1.7      gwr 
   1849       1.7      gwr 		/*
   1850       1.7      gwr 		 * If this table is to be wired, make sure the parent A table
   1851       1.1      gwr 		 * wired count is updated to reflect that it has another wired
   1852       1.1      gwr 		 * entry.
   1853       1.1      gwr 		 */
   1854       1.1      gwr 		if (wired)
   1855       1.1      gwr 			a_tbl->at_wcnt++;
   1856       1.1      gwr 		else if (llevel == NONE)
   1857       1.1      gwr 			llevel = NEWB;
   1858       1.1      gwr 	}
   1859       1.1      gwr 
   1860       1.7      gwr 	/*
   1861       1.7      gwr 	 * Step 3 - Walk into the C table, if there is no valid C table,
   1862       1.1      gwr 	 * allocate one.
   1863       1.1      gwr 	 */
   1864       1.1      gwr 
   1865       1.1      gwr 	b_idx = MMU_TIB(va);            /* Calculate the TIB of the VA */
   1866       1.1      gwr 	b_dte = &b_tbl->bt_dtbl[b_idx]; /* Retrieve descriptor from table */
   1867       1.1      gwr 	if (MMU_VALID_DT(*b_dte)) {     /* Is the descriptor valid? */
   1868       1.7      gwr 		/* The descriptor is valid.  Use the C table it points to. */
   1869       1.1      gwr 		/**************************************
   1870       1.1      gwr 		 *               c_idx                *
   1871       1.1      gwr 		 * |                v                 *
   1872       1.1      gwr 		 * \- b_tbl -> +-+-+-+-+-+-+-+-+-+-+- *
   1873       1.1      gwr 		 *             | | | | | | | | | | |  *
   1874       1.1      gwr 		 *             +-+-+-+-+-+-+-+-+-+-+- *
   1875       1.1      gwr 		 *                  |                 *
   1876       1.1      gwr 		 *                  \- c_tbl -> +-+-- *
   1877       1.1      gwr 		 *                              | | | *
   1878       1.1      gwr 		 *                              +-+-- *
   1879       1.1      gwr 		 **************************************/
   1880       1.7      gwr 		c_pte = mmu_ptov(MMU_PTE_PA(*b_dte));
   1881       1.1      gwr 		c_tbl = mmuC2tmgr(c_pte);
   1882       1.7      gwr 
   1883       1.7      gwr 		/* If mapping is wired and table is not */
   1884       1.1      gwr 		if (wired && !c_tbl->ct_wcnt) {
   1885       1.1      gwr 			TAILQ_REMOVE(&c_pool, c_tbl, ct_link);
   1886       1.1      gwr 			b_tbl->bt_wcnt++;
   1887       1.1      gwr 		}
   1888       1.1      gwr 	} else {
   1889       1.7      gwr 		/* The descriptor is invalid.  Allocate a new C table. */
   1890       1.7      gwr 		c_tbl = get_c_table();
   1891       1.7      gwr 
   1892       1.1      gwr 		/* Point the parent B table descriptor to this new C table. */
   1893       1.7      gwr 		b_dte->attr.raw = mmu_vtop(c_tbl->ct_dtbl);
   1894       1.7      gwr 		b_dte->attr.raw |= MMU_DT_SHORT;
   1895       1.7      gwr 		b_tbl->bt_ecnt++; /* Update parent's valid entry count */
   1896       1.7      gwr 
   1897       1.1      gwr 		/* Create the necessary back references to the parent table */
   1898       1.1      gwr 		c_tbl->ct_parent = b_tbl;
   1899       1.1      gwr 		c_tbl->ct_pidx = b_idx;
   1900      1.26   jeremy 		/*
   1901      1.26   jeremy 		 * Store the pmap and base virtual managed address for faster
   1902      1.26   jeremy 		 * retrieval in the PV functions.
   1903      1.26   jeremy 		 */
   1904      1.26   jeremy 		c_tbl->ct_pmap = pmap;
   1905      1.26   jeremy 		c_tbl->ct_va = (va & (MMU_TIA_MASK|MMU_TIB_MASK));
   1906       1.7      gwr 
   1907       1.7      gwr 		/*
   1908       1.7      gwr 		 * If this table is to be wired, make sure the parent B table
   1909       1.1      gwr 		 * wired count is updated to reflect that it has another wired
   1910       1.1      gwr 		 * entry.
   1911       1.1      gwr 		 */
   1912       1.1      gwr 		if (wired)
   1913       1.1      gwr 			b_tbl->bt_wcnt++;
   1914       1.1      gwr 		else if (llevel == NONE)
   1915       1.1      gwr 			llevel = NEWC;
   1916       1.1      gwr 	}
   1917       1.1      gwr 
   1918       1.7      gwr 	/*
   1919       1.7      gwr 	 * Step 4 - Deposit a page descriptor (PTE) into the appropriate
   1920       1.1      gwr 	 * slot of the C table, describing the PA to which the VA is mapped.
   1921       1.1      gwr 	 */
   1922       1.1      gwr 
   1923       1.1      gwr 	pte_idx = MMU_TIC(va);
   1924       1.1      gwr 	c_pte = &c_tbl->ct_dtbl[pte_idx];
   1925       1.1      gwr 	if (MMU_VALID_DT(*c_pte)) { /* Is the entry currently valid? */
   1926       1.7      gwr 		/*
   1927       1.7      gwr 		 * The PTE is currently valid.  This particular call
   1928       1.1      gwr 		 * is just a synonym for one (or more) of the following
   1929       1.1      gwr 		 * operations:
   1930       1.7      gwr 		 *     change protection of a page
   1931       1.1      gwr 		 *     change wiring status of a page
   1932       1.1      gwr 		 *     remove the mapping of a page
   1933       1.7      gwr 		 *
   1934       1.7      gwr 		 * XXX - Semi critical: This code should unwire the PTE
   1935       1.7      gwr 		 * and, possibly, associated parent tables if this is a
   1936       1.7      gwr 		 * change wiring operation.  Currently it does not.
   1937       1.7      gwr 		 *
   1938      1.47  thorpej 		 * This may be ok if pmap_unwire() is the only
   1939       1.7      gwr 		 * interface used to UNWIRE a page.
   1940       1.1      gwr 		 */
   1941       1.7      gwr 
   1942       1.7      gwr 		/* First check if this is a wiring operation. */
   1943       1.7      gwr 		if (wired && (c_pte->attr.raw & MMU_SHORT_PTE_WIRED)) {
   1944       1.7      gwr 			/*
   1945       1.7      gwr 			 * The PTE is already wired.  To prevent it from being
   1946       1.7      gwr 			 * counted as a new wiring operation, reset the 'wired'
   1947       1.7      gwr 			 * variable.
   1948       1.7      gwr 			 */
   1949       1.7      gwr 			wired = FALSE;
   1950       1.7      gwr 		}
   1951       1.7      gwr 
   1952       1.1      gwr 		/* Is the new address the same as the old? */
   1953       1.1      gwr 		if (MMU_PTE_PA(*c_pte) == pa) {
   1954       1.7      gwr 			/*
   1955       1.7      gwr 			 * Yes, mark that it does not need to be reinserted
   1956       1.7      gwr 			 * into the PV list.
   1957       1.7      gwr 			 */
   1958       1.7      gwr 			insert = FALSE;
   1959       1.7      gwr 
   1960       1.7      gwr 			/*
   1961       1.7      gwr 			 * Clear all but the modified, referenced and wired
   1962       1.7      gwr 			 * bits on the PTE.
   1963       1.7      gwr 			 */
   1964       1.7      gwr 			c_pte->attr.raw &= (MMU_SHORT_PTE_M
   1965       1.7      gwr 				| MMU_SHORT_PTE_USED | MMU_SHORT_PTE_WIRED);
   1966       1.1      gwr 		} else {
   1967       1.1      gwr 			/* No, remove the old entry */
   1968       1.1      gwr 			pmap_remove_pte(c_pte);
   1969       1.7      gwr 			insert = TRUE;
   1970       1.1      gwr 		}
   1971       1.8      gwr 
   1972       1.8      gwr 		/*
   1973       1.8      gwr 		 * TLB flush is only necessary if modifying current map.
   1974       1.8      gwr 		 * However, in pmap_enter(), the pmap almost always IS
   1975       1.8      gwr 		 * the current pmap, so don't even bother to check.
   1976       1.8      gwr 		 */
   1977       1.8      gwr 		TBIS(va);
   1978       1.1      gwr 	} else {
   1979       1.7      gwr 		/*
   1980       1.7      gwr 		 * The PTE is invalid.  Increment the valid entry count in
   1981       1.8      gwr 		 * the C table manager to reflect the addition of a new entry.
   1982       1.7      gwr 		 */
   1983       1.1      gwr 		c_tbl->ct_ecnt++;
   1984       1.8      gwr 
   1985       1.8      gwr 		/* XXX - temporarily make sure the PTE is cleared. */
   1986       1.8      gwr 		c_pte->attr.raw = 0;
   1987       1.1      gwr 
   1988       1.7      gwr 		/* It will also need to be inserted into the PV list. */
   1989       1.7      gwr 		insert = TRUE;
   1990       1.7      gwr 	}
   1991       1.7      gwr 
   1992       1.7      gwr 	/*
   1993       1.7      gwr 	 * If page is changing from unwired to wired status, set an unused bit
   1994       1.7      gwr 	 * within the PTE to indicate that it is wired.  Also increment the
   1995       1.7      gwr 	 * wired entry count in the C table manager.
   1996       1.7      gwr 	 */
   1997       1.7      gwr 	if (wired) {
   1998       1.1      gwr 		c_pte->attr.raw |= MMU_SHORT_PTE_WIRED;
   1999       1.7      gwr 		c_tbl->ct_wcnt++;
   2000       1.1      gwr 	}
   2001       1.1      gwr 
   2002       1.7      gwr 	/*
   2003       1.7      gwr 	 * Map the page, being careful to preserve modify/reference/wired
   2004       1.7      gwr 	 * bits.  At this point it is assumed that the PTE either has no bits
   2005       1.7      gwr 	 * set, or if there are set bits, they are only modified, reference or
   2006       1.7      gwr 	 * wired bits.  If not, the following statement will cause erratic
   2007       1.7      gwr 	 * behavior.
   2008       1.7      gwr 	 */
   2009       1.8      gwr #ifdef	PMAP_DEBUG
   2010       1.7      gwr 	if (c_pte->attr.raw & ~(MMU_SHORT_PTE_M |
   2011       1.7      gwr 		MMU_SHORT_PTE_USED | MMU_SHORT_PTE_WIRED)) {
   2012       1.7      gwr 		printf("pmap_enter: junk left in PTE at %p\n", c_pte);
   2013       1.7      gwr 		Debugger();
   2014       1.7      gwr 	}
   2015       1.7      gwr #endif
   2016       1.7      gwr 	c_pte->attr.raw |= ((u_long) pa | MMU_DT_PAGE);
   2017       1.7      gwr 
   2018       1.7      gwr 	/*
   2019       1.7      gwr 	 * If the mapping should be read-only, set the write protect
   2020       1.7      gwr 	 * bit in the PTE.
   2021       1.7      gwr 	 */
   2022       1.7      gwr 	if (!(prot & VM_PROT_WRITE))
   2023       1.7      gwr 		c_pte->attr.raw |= MMU_SHORT_PTE_WP;
   2024       1.7      gwr 
   2025       1.7      gwr 	/*
   2026       1.7      gwr 	 * If the mapping should be cache inhibited (indicated by the flag
   2027       1.7      gwr 	 * bits found on the lower order of the physical address.)
   2028       1.7      gwr 	 * mark the PTE as a cache inhibited page.
   2029       1.7      gwr 	 */
   2030  1.50.2.1   bouyer 	if (mapflags & PMAP_NC)
   2031       1.7      gwr 		c_pte->attr.raw |= MMU_SHORT_PTE_CI;
   2032       1.7      gwr 
   2033       1.7      gwr 	/*
   2034       1.7      gwr 	 * If the physical address being mapped is managed by the PV
   2035       1.7      gwr 	 * system then link the pte into the list of pages mapped to that
   2036       1.7      gwr 	 * address.
   2037       1.7      gwr 	 */
   2038       1.7      gwr 	if (insert && managed) {
   2039       1.7      gwr 		pv = pa2pv(pa);
   2040       1.7      gwr 		nidx = pteidx(c_pte);
   2041       1.7      gwr 
   2042  1.50.2.4   bouyer 		s = splvm();
   2043       1.7      gwr 		pvebase[nidx].pve_next = pv->pv_idx;
   2044       1.7      gwr 		pv->pv_idx = nidx;
   2045       1.7      gwr 		splx(s);
   2046       1.7      gwr 	}
   2047       1.1      gwr 
   2048       1.1      gwr 	/* Move any allocated tables back into the active pool. */
   2049       1.1      gwr 
   2050       1.1      gwr 	switch (llevel) {
   2051       1.1      gwr 		case NEWA:
   2052       1.1      gwr 			TAILQ_INSERT_TAIL(&a_pool, a_tbl, at_link);
   2053       1.1      gwr 			/* FALLTHROUGH */
   2054       1.1      gwr 		case NEWB:
   2055       1.1      gwr 			TAILQ_INSERT_TAIL(&b_pool, b_tbl, bt_link);
   2056       1.1      gwr 			/* FALLTHROUGH */
   2057       1.1      gwr 		case NEWC:
   2058       1.1      gwr 			TAILQ_INSERT_TAIL(&c_pool, c_tbl, ct_link);
   2059       1.1      gwr 			/* FALLTHROUGH */
   2060       1.1      gwr 		default:
   2061       1.1      gwr 			break;
   2062       1.1      gwr 	}
   2063  1.50.2.1   bouyer 
   2064  1.50.2.1   bouyer 	return (KERN_SUCCESS);
   2065       1.1      gwr }
   2066       1.1      gwr 
   2067       1.1      gwr /* pmap_enter_kernel			INTERNAL
   2068       1.1      gwr  **
   2069       1.1      gwr  * Map the given virtual address to the given physical address within the
   2070       1.1      gwr  * kernel address space.  This function exists because the kernel map does
   2071       1.1      gwr  * not do dynamic table allocation.  It consists of a contiguous array of ptes
   2072       1.1      gwr  * and can be edited directly without the need to walk through any tables.
   2073       1.1      gwr  *
   2074       1.1      gwr  * XXX: "Danger, Will Robinson!"
   2075       1.1      gwr  * Note that the kernel should never take a fault on any page
   2076       1.1      gwr  * between [ KERNBASE .. virtual_avail ] and this is checked in
   2077       1.1      gwr  * trap.c for kernel-mode MMU faults.  This means that mappings
   2078       1.1      gwr  * created in that range must be implicily wired. -gwr
   2079       1.1      gwr  */
   2080       1.1      gwr void
   2081       1.1      gwr pmap_enter_kernel(va, pa, prot)
   2082       1.1      gwr 	vm_offset_t va;
   2083       1.1      gwr 	vm_offset_t pa;
   2084       1.1      gwr 	vm_prot_t   prot;
   2085       1.1      gwr {
   2086       1.7      gwr 	boolean_t       was_valid, insert;
   2087      1.32      gwr 	u_short         pte_idx;
   2088       1.7      gwr 	int             s, flags;
   2089       1.1      gwr 	mmu_short_pte_t *pte;
   2090       1.7      gwr 	pv_t            *pv;
   2091       1.7      gwr 	vm_offset_t     old_pa;
   2092       1.7      gwr 
   2093      1.32      gwr 	flags = (pa & ~MMU_PAGE_MASK);
   2094      1.32      gwr 	pa &= MMU_PAGE_MASK;
   2095      1.32      gwr 
   2096      1.32      gwr 	if (is_managed(pa))
   2097      1.32      gwr 		insert = TRUE;
   2098      1.32      gwr 	else
   2099      1.32      gwr 		insert = FALSE;
   2100       1.7      gwr 
   2101       1.7      gwr 	/*
   2102       1.7      gwr 	 * Calculate the index of the PTE being modified.
   2103       1.7      gwr 	 */
   2104      1.25    veego 	pte_idx = (u_long) m68k_btop(va - KERNBASE);
   2105       1.1      gwr 
   2106      1.22   jeremy 	/* This array is traditionally named "Sysmap" */
   2107       1.7      gwr 	pte = &kernCbase[pte_idx];
   2108       1.7      gwr 
   2109  1.50.2.4   bouyer 	s = splvm();
   2110       1.7      gwr 	if (MMU_VALID_DT(*pte)) {
   2111       1.1      gwr 		was_valid = TRUE;
   2112       1.7      gwr 		/*
   2113      1.32      gwr 		 * If the PTE already maps a different
   2114      1.32      gwr 		 * physical address, umap and pv_unlink.
   2115      1.24   jeremy 		 */
   2116      1.24   jeremy 		old_pa = MMU_PTE_PA(*pte);
   2117      1.32      gwr 		if (pa != old_pa)
   2118      1.32      gwr 			pmap_remove_pte(pte);
   2119      1.32      gwr 		else {
   2120      1.24   jeremy 		    /*
   2121      1.32      gwr 		     * Old PA and new PA are the same.  No need to
   2122      1.32      gwr 		     * relink the mapping within the PV list.
   2123      1.24   jeremy 		     */
   2124      1.24   jeremy 		     insert = FALSE;
   2125       1.8      gwr 
   2126       1.7      gwr 		    /*
   2127      1.24   jeremy 		     * Save any mod/ref bits on the PTE.
   2128       1.7      gwr 		     */
   2129      1.24   jeremy 		    pte->attr.raw &= (MMU_SHORT_PTE_USED|MMU_SHORT_PTE_M);
   2130       1.7      gwr 		}
   2131       1.7      gwr 	} else {
   2132       1.8      gwr 		pte->attr.raw = MMU_DT_INVALID;
   2133       1.7      gwr 		was_valid = FALSE;
   2134       1.7      gwr 	}
   2135       1.7      gwr 
   2136       1.7      gwr 	/*
   2137       1.8      gwr 	 * Map the page.  Being careful to preserve modified/referenced bits
   2138       1.8      gwr 	 * on the PTE.
   2139       1.7      gwr 	 */
   2140       1.7      gwr 	pte->attr.raw |= (pa | MMU_DT_PAGE);
   2141       1.1      gwr 
   2142       1.1      gwr 	if (!(prot & VM_PROT_WRITE)) /* If access should be read-only */
   2143       1.1      gwr 		pte->attr.raw |= MMU_SHORT_PTE_WP;
   2144       1.7      gwr 	if (flags & PMAP_NC)
   2145       1.1      gwr 		pte->attr.raw |= MMU_SHORT_PTE_CI;
   2146       1.8      gwr 	if (was_valid)
   2147       1.7      gwr 		TBIS(va);
   2148       1.1      gwr 
   2149       1.7      gwr 	/*
   2150       1.7      gwr 	 * Insert the PTE into the PV system, if need be.
   2151       1.7      gwr 	 */
   2152       1.7      gwr 	if (insert) {
   2153       1.7      gwr 		pv = pa2pv(pa);
   2154       1.7      gwr 		pvebase[pte_idx].pve_next = pv->pv_idx;
   2155       1.7      gwr 		pv->pv_idx = pte_idx;
   2156       1.7      gwr 	}
   2157       1.7      gwr 	splx(s);
   2158       1.7      gwr 
   2159      1.34      gwr }
   2160      1.34      gwr 
   2161      1.49      chs void
   2162      1.49      chs pmap_kenter_pa(va, pa, prot)
   2163      1.49      chs 	vaddr_t va;
   2164      1.49      chs 	paddr_t pa;
   2165      1.49      chs 	vm_prot_t prot;
   2166      1.49      chs {
   2167  1.50.2.1   bouyer 	pmap_enter(pmap_kernel(), va, pa, prot, PMAP_WIRED);
   2168      1.49      chs }
   2169      1.49      chs 
   2170      1.49      chs void
   2171      1.49      chs pmap_kenter_pgs(va, pgs, npgs)
   2172      1.49      chs 	vaddr_t va;
   2173      1.49      chs 	struct vm_page **pgs;
   2174      1.49      chs 	int npgs;
   2175      1.49      chs {
   2176      1.49      chs 	int i;
   2177      1.49      chs 
   2178      1.49      chs 	for (i = 0; i < npgs; i++, va += PAGE_SIZE) {
   2179      1.49      chs 		pmap_enter(pmap_kernel(), va, VM_PAGE_TO_PHYS(pgs[i]),
   2180  1.50.2.1   bouyer 				VM_PROT_READ|VM_PROT_WRITE, PMAP_WIRED);
   2181      1.49      chs 	}
   2182      1.49      chs }
   2183      1.49      chs 
   2184      1.49      chs void
   2185      1.49      chs pmap_kremove(va, len)
   2186      1.49      chs 	vaddr_t va;
   2187      1.49      chs 	vsize_t len;
   2188      1.49      chs {
   2189      1.49      chs 	for (len >>= PAGE_SHIFT; len > 0; len--, va += PAGE_SIZE) {
   2190      1.49      chs 		pmap_remove(pmap_kernel(), va, va + PAGE_SIZE);
   2191      1.49      chs 	}
   2192      1.49      chs }
   2193      1.49      chs 
   2194      1.35   jeremy /* pmap_map			INTERNAL
   2195      1.35   jeremy  **
   2196      1.35   jeremy  * Map a contiguous range of physical memory into a contiguous range of
   2197      1.35   jeremy  * the kernel virtual address space.
   2198      1.35   jeremy  *
   2199      1.35   jeremy  * Used for device mappings and early mapping of the kernel text/data/bss.
   2200      1.35   jeremy  * Returns the first virtual address beyond the end of the range.
   2201      1.34      gwr  */
   2202      1.34      gwr vm_offset_t
   2203      1.34      gwr pmap_map(va, pa, endpa, prot)
   2204      1.34      gwr 	vm_offset_t	va;
   2205      1.34      gwr 	vm_offset_t	pa;
   2206      1.34      gwr 	vm_offset_t	endpa;
   2207      1.34      gwr 	int		prot;
   2208      1.34      gwr {
   2209      1.34      gwr 	int sz;
   2210      1.34      gwr 
   2211      1.34      gwr 	sz = endpa - pa;
   2212      1.34      gwr 	do {
   2213      1.34      gwr 		pmap_enter_kernel(va, pa, prot);
   2214      1.34      gwr 		va += NBPG;
   2215      1.34      gwr 		pa += NBPG;
   2216      1.34      gwr 		sz -= NBPG;
   2217      1.34      gwr 	} while (sz > 0);
   2218      1.34      gwr 	return(va);
   2219       1.1      gwr }
   2220       1.1      gwr 
   2221       1.1      gwr /* pmap_protect			INTERFACE
   2222       1.1      gwr  **
   2223       1.7      gwr  * Apply the given protection to the given virtual address range within
   2224       1.1      gwr  * the given map.
   2225       1.1      gwr  *
   2226       1.1      gwr  * It is ok for the protection applied to be stronger than what is
   2227       1.1      gwr  * specified.  We use this to our advantage when the given map has no
   2228       1.7      gwr  * mapping for the virtual address.  By skipping a page when this
   2229       1.1      gwr  * is discovered, we are effectively applying a protection of VM_PROT_NONE,
   2230       1.1      gwr  * and therefore do not need to map the page just to apply a protection
   2231       1.1      gwr  * code.  Only pmap_enter() needs to create new mappings if they do not exist.
   2232       1.7      gwr  *
   2233       1.7      gwr  * XXX - This function could be speeded up by using pmap_stroll() for inital
   2234       1.7      gwr  *       setup, and then manual scrolling in the for() loop.
   2235       1.1      gwr  */
   2236       1.1      gwr void
   2237       1.7      gwr pmap_protect(pmap, startva, endva, prot)
   2238       1.1      gwr 	pmap_t pmap;
   2239       1.7      gwr 	vm_offset_t startva, endva;
   2240       1.1      gwr 	vm_prot_t prot;
   2241       1.1      gwr {
   2242       1.7      gwr 	boolean_t iscurpmap;
   2243       1.1      gwr 	int a_idx, b_idx, c_idx;
   2244       1.1      gwr 	a_tmgr_t *a_tbl;
   2245       1.1      gwr 	b_tmgr_t *b_tbl;
   2246       1.1      gwr 	c_tmgr_t *c_tbl;
   2247       1.1      gwr 	mmu_short_pte_t *pte;
   2248       1.1      gwr 
   2249       1.1      gwr 	if (pmap == NULL)
   2250       1.1      gwr 		return;
   2251       1.1      gwr 	if (pmap == pmap_kernel()) {
   2252       1.7      gwr 		pmap_protect_kernel(startva, endva, prot);
   2253       1.1      gwr 		return;
   2254       1.1      gwr 	}
   2255       1.1      gwr 
   2256      1.11   jeremy 	/*
   2257      1.12   jeremy 	 * In this particular pmap implementation, there are only three
   2258      1.12   jeremy 	 * types of memory protection: 'all' (read/write/execute),
   2259      1.12   jeremy 	 * 'read-only' (read/execute) and 'none' (no mapping.)
   2260      1.12   jeremy 	 * It is not possible for us to treat 'executable' as a separate
   2261      1.12   jeremy 	 * protection type.  Therefore, protection requests that seek to
   2262      1.12   jeremy 	 * remove execute permission while retaining read or write, and those
   2263      1.12   jeremy 	 * that make little sense (write-only for example) are ignored.
   2264      1.11   jeremy 	 */
   2265      1.12   jeremy 	switch (prot) {
   2266      1.12   jeremy 		case VM_PROT_NONE:
   2267      1.12   jeremy 			/*
   2268      1.12   jeremy 			 * A request to apply the protection code of
   2269      1.12   jeremy 			 * 'VM_PROT_NONE' is a synonym for pmap_remove().
   2270      1.12   jeremy 			 */
   2271      1.12   jeremy 			pmap_remove(pmap, startva, endva);
   2272      1.12   jeremy 			return;
   2273      1.12   jeremy 		case	VM_PROT_EXECUTE:
   2274      1.12   jeremy 		case	VM_PROT_READ:
   2275      1.12   jeremy 		case	VM_PROT_READ|VM_PROT_EXECUTE:
   2276      1.12   jeremy 			/* continue */
   2277      1.12   jeremy 			break;
   2278      1.12   jeremy 		case	VM_PROT_WRITE:
   2279      1.12   jeremy 		case	VM_PROT_WRITE|VM_PROT_READ:
   2280      1.12   jeremy 		case	VM_PROT_WRITE|VM_PROT_EXECUTE:
   2281      1.12   jeremy 		case	VM_PROT_ALL:
   2282      1.12   jeremy 			/* None of these should happen in a sane system. */
   2283      1.12   jeremy 			return;
   2284      1.11   jeremy 	}
   2285      1.11   jeremy 
   2286      1.11   jeremy 	/*
   2287      1.11   jeremy 	 * If the pmap has no A table, it has no mappings and therefore
   2288      1.11   jeremy 	 * there is nothing to protect.
   2289      1.11   jeremy 	 */
   2290      1.11   jeremy 	if ((a_tbl = pmap->pm_a_tmgr) == NULL)
   2291      1.11   jeremy 		return;
   2292      1.11   jeremy 
   2293      1.11   jeremy 	a_idx = MMU_TIA(startva);
   2294      1.11   jeremy 	b_idx = MMU_TIB(startva);
   2295      1.11   jeremy 	c_idx = MMU_TIC(startva);
   2296      1.11   jeremy 	b_tbl = (b_tmgr_t *) c_tbl = NULL;
   2297      1.11   jeremy 
   2298       1.7      gwr 	iscurpmap = (pmap == current_pmap());
   2299      1.11   jeremy 	while (startva < endva) {
   2300      1.11   jeremy 		if (b_tbl || MMU_VALID_DT(a_tbl->at_dtbl[a_idx])) {
   2301      1.11   jeremy 		  if (b_tbl == NULL) {
   2302      1.11   jeremy 		    b_tbl = (b_tmgr_t *) a_tbl->at_dtbl[a_idx].addr.raw;
   2303      1.11   jeremy 		    b_tbl = mmu_ptov((vm_offset_t) b_tbl);
   2304      1.11   jeremy 		    b_tbl = mmuB2tmgr((mmu_short_dte_t *) b_tbl);
   2305      1.11   jeremy 		  }
   2306      1.11   jeremy 		  if (c_tbl || MMU_VALID_DT(b_tbl->bt_dtbl[b_idx])) {
   2307      1.11   jeremy 		    if (c_tbl == NULL) {
   2308      1.11   jeremy 		      c_tbl = (c_tmgr_t *) MMU_DTE_PA(b_tbl->bt_dtbl[b_idx]);
   2309      1.11   jeremy 		      c_tbl = mmu_ptov((vm_offset_t) c_tbl);
   2310      1.11   jeremy 		      c_tbl = mmuC2tmgr((mmu_short_pte_t *) c_tbl);
   2311      1.11   jeremy 		    }
   2312      1.11   jeremy 		    if (MMU_VALID_DT(c_tbl->ct_dtbl[c_idx])) {
   2313      1.11   jeremy 		      pte = &c_tbl->ct_dtbl[c_idx];
   2314      1.12   jeremy 		      /* make the mapping read-only */
   2315      1.12   jeremy 		      pte->attr.raw |= MMU_SHORT_PTE_WP;
   2316      1.11   jeremy 		      /*
   2317      1.11   jeremy 		       * If we just modified the current address space,
   2318      1.11   jeremy 		       * flush any translations for the modified page from
   2319      1.11   jeremy 		       * the translation cache and any data from it in the
   2320      1.11   jeremy 		       * data cache.
   2321      1.11   jeremy 		       */
   2322      1.11   jeremy 		      if (iscurpmap)
   2323      1.11   jeremy 		          TBIS(startva);
   2324      1.11   jeremy 		    }
   2325      1.11   jeremy 		    startva += NBPG;
   2326       1.1      gwr 
   2327      1.11   jeremy 		    if (++c_idx >= MMU_C_TBL_SIZE) { /* exceeded C table? */
   2328      1.11   jeremy 		      c_tbl = NULL;
   2329      1.11   jeremy 		      c_idx = 0;
   2330      1.11   jeremy 		      if (++b_idx >= MMU_B_TBL_SIZE) { /* exceeded B table? */
   2331      1.11   jeremy 		        b_tbl = NULL;
   2332      1.11   jeremy 		        b_idx = 0;
   2333      1.11   jeremy 		      }
   2334      1.11   jeremy 		    }
   2335      1.11   jeremy 		  } else { /* C table wasn't valid */
   2336      1.11   jeremy 		    c_tbl = NULL;
   2337      1.11   jeremy 		    c_idx = 0;
   2338      1.11   jeremy 		    startva += MMU_TIB_RANGE;
   2339      1.11   jeremy 		    if (++b_idx >= MMU_B_TBL_SIZE) { /* exceeded B table? */
   2340      1.11   jeremy 		      b_tbl = NULL;
   2341      1.11   jeremy 		      b_idx = 0;
   2342      1.11   jeremy 		    }
   2343      1.11   jeremy 		  } /* C table */
   2344      1.11   jeremy 		} else { /* B table wasn't valid */
   2345      1.11   jeremy 		  b_tbl = NULL;
   2346      1.11   jeremy 		  b_idx = 0;
   2347      1.11   jeremy 		  startva += MMU_TIA_RANGE;
   2348      1.11   jeremy 		  a_idx++;
   2349      1.11   jeremy 		} /* B table */
   2350       1.1      gwr 	}
   2351       1.1      gwr }
   2352       1.1      gwr 
   2353       1.1      gwr /* pmap_protect_kernel			INTERNAL
   2354       1.1      gwr  **
   2355       1.7      gwr  * Apply the given protection code to a kernel address range.
   2356       1.1      gwr  */
   2357       1.1      gwr void
   2358       1.7      gwr pmap_protect_kernel(startva, endva, prot)
   2359       1.7      gwr 	vm_offset_t startva, endva;
   2360       1.1      gwr 	vm_prot_t prot;
   2361       1.1      gwr {
   2362       1.7      gwr 	vm_offset_t va;
   2363       1.1      gwr 	mmu_short_pte_t *pte;
   2364       1.1      gwr 
   2365      1.25    veego 	pte = &kernCbase[(unsigned long) m68k_btop(startva - KERNBASE)];
   2366       1.7      gwr 	for (va = startva; va < endva; va += NBPG, pte++) {
   2367       1.7      gwr 		if (MMU_VALID_DT(*pte)) {
   2368       1.7      gwr 		    switch (prot) {
   2369       1.7      gwr 		        case VM_PROT_ALL:
   2370       1.7      gwr 		            break;
   2371       1.7      gwr 		        case VM_PROT_EXECUTE:
   2372       1.7      gwr 		        case VM_PROT_READ:
   2373       1.7      gwr 		        case VM_PROT_READ|VM_PROT_EXECUTE:
   2374       1.7      gwr 		            pte->attr.raw |= MMU_SHORT_PTE_WP;
   2375       1.7      gwr 		            break;
   2376       1.7      gwr 		        case VM_PROT_NONE:
   2377       1.7      gwr 		            /* this is an alias for 'pmap_remove_kernel' */
   2378       1.7      gwr 		            pmap_remove_pte(pte);
   2379       1.7      gwr 		            break;
   2380       1.7      gwr 		        default:
   2381       1.7      gwr 		            break;
   2382       1.7      gwr 		    }
   2383       1.7      gwr 		    /*
   2384       1.7      gwr 		     * since this is the kernel, immediately flush any cached
   2385       1.7      gwr 		     * descriptors for this address.
   2386       1.7      gwr 		     */
   2387       1.7      gwr 		    TBIS(va);
   2388       1.1      gwr 		}
   2389       1.1      gwr 	}
   2390       1.1      gwr }
   2391       1.1      gwr 
   2392      1.47  thorpej /* pmap_unwire				INTERFACE
   2393       1.1      gwr  **
   2394      1.47  thorpej  * Clear the wired attribute of the specified page.
   2395       1.1      gwr  *
   2396       1.1      gwr  * This function is called from vm_fault.c to unwire
   2397      1.47  thorpej  * a mapping.
   2398       1.1      gwr  */
   2399       1.1      gwr void
   2400      1.47  thorpej pmap_unwire(pmap, va)
   2401       1.1      gwr 	pmap_t pmap;
   2402       1.1      gwr 	vm_offset_t va;
   2403       1.1      gwr {
   2404       1.1      gwr 	int a_idx, b_idx, c_idx;
   2405       1.1      gwr 	a_tmgr_t *a_tbl;
   2406       1.1      gwr 	b_tmgr_t *b_tbl;
   2407       1.1      gwr 	c_tmgr_t *c_tbl;
   2408       1.1      gwr 	mmu_short_pte_t *pte;
   2409       1.1      gwr 
   2410       1.1      gwr 	/* Kernel mappings always remain wired. */
   2411       1.1      gwr 	if (pmap == pmap_kernel())
   2412       1.1      gwr 		return;
   2413       1.1      gwr 
   2414       1.7      gwr 	/*
   2415       1.7      gwr 	 * Walk through the tables.  If the walk terminates without
   2416       1.1      gwr 	 * a valid PTE then the address wasn't wired in the first place.
   2417       1.1      gwr 	 * Return immediately.
   2418       1.1      gwr 	 */
   2419       1.1      gwr 	if (pmap_stroll(pmap, va, &a_tbl, &b_tbl, &c_tbl, &pte, &a_idx,
   2420       1.1      gwr 		&b_idx, &c_idx) == FALSE)
   2421       1.1      gwr 		return;
   2422       1.1      gwr 
   2423       1.1      gwr 
   2424       1.1      gwr 	/* Is the PTE wired?  If not, return. */
   2425       1.1      gwr 	if (!(pte->attr.raw & MMU_SHORT_PTE_WIRED))
   2426       1.1      gwr 		return;
   2427       1.1      gwr 
   2428       1.1      gwr 	/* Remove the wiring bit. */
   2429       1.1      gwr 	pte->attr.raw &= ~(MMU_SHORT_PTE_WIRED);
   2430       1.1      gwr 
   2431       1.7      gwr 	/*
   2432       1.7      gwr 	 * Decrement the wired entry count in the C table.
   2433       1.1      gwr 	 * If it reaches zero the following things happen:
   2434       1.1      gwr 	 * 1. The table no longer has any wired entries and is considered
   2435       1.1      gwr 	 *    unwired.
   2436       1.1      gwr 	 * 2. It is placed on the available queue.
   2437       1.1      gwr 	 * 3. The parent table's wired entry count is decremented.
   2438       1.1      gwr 	 * 4. If it reaches zero, this process repeats at step 1 and
   2439       1.1      gwr 	 *    stops at after reaching the A table.
   2440       1.1      gwr 	 */
   2441       1.7      gwr 	if (--c_tbl->ct_wcnt == 0) {
   2442       1.1      gwr 		TAILQ_INSERT_TAIL(&c_pool, c_tbl, ct_link);
   2443       1.7      gwr 		if (--b_tbl->bt_wcnt == 0) {
   2444       1.1      gwr 			TAILQ_INSERT_TAIL(&b_pool, b_tbl, bt_link);
   2445       1.7      gwr 			if (--a_tbl->at_wcnt == 0) {
   2446       1.1      gwr 				TAILQ_INSERT_TAIL(&a_pool, a_tbl, at_link);
   2447       1.1      gwr 			}
   2448       1.1      gwr 		}
   2449       1.1      gwr 	}
   2450       1.1      gwr }
   2451       1.1      gwr 
   2452       1.1      gwr /* pmap_copy				INTERFACE
   2453       1.1      gwr  **
   2454       1.1      gwr  * Copy the mappings of a range of addresses in one pmap, into
   2455       1.1      gwr  * the destination address of another.
   2456       1.1      gwr  *
   2457       1.1      gwr  * This routine is advisory.  Should we one day decide that MMU tables
   2458       1.1      gwr  * may be shared by more than one pmap, this function should be used to
   2459       1.1      gwr  * link them together.  Until that day however, we do nothing.
   2460       1.1      gwr  */
   2461       1.1      gwr void
   2462       1.1      gwr pmap_copy(pmap_a, pmap_b, dst, len, src)
   2463       1.1      gwr 	pmap_t pmap_a, pmap_b;
   2464       1.1      gwr 	vm_offset_t dst;
   2465       1.1      gwr 	vm_size_t   len;
   2466       1.1      gwr 	vm_offset_t src;
   2467       1.1      gwr {
   2468       1.1      gwr 	/* not implemented. */
   2469       1.1      gwr }
   2470       1.1      gwr 
   2471       1.1      gwr /* pmap_copy_page			INTERFACE
   2472       1.1      gwr  **
   2473       1.1      gwr  * Copy the contents of one physical page into another.
   2474       1.1      gwr  *
   2475       1.7      gwr  * This function makes use of two virtual pages allocated in pmap_bootstrap()
   2476      1.24   jeremy  * to map the two specified physical pages into the kernel address space.
   2477       1.7      gwr  *
   2478       1.7      gwr  * Note: We could use the transparent translation registers to make the
   2479       1.7      gwr  * mappings.  If we do so, be sure to disable interrupts before using them.
   2480       1.1      gwr  */
   2481       1.1      gwr void
   2482      1.24   jeremy pmap_copy_page(srcpa, dstpa)
   2483      1.24   jeremy 	vm_offset_t srcpa, dstpa;
   2484       1.1      gwr {
   2485      1.24   jeremy 	vm_offset_t srcva, dstva;
   2486      1.23   jeremy 	int s;
   2487      1.24   jeremy 
   2488      1.24   jeremy 	srcva = tmp_vpages[0];
   2489      1.24   jeremy 	dstva = tmp_vpages[1];
   2490       1.1      gwr 
   2491  1.50.2.4   bouyer 	s = splvm();
   2492      1.24   jeremy 	if (tmp_vpages_inuse++)
   2493      1.24   jeremy 		panic("pmap_copy_page: temporary vpages are in use.");
   2494      1.23   jeremy 
   2495      1.23   jeremy 	/* Map pages as non-cacheable to avoid cache polution? */
   2496      1.24   jeremy 	pmap_enter_kernel(srcva, srcpa, VM_PROT_READ);
   2497      1.24   jeremy 	pmap_enter_kernel(dstva, dstpa, VM_PROT_READ|VM_PROT_WRITE);
   2498       1.7      gwr 
   2499      1.24   jeremy 	/* Hand-optimized version of bcopy(src, dst, NBPG) */
   2500      1.24   jeremy 	copypage((char *) srcva, (char *) dstva);
   2501      1.24   jeremy 
   2502      1.24   jeremy 	pmap_remove_kernel(srcva, srcva + NBPG);
   2503      1.24   jeremy 	pmap_remove_kernel(dstva, dstva + NBPG);
   2504      1.24   jeremy 
   2505      1.24   jeremy 	--tmp_vpages_inuse;
   2506      1.23   jeremy 	splx(s);
   2507       1.1      gwr }
   2508       1.1      gwr 
   2509       1.1      gwr /* pmap_zero_page			INTERFACE
   2510       1.1      gwr  **
   2511       1.1      gwr  * Zero the contents of the specified physical page.
   2512       1.1      gwr  *
   2513       1.7      gwr  * Uses one of the virtual pages allocated in pmap_boostrap()
   2514      1.24   jeremy  * to map the specified page into the kernel address space.
   2515       1.1      gwr  */
   2516       1.1      gwr void
   2517      1.24   jeremy pmap_zero_page(dstpa)
   2518      1.24   jeremy 	vm_offset_t dstpa;
   2519       1.1      gwr {
   2520      1.24   jeremy 	vm_offset_t dstva;
   2521      1.23   jeremy 	int s;
   2522      1.23   jeremy 
   2523      1.24   jeremy 	dstva = tmp_vpages[1];
   2524  1.50.2.4   bouyer 	s = splvm();
   2525      1.26   jeremy 	if (tmp_vpages_inuse++)
   2526      1.24   jeremy 		panic("pmap_zero_page: temporary vpages are in use.");
   2527      1.24   jeremy 
   2528      1.24   jeremy 	/* The comments in pmap_copy_page() above apply here also. */
   2529      1.24   jeremy 	pmap_enter_kernel(dstva, dstpa, VM_PROT_READ|VM_PROT_WRITE);
   2530      1.24   jeremy 
   2531      1.24   jeremy 	/* Hand-optimized version of bzero(ptr, NBPG) */
   2532      1.24   jeremy 	zeropage((char *) dstva);
   2533       1.1      gwr 
   2534      1.24   jeremy 	pmap_remove_kernel(dstva, dstva + NBPG);
   2535       1.1      gwr 
   2536      1.24   jeremy 	--tmp_vpages_inuse;
   2537      1.23   jeremy 	splx(s);
   2538       1.1      gwr }
   2539       1.1      gwr 
   2540       1.1      gwr /* pmap_collect			INTERFACE
   2541       1.1      gwr  **
   2542       1.7      gwr  * Called from the VM system when we are about to swap out
   2543       1.7      gwr  * the process using this pmap.  This should give up any
   2544       1.7      gwr  * resources held here, including all its MMU tables.
   2545       1.1      gwr  */
   2546       1.1      gwr void
   2547       1.1      gwr pmap_collect(pmap)
   2548       1.1      gwr 	pmap_t pmap;
   2549       1.1      gwr {
   2550       1.7      gwr 	/* XXX - todo... */
   2551       1.1      gwr }
   2552       1.1      gwr 
   2553       1.1      gwr /* pmap_create			INTERFACE
   2554       1.1      gwr  **
   2555       1.1      gwr  * Create and return a pmap structure.
   2556       1.1      gwr  */
   2557       1.1      gwr pmap_t
   2558      1.49      chs pmap_create()
   2559       1.1      gwr {
   2560       1.1      gwr 	pmap_t	pmap;
   2561       1.1      gwr 
   2562  1.50.2.2   bouyer 	pmap = pool_get(&pmap_pmap_pool, PR_WAITOK);
   2563       1.1      gwr 	pmap_pinit(pmap);
   2564       1.1      gwr 	return pmap;
   2565       1.1      gwr }
   2566       1.1      gwr 
   2567       1.1      gwr /* pmap_pinit			INTERNAL
   2568       1.1      gwr  **
   2569       1.1      gwr  * Initialize a pmap structure.
   2570       1.1      gwr  */
   2571       1.1      gwr void
   2572       1.1      gwr pmap_pinit(pmap)
   2573       1.1      gwr 	pmap_t pmap;
   2574       1.1      gwr {
   2575       1.1      gwr 	bzero(pmap, sizeof(struct pmap));
   2576       1.7      gwr 	pmap->pm_a_tmgr = NULL;
   2577       1.7      gwr 	pmap->pm_a_phys = kernAphys;
   2578  1.50.2.1   bouyer 	pmap->pm_refcount = 1;
   2579  1.50.2.1   bouyer 	simple_lock_init(&pmap->pm_lock);
   2580       1.1      gwr }
   2581       1.1      gwr 
   2582       1.1      gwr /* pmap_release				INTERFACE
   2583       1.1      gwr  **
   2584       1.1      gwr  * Release any resources held by the given pmap.
   2585       1.1      gwr  *
   2586       1.1      gwr  * This is the reverse analog to pmap_pinit.  It does not
   2587       1.1      gwr  * necessarily mean for the pmap structure to be deallocated,
   2588       1.1      gwr  * as in pmap_destroy.
   2589       1.1      gwr  */
   2590       1.1      gwr void
   2591       1.1      gwr pmap_release(pmap)
   2592       1.1      gwr 	pmap_t pmap;
   2593       1.1      gwr {
   2594       1.7      gwr 	/*
   2595       1.7      gwr 	 * As long as the pmap contains no mappings,
   2596       1.1      gwr 	 * which always should be the case whenever
   2597       1.1      gwr 	 * this function is called, there really should
   2598       1.1      gwr 	 * be nothing to do.
   2599       1.1      gwr 	 */
   2600       1.1      gwr #ifdef	PMAP_DEBUG
   2601       1.1      gwr 	if (pmap == NULL)
   2602       1.1      gwr 		return;
   2603       1.1      gwr 	if (pmap == pmap_kernel())
   2604       1.9      gwr 		panic("pmap_release: kernel pmap");
   2605       1.1      gwr #endif
   2606       1.9      gwr 	/*
   2607       1.9      gwr 	 * XXX - If this pmap has an A table, give it back.
   2608       1.9      gwr 	 * The pmap SHOULD be empty by now, and pmap_remove
   2609       1.9      gwr 	 * should have already given back the A table...
   2610       1.9      gwr 	 * However, I see:  pmap->pm_a_tmgr->at_ecnt == 1
   2611       1.9      gwr 	 * at this point, which means some mapping was not
   2612       1.9      gwr 	 * removed when it should have been. -gwr
   2613       1.9      gwr 	 */
   2614       1.7      gwr 	if (pmap->pm_a_tmgr != NULL) {
   2615       1.9      gwr 		/* First make sure we are not using it! */
   2616       1.9      gwr 		if (kernel_crp.rp_addr == pmap->pm_a_phys) {
   2617       1.9      gwr 			kernel_crp.rp_addr = kernAphys;
   2618       1.9      gwr 			loadcrp(&kernel_crp);
   2619       1.9      gwr 		}
   2620      1.13      gwr #ifdef	PMAP_DEBUG /* XXX - todo! */
   2621      1.13      gwr 		/* XXX - Now complain... */
   2622      1.13      gwr 		printf("pmap_release: still have table\n");
   2623      1.13      gwr 		Debugger();
   2624      1.13      gwr #endif
   2625       1.7      gwr 		free_a_table(pmap->pm_a_tmgr, TRUE);
   2626       1.7      gwr 		pmap->pm_a_tmgr = NULL;
   2627       1.7      gwr 		pmap->pm_a_phys = kernAphys;
   2628       1.7      gwr 	}
   2629       1.1      gwr }
   2630       1.1      gwr 
   2631       1.1      gwr /* pmap_reference			INTERFACE
   2632       1.1      gwr  **
   2633       1.1      gwr  * Increment the reference count of a pmap.
   2634       1.1      gwr  */
   2635       1.1      gwr void
   2636       1.1      gwr pmap_reference(pmap)
   2637       1.1      gwr 	pmap_t pmap;
   2638       1.1      gwr {
   2639       1.1      gwr 	if (pmap == NULL)
   2640       1.1      gwr 		return;
   2641       1.1      gwr 
   2642  1.50.2.1   bouyer 	pmap_lock(pmap);
   2643  1.50.2.1   bouyer 	pmap_add_ref(pmap);
   2644  1.50.2.1   bouyer 	pmap_unlock(pmap);
   2645       1.1      gwr }
   2646       1.1      gwr 
   2647       1.1      gwr /* pmap_dereference			INTERNAL
   2648       1.1      gwr  **
   2649       1.1      gwr  * Decrease the reference count on the given pmap
   2650       1.1      gwr  * by one and return the current count.
   2651       1.1      gwr  */
   2652       1.1      gwr int
   2653       1.1      gwr pmap_dereference(pmap)
   2654       1.1      gwr 	pmap_t pmap;
   2655       1.1      gwr {
   2656       1.1      gwr 	int rtn;
   2657       1.1      gwr 
   2658       1.1      gwr 	if (pmap == NULL)
   2659       1.1      gwr 		return 0;
   2660       1.1      gwr 
   2661  1.50.2.1   bouyer 	pmap_lock(pmap);
   2662  1.50.2.1   bouyer 	rtn = pmap_del_ref(pmap);
   2663  1.50.2.1   bouyer 	pmap_unlock(pmap);
   2664       1.1      gwr 
   2665       1.1      gwr 	return rtn;
   2666       1.1      gwr }
   2667       1.1      gwr 
   2668       1.1      gwr /* pmap_destroy			INTERFACE
   2669       1.1      gwr  **
   2670       1.1      gwr  * Decrement a pmap's reference count and delete
   2671       1.1      gwr  * the pmap if it becomes zero.  Will be called
   2672       1.1      gwr  * only after all mappings have been removed.
   2673       1.1      gwr  */
   2674       1.1      gwr void
   2675       1.1      gwr pmap_destroy(pmap)
   2676       1.1      gwr 	pmap_t pmap;
   2677       1.1      gwr {
   2678       1.1      gwr 	if (pmap == NULL)
   2679       1.1      gwr 		return;
   2680       1.1      gwr 	if (pmap == &kernel_pmap)
   2681       1.1      gwr 		panic("pmap_destroy: kernel_pmap!");
   2682       1.1      gwr 	if (pmap_dereference(pmap) == 0) {
   2683       1.1      gwr 		pmap_release(pmap);
   2684  1.50.2.2   bouyer 		pool_put(&pmap_pmap_pool, pmap);
   2685       1.1      gwr 	}
   2686       1.1      gwr }
   2687       1.1      gwr 
   2688       1.1      gwr /* pmap_is_referenced			INTERFACE
   2689       1.1      gwr  **
   2690       1.1      gwr  * Determine if the given physical page has been
   2691       1.1      gwr  * referenced (read from [or written to.])
   2692       1.1      gwr  */
   2693       1.1      gwr boolean_t
   2694      1.49      chs pmap_is_referenced(pg)
   2695      1.49      chs 	struct vm_page *pg;
   2696       1.1      gwr {
   2697      1.49      chs 	paddr_t   pa = VM_PAGE_TO_PHYS(pg);
   2698       1.1      gwr 	pv_t      *pv;
   2699       1.7      gwr 	int       idx, s;
   2700       1.1      gwr 
   2701       1.1      gwr 	if (!pv_initialized)
   2702       1.1      gwr 		return FALSE;
   2703       1.7      gwr 	/* XXX - this may be unecessary. */
   2704       1.1      gwr 	if (!is_managed(pa))
   2705       1.1      gwr 		return FALSE;
   2706       1.1      gwr 
   2707       1.1      gwr 	pv = pa2pv(pa);
   2708       1.7      gwr 	/*
   2709       1.7      gwr 	 * Check the flags on the pv head.  If they are set,
   2710       1.1      gwr 	 * return immediately.  Otherwise a search must be done.
   2711       1.7      gwr 	 */
   2712       1.1      gwr 	if (pv->pv_flags & PV_FLAGS_USED)
   2713       1.1      gwr 		return TRUE;
   2714      1.32      gwr 
   2715  1.50.2.4   bouyer 	s = splvm();
   2716      1.32      gwr 	/*
   2717      1.32      gwr 	 * Search through all pv elements pointing
   2718      1.32      gwr 	 * to this page and query their reference bits
   2719      1.32      gwr 	 */
   2720      1.32      gwr 	for (idx = pv->pv_idx;
   2721      1.32      gwr 		 idx != PVE_EOL;
   2722      1.32      gwr 		 idx = pvebase[idx].pve_next) {
   2723      1.32      gwr 
   2724      1.32      gwr 		if (MMU_PTE_USED(kernCbase[idx])) {
   2725      1.32      gwr 			splx(s);
   2726      1.32      gwr 			return TRUE;
   2727      1.32      gwr 		}
   2728       1.7      gwr 	}
   2729      1.32      gwr 	splx(s);
   2730       1.1      gwr 
   2731       1.1      gwr 	return FALSE;
   2732       1.1      gwr }
   2733       1.1      gwr 
   2734       1.1      gwr /* pmap_is_modified			INTERFACE
   2735       1.1      gwr  **
   2736       1.1      gwr  * Determine if the given physical page has been
   2737       1.1      gwr  * modified (written to.)
   2738       1.1      gwr  */
   2739       1.1      gwr boolean_t
   2740      1.49      chs pmap_is_modified(pg)
   2741      1.49      chs 	struct vm_page *pg;
   2742       1.1      gwr {
   2743      1.49      chs 	paddr_t   pa = VM_PAGE_TO_PHYS(pg);
   2744       1.1      gwr 	pv_t      *pv;
   2745       1.7      gwr 	int       idx, s;
   2746       1.1      gwr 
   2747       1.1      gwr 	if (!pv_initialized)
   2748       1.1      gwr 		return FALSE;
   2749       1.7      gwr 	/* XXX - this may be unecessary. */
   2750       1.1      gwr 	if (!is_managed(pa))
   2751       1.1      gwr 		return FALSE;
   2752       1.1      gwr 
   2753       1.1      gwr 	/* see comments in pmap_is_referenced() */
   2754       1.1      gwr 	pv = pa2pv(pa);
   2755      1.32      gwr 	if (pv->pv_flags & PV_FLAGS_MDFY)
   2756       1.1      gwr 		return TRUE;
   2757      1.32      gwr 
   2758  1.50.2.4   bouyer 	s = splvm();
   2759      1.32      gwr 	for (idx = pv->pv_idx;
   2760      1.32      gwr 		 idx != PVE_EOL;
   2761      1.32      gwr 		 idx = pvebase[idx].pve_next) {
   2762      1.32      gwr 
   2763      1.32      gwr 		if (MMU_PTE_MODIFIED(kernCbase[idx])) {
   2764      1.32      gwr 			splx(s);
   2765      1.32      gwr 			return TRUE;
   2766      1.32      gwr 		}
   2767       1.7      gwr 	}
   2768      1.32      gwr 	splx(s);
   2769       1.7      gwr 
   2770       1.1      gwr 	return FALSE;
   2771       1.1      gwr }
   2772       1.1      gwr 
   2773       1.1      gwr /* pmap_page_protect			INTERFACE
   2774       1.1      gwr  **
   2775       1.1      gwr  * Applies the given protection to all mappings to the given
   2776       1.1      gwr  * physical page.
   2777       1.1      gwr  */
   2778       1.1      gwr void
   2779      1.49      chs pmap_page_protect(pg, prot)
   2780      1.49      chs 	struct vm_page *pg;
   2781       1.1      gwr 	vm_prot_t prot;
   2782       1.1      gwr {
   2783      1.49      chs 	paddr_t   pa = VM_PAGE_TO_PHYS(pg);
   2784       1.1      gwr 	pv_t      *pv;
   2785       1.7      gwr 	int       idx, s;
   2786       1.8      gwr 	vm_offset_t va;
   2787       1.1      gwr 	struct mmu_short_pte_struct *pte;
   2788       1.8      gwr 	c_tmgr_t  *c_tbl;
   2789       1.8      gwr 	pmap_t    pmap, curpmap;
   2790       1.1      gwr 
   2791       1.1      gwr 	if (!is_managed(pa))
   2792       1.1      gwr 		return;
   2793       1.1      gwr 
   2794       1.8      gwr 	curpmap = current_pmap();
   2795       1.1      gwr 	pv = pa2pv(pa);
   2796  1.50.2.4   bouyer 	s = splvm();
   2797      1.32      gwr 
   2798      1.32      gwr 	for (idx = pv->pv_idx;
   2799      1.32      gwr 		 idx != PVE_EOL;
   2800      1.32      gwr 		 idx = pvebase[idx].pve_next) {
   2801      1.32      gwr 
   2802       1.7      gwr 		pte = &kernCbase[idx];
   2803       1.1      gwr 		switch (prot) {
   2804       1.1      gwr 			case VM_PROT_ALL:
   2805       1.1      gwr 				/* do nothing */
   2806       1.1      gwr 				break;
   2807       1.7      gwr 			case VM_PROT_EXECUTE:
   2808       1.1      gwr 			case VM_PROT_READ:
   2809       1.1      gwr 			case VM_PROT_READ|VM_PROT_EXECUTE:
   2810       1.8      gwr 				/*
   2811       1.8      gwr 				 * Determine the virtual address mapped by
   2812       1.8      gwr 				 * the PTE and flush ATC entries if necessary.
   2813       1.8      gwr 				 */
   2814       1.8      gwr 				va = pmap_get_pteinfo(idx, &pmap, &c_tbl);
   2815      1.40      gwr 				/* XXX don't write protect pager mappings */
   2816      1.40      gwr 				if (va >= PAGER_SVA && va < PAGER_EVA) {
   2817      1.40      gwr #ifdef	PMAP_DEBUG
   2818      1.40      gwr 					/* XXX - Does this actually happen? */
   2819      1.40      gwr 					printf("pmap_page_protect: in pager!\n");
   2820      1.40      gwr 					Debugger();
   2821      1.40      gwr #endif
   2822      1.40      gwr 				} else
   2823      1.40      gwr 					pte->attr.raw |= MMU_SHORT_PTE_WP;
   2824       1.8      gwr 				if (pmap == curpmap || pmap == pmap_kernel())
   2825       1.8      gwr 					TBIS(va);
   2826       1.1      gwr 				break;
   2827       1.1      gwr 			case VM_PROT_NONE:
   2828       1.7      gwr 				/* Save the mod/ref bits. */
   2829       1.7      gwr 				pv->pv_flags |= pte->attr.raw;
   2830       1.7      gwr 				/* Invalidate the PTE. */
   2831       1.7      gwr 				pte->attr.raw = MMU_DT_INVALID;
   2832       1.8      gwr 
   2833       1.8      gwr 				/*
   2834       1.8      gwr 				 * Update table counts.  And flush ATC entries
   2835       1.8      gwr 				 * if necessary.
   2836       1.8      gwr 				 */
   2837       1.8      gwr 				va = pmap_get_pteinfo(idx, &pmap, &c_tbl);
   2838       1.8      gwr 
   2839       1.8      gwr 				/*
   2840       1.8      gwr 				 * If the PTE belongs to the kernel map,
   2841       1.8      gwr 				 * be sure to flush the page it maps.
   2842       1.8      gwr 				 */
   2843       1.8      gwr 				if (pmap == pmap_kernel()) {
   2844       1.8      gwr 					TBIS(va);
   2845       1.8      gwr 				} else {
   2846       1.8      gwr 					/*
   2847       1.8      gwr 					 * The PTE belongs to a user map.
   2848       1.8      gwr 					 * update the entry count in the C
   2849       1.8      gwr 					 * table to which it belongs and flush
   2850       1.8      gwr 					 * the ATC if the mapping belongs to
   2851       1.8      gwr 					 * the current pmap.
   2852       1.8      gwr 					 */
   2853       1.8      gwr 					c_tbl->ct_ecnt--;
   2854       1.8      gwr 					if (pmap == curpmap)
   2855       1.8      gwr 						TBIS(va);
   2856       1.8      gwr 				}
   2857       1.1      gwr 				break;
   2858       1.1      gwr 			default:
   2859       1.1      gwr 				break;
   2860       1.1      gwr 		}
   2861       1.1      gwr 	}
   2862       1.8      gwr 
   2863       1.8      gwr 	/*
   2864       1.8      gwr 	 * If the protection code indicates that all mappings to the page
   2865       1.8      gwr 	 * be removed, truncate the PV list to zero entries.
   2866       1.8      gwr 	 */
   2867       1.7      gwr 	if (prot == VM_PROT_NONE)
   2868       1.7      gwr 		pv->pv_idx = PVE_EOL;
   2869       1.7      gwr 	splx(s);
   2870       1.1      gwr }
   2871       1.1      gwr 
   2872       1.7      gwr /* pmap_get_pteinfo		INTERNAL
   2873       1.1      gwr  **
   2874       1.7      gwr  * Called internally to find the pmap and virtual address within that
   2875       1.8      gwr  * map to which the pte at the given index maps.  Also includes the PTE's C
   2876       1.8      gwr  * table manager.
   2877       1.1      gwr  *
   2878       1.7      gwr  * Returns the pmap in the argument provided, and the virtual address
   2879       1.7      gwr  * by return value.
   2880       1.1      gwr  */
   2881       1.1      gwr vm_offset_t
   2882       1.8      gwr pmap_get_pteinfo(idx, pmap, tbl)
   2883       1.8      gwr 	u_int idx;
   2884       1.7      gwr 	pmap_t *pmap;
   2885       1.7      gwr 	c_tmgr_t **tbl;
   2886       1.1      gwr {
   2887       1.1      gwr 	vm_offset_t     va = 0;
   2888       1.1      gwr 
   2889       1.7      gwr 	/*
   2890       1.7      gwr 	 * Determine if the PTE is a kernel PTE or a user PTE.
   2891       1.1      gwr 	 */
   2892       1.8      gwr 	if (idx >= NUM_KERN_PTES) {
   2893       1.7      gwr 		/*
   2894       1.7      gwr 		 * The PTE belongs to a user mapping.
   2895       1.7      gwr 		 */
   2896       1.8      gwr 		/* XXX: Would like an inline for this to validate idx... */
   2897      1.26   jeremy 		*tbl = &Ctmgrbase[(idx - NUM_KERN_PTES) / MMU_C_TBL_SIZE];
   2898      1.26   jeremy 
   2899      1.26   jeremy 		*pmap = (*tbl)->ct_pmap;
   2900      1.26   jeremy 		/*
   2901      1.26   jeremy 		 * To find the va to which the PTE maps, we first take
   2902      1.26   jeremy 		 * the table's base virtual address mapping which is stored
   2903      1.26   jeremy 		 * in ct_va.  We then increment this address by a page for
   2904      1.26   jeremy 		 * every slot skipped until we reach the PTE.
   2905      1.26   jeremy 		 */
   2906      1.26   jeremy 		va =    (*tbl)->ct_va;
   2907      1.26   jeremy 		va += m68k_ptob(idx % MMU_C_TBL_SIZE);
   2908       1.7      gwr 	} else {
   2909       1.7      gwr 		/*
   2910       1.7      gwr 		 * The PTE belongs to the kernel map.
   2911       1.7      gwr 		 */
   2912       1.8      gwr 		*pmap = pmap_kernel();
   2913       1.8      gwr 
   2914      1.25    veego 		va = m68k_ptob(idx);
   2915       1.7      gwr 		va += KERNBASE;
   2916       1.7      gwr 	}
   2917       1.7      gwr 
   2918       1.1      gwr 	return va;
   2919       1.1      gwr }
   2920       1.1      gwr 
   2921       1.1      gwr /* pmap_clear_modify			INTERFACE
   2922       1.1      gwr  **
   2923       1.1      gwr  * Clear the modification bit on the page at the specified
   2924       1.1      gwr  * physical address.
   2925       1.1      gwr  *
   2926       1.1      gwr  */
   2927      1.49      chs boolean_t
   2928      1.49      chs pmap_clear_modify(pg)
   2929      1.49      chs 	struct vm_page *pg;
   2930       1.1      gwr {
   2931      1.49      chs 	paddr_t pa = VM_PAGE_TO_PHYS(pg);
   2932      1.49      chs 	boolean_t rv;
   2933      1.49      chs 
   2934      1.19   jeremy 	if (!is_managed(pa))
   2935      1.49      chs 		return FALSE;
   2936      1.49      chs 	rv = pmap_is_modified(pg);
   2937       1.1      gwr 	pmap_clear_pv(pa, PV_FLAGS_MDFY);
   2938      1.49      chs 	return rv;
   2939       1.1      gwr }
   2940       1.1      gwr 
   2941       1.1      gwr /* pmap_clear_reference			INTERFACE
   2942       1.1      gwr  **
   2943       1.1      gwr  * Clear the referenced bit on the page at the specified
   2944       1.1      gwr  * physical address.
   2945       1.1      gwr  */
   2946      1.49      chs boolean_t
   2947      1.49      chs pmap_clear_reference(pg)
   2948      1.49      chs 	struct vm_page *pg;
   2949       1.1      gwr {
   2950      1.49      chs 	paddr_t pa = VM_PAGE_TO_PHYS(pg);
   2951      1.49      chs 	boolean_t rv;
   2952      1.49      chs 
   2953      1.19   jeremy 	if (!is_managed(pa))
   2954      1.50      chs 		return FALSE;
   2955      1.49      chs 	rv = pmap_is_referenced(pg);
   2956       1.1      gwr 	pmap_clear_pv(pa, PV_FLAGS_USED);
   2957      1.49      chs 	return rv;
   2958       1.1      gwr }
   2959       1.1      gwr 
   2960       1.1      gwr /* pmap_clear_pv			INTERNAL
   2961       1.1      gwr  **
   2962       1.1      gwr  * Clears the specified flag from the specified physical address.
   2963       1.1      gwr  * (Used by pmap_clear_modify() and pmap_clear_reference().)
   2964       1.1      gwr  *
   2965       1.1      gwr  * Flag is one of:
   2966       1.1      gwr  *   PV_FLAGS_MDFY - Page modified bit.
   2967       1.1      gwr  *   PV_FLAGS_USED - Page used (referenced) bit.
   2968       1.1      gwr  *
   2969       1.1      gwr  * This routine must not only clear the flag on the pv list
   2970       1.1      gwr  * head.  It must also clear the bit on every pte in the pv
   2971       1.1      gwr  * list associated with the address.
   2972       1.1      gwr  */
   2973       1.1      gwr void
   2974       1.1      gwr pmap_clear_pv(pa, flag)
   2975       1.1      gwr 	vm_offset_t pa;
   2976       1.1      gwr 	int flag;
   2977       1.1      gwr {
   2978       1.1      gwr 	pv_t      *pv;
   2979       1.7      gwr 	int       idx, s;
   2980       1.7      gwr 	vm_offset_t     va;
   2981       1.7      gwr 	pmap_t          pmap;
   2982       1.1      gwr 	mmu_short_pte_t *pte;
   2983       1.7      gwr 	c_tmgr_t        *c_tbl;
   2984       1.1      gwr 
   2985       1.1      gwr 	pv = pa2pv(pa);
   2986       1.7      gwr 
   2987  1.50.2.4   bouyer 	s = splvm();
   2988       1.1      gwr 	pv->pv_flags &= ~(flag);
   2989      1.32      gwr 
   2990      1.32      gwr 	for (idx = pv->pv_idx;
   2991      1.32      gwr 		 idx != PVE_EOL;
   2992      1.32      gwr 		 idx = pvebase[idx].pve_next) {
   2993      1.32      gwr 
   2994       1.7      gwr 		pte = &kernCbase[idx];
   2995       1.1      gwr 		pte->attr.raw &= ~(flag);
   2996       1.7      gwr 		/*
   2997       1.7      gwr 		 * The MC68030 MMU will not set the modified or
   2998       1.7      gwr 		 * referenced bits on any MMU tables for which it has
   2999       1.7      gwr 		 * a cached descriptor with its modify bit set.  To insure
   3000       1.7      gwr 		 * that it will modify these bits on the PTE during the next
   3001       1.7      gwr 		 * time it is written to or read from, we must flush it from
   3002       1.7      gwr 		 * the ATC.
   3003       1.7      gwr 		 *
   3004       1.7      gwr 		 * Ordinarily it is only necessary to flush the descriptor
   3005       1.7      gwr 		 * if it is used in the current address space.  But since I
   3006       1.7      gwr 		 * am not sure that there will always be a notion of
   3007       1.7      gwr 		 * 'the current address space' when this function is called,
   3008       1.7      gwr 		 * I will skip the test and always flush the address.  It
   3009       1.7      gwr 		 * does no harm.
   3010       1.7      gwr 		 */
   3011       1.8      gwr 		va = pmap_get_pteinfo(idx, &pmap, &c_tbl);
   3012       1.7      gwr 		TBIS(va);
   3013       1.1      gwr 	}
   3014       1.7      gwr 	splx(s);
   3015       1.1      gwr }
   3016       1.1      gwr 
   3017       1.1      gwr /* pmap_extract			INTERFACE
   3018       1.1      gwr  **
   3019       1.1      gwr  * Return the physical address mapped by the virtual address
   3020      1.48  thorpej  * in the specified pmap.
   3021       1.1      gwr  *
   3022       1.1      gwr  * Note: this function should also apply an exclusive lock
   3023       1.1      gwr  * on the pmap system during its duration.
   3024       1.1      gwr  */
   3025      1.48  thorpej boolean_t
   3026      1.48  thorpej pmap_extract(pmap, va, pap)
   3027      1.48  thorpej 	pmap_t pmap;
   3028      1.48  thorpej 	vaddr_t va;
   3029      1.48  thorpej 	paddr_t *pap;
   3030       1.1      gwr {
   3031       1.1      gwr 	int a_idx, b_idx, pte_idx;
   3032       1.1      gwr 	a_tmgr_t	*a_tbl;
   3033       1.1      gwr 	b_tmgr_t	*b_tbl;
   3034       1.1      gwr 	c_tmgr_t	*c_tbl;
   3035       1.1      gwr 	mmu_short_pte_t	*c_pte;
   3036       1.1      gwr 
   3037       1.1      gwr 	if (pmap == pmap_kernel())
   3038      1.48  thorpej 		return pmap_extract_kernel(va, pap);
   3039       1.1      gwr 	if (pmap == NULL)
   3040      1.48  thorpej 		return FALSE;
   3041       1.1      gwr 
   3042       1.1      gwr 	if (pmap_stroll(pmap, va, &a_tbl, &b_tbl, &c_tbl,
   3043       1.7      gwr 		&c_pte, &a_idx, &b_idx, &pte_idx) == FALSE)
   3044      1.48  thorpej 		return FALSE;
   3045       1.1      gwr 
   3046       1.7      gwr 	if (!MMU_VALID_DT(*c_pte))
   3047      1.48  thorpej 		return FALSE;
   3048       1.7      gwr 
   3049      1.48  thorpej 	if (pap != NULL)
   3050      1.48  thorpej 		*pap = MMU_PTE_PA(*c_pte);
   3051      1.48  thorpej 	return (TRUE);
   3052       1.1      gwr }
   3053       1.1      gwr 
   3054       1.1      gwr /* pmap_extract_kernel		INTERNAL
   3055       1.1      gwr  **
   3056       1.8      gwr  * Extract a translation from the kernel address space.
   3057       1.1      gwr  */
   3058      1.48  thorpej boolean_t
   3059      1.48  thorpej pmap_extract_kernel(va, pap)
   3060      1.48  thorpej 	vaddr_t va;
   3061      1.48  thorpej 	paddr_t *pap;
   3062       1.1      gwr {
   3063       1.1      gwr 	mmu_short_pte_t *pte;
   3064       1.1      gwr 
   3065      1.25    veego 	pte = &kernCbase[(u_int) m68k_btop(va - KERNBASE)];
   3066      1.48  thorpej 	if (!MMU_VALID_DT(*pte))
   3067      1.48  thorpej 		return (FALSE);
   3068      1.48  thorpej 	if (pap != NULL)
   3069      1.48  thorpej 		*pap = MMU_PTE_PA(*pte);
   3070      1.48  thorpej 	return (TRUE);
   3071       1.1      gwr }
   3072       1.1      gwr 
   3073       1.1      gwr /* pmap_remove_kernel		INTERNAL
   3074       1.1      gwr  **
   3075       1.1      gwr  * Remove the mapping of a range of virtual addresses from the kernel map.
   3076       1.9      gwr  * The arguments are already page-aligned.
   3077       1.1      gwr  */
   3078       1.1      gwr void
   3079       1.9      gwr pmap_remove_kernel(sva, eva)
   3080       1.9      gwr 	vm_offset_t sva;
   3081       1.9      gwr 	vm_offset_t eva;
   3082       1.1      gwr {
   3083       1.9      gwr 	int idx, eidx;
   3084       1.9      gwr 
   3085       1.9      gwr #ifdef	PMAP_DEBUG
   3086       1.9      gwr 	if ((sva & PGOFSET) || (eva & PGOFSET))
   3087       1.9      gwr 		panic("pmap_remove_kernel: alignment");
   3088       1.9      gwr #endif
   3089       1.1      gwr 
   3090      1.25    veego 	idx  = m68k_btop(sva - KERNBASE);
   3091      1.25    veego 	eidx = m68k_btop(eva - KERNBASE);
   3092       1.9      gwr 
   3093      1.24   jeremy 	while (idx < eidx) {
   3094       1.9      gwr 		pmap_remove_pte(&kernCbase[idx++]);
   3095      1.24   jeremy 		TBIS(sva);
   3096      1.24   jeremy 		sva += NBPG;
   3097      1.24   jeremy 	}
   3098       1.1      gwr }
   3099       1.1      gwr 
   3100       1.1      gwr /* pmap_remove			INTERFACE
   3101       1.1      gwr  **
   3102       1.1      gwr  * Remove the mapping of a range of virtual addresses from the given pmap.
   3103       1.7      gwr  *
   3104       1.7      gwr  * If the range contains any wired entries, this function will probably create
   3105       1.7      gwr  * disaster.
   3106       1.1      gwr  */
   3107       1.1      gwr void
   3108       1.1      gwr pmap_remove(pmap, start, end)
   3109       1.1      gwr 	pmap_t pmap;
   3110       1.1      gwr 	vm_offset_t start;
   3111       1.1      gwr 	vm_offset_t end;
   3112       1.1      gwr {
   3113       1.7      gwr 
   3114       1.1      gwr 	if (pmap == pmap_kernel()) {
   3115       1.1      gwr 		pmap_remove_kernel(start, end);
   3116       1.1      gwr 		return;
   3117       1.1      gwr 	}
   3118       1.1      gwr 
   3119       1.7      gwr 	/*
   3120       1.7      gwr 	 * XXX - Temporary(?) statement to prevent panic caused
   3121       1.7      gwr 	 * by vm_alloc_with_pager() handing us a software map (ie NULL)
   3122       1.7      gwr 	 * to remove because it couldn't get backing store.
   3123       1.7      gwr 	 * (I guess.)
   3124       1.7      gwr 	 */
   3125       1.7      gwr 	if (pmap == NULL)
   3126       1.7      gwr 		return;
   3127       1.7      gwr 
   3128       1.7      gwr 	/*
   3129       1.7      gwr 	 * If the pmap doesn't have an A table of its own, it has no mappings
   3130       1.7      gwr 	 * that can be removed.
   3131       1.1      gwr 	 */
   3132       1.7      gwr 	if (pmap->pm_a_tmgr == NULL)
   3133       1.7      gwr 		return;
   3134       1.7      gwr 
   3135       1.7      gwr 	/*
   3136       1.7      gwr 	 * Remove the specified range from the pmap.  If the function
   3137       1.7      gwr 	 * returns true, the operation removed all the valid mappings
   3138       1.7      gwr 	 * in the pmap and freed its A table.  If this happened to the
   3139       1.7      gwr 	 * currently loaded pmap, the MMU root pointer must be reloaded
   3140       1.7      gwr 	 * with the default 'kernel' map.
   3141       1.7      gwr 	 */
   3142       1.7      gwr 	if (pmap_remove_a(pmap->pm_a_tmgr, start, end)) {
   3143       1.9      gwr 		if (kernel_crp.rp_addr == pmap->pm_a_phys) {
   3144       1.9      gwr 			kernel_crp.rp_addr = kernAphys;
   3145       1.9      gwr 			loadcrp(&kernel_crp);
   3146       1.9      gwr 			/* will do TLB flush below */
   3147       1.9      gwr 		}
   3148       1.7      gwr 		pmap->pm_a_tmgr = NULL;
   3149       1.7      gwr 		pmap->pm_a_phys = kernAphys;
   3150       1.1      gwr 	}
   3151       1.9      gwr 
   3152       1.9      gwr 	/*
   3153       1.9      gwr 	 * If we just modified the current address space,
   3154       1.9      gwr 	 * make sure to flush the MMU cache.
   3155       1.9      gwr 	 *
   3156       1.9      gwr 	 * XXX - this could be an unecessarily large flush.
   3157       1.9      gwr 	 * XXX - Could decide, based on the size of the VA range
   3158       1.9      gwr 	 * to be removed, whether to flush "by pages" or "all".
   3159       1.9      gwr 	 */
   3160       1.9      gwr 	if (pmap == current_pmap())
   3161       1.9      gwr 		TBIAU();
   3162       1.1      gwr }
   3163       1.1      gwr 
   3164       1.1      gwr /* pmap_remove_a			INTERNAL
   3165       1.1      gwr  **
   3166       1.1      gwr  * This is function number one in a set of three that removes a range
   3167       1.1      gwr  * of memory in the most efficient manner by removing the highest possible
   3168       1.1      gwr  * tables from the memory space.  This particular function attempts to remove
   3169       1.1      gwr  * as many B tables as it can, delegating the remaining fragmented ranges to
   3170       1.1      gwr  * pmap_remove_b().
   3171       1.1      gwr  *
   3172       1.7      gwr  * If the removal operation results in an empty A table, the function returns
   3173       1.7      gwr  * TRUE.
   3174       1.7      gwr  *
   3175       1.1      gwr  * It's ugly but will do for now.
   3176       1.1      gwr  */
   3177       1.7      gwr boolean_t
   3178       1.1      gwr pmap_remove_a(a_tbl, start, end)
   3179       1.1      gwr 	a_tmgr_t *a_tbl;
   3180       1.1      gwr 	vm_offset_t start;
   3181       1.1      gwr 	vm_offset_t end;
   3182       1.1      gwr {
   3183       1.7      gwr 	boolean_t empty;
   3184       1.1      gwr 	int idx;
   3185       1.7      gwr 	vm_offset_t nstart, nend;
   3186       1.1      gwr 	b_tmgr_t *b_tbl;
   3187       1.1      gwr 	mmu_long_dte_t  *a_dte;
   3188       1.1      gwr 	mmu_short_dte_t *b_dte;
   3189       1.8      gwr 
   3190       1.7      gwr 	/*
   3191       1.7      gwr 	 * The following code works with what I call a 'granularity
   3192       1.7      gwr 	 * reduction algorithim'.  A range of addresses will always have
   3193       1.7      gwr 	 * the following properties, which are classified according to
   3194       1.7      gwr 	 * how the range relates to the size of the current granularity
   3195       1.7      gwr 	 * - an A table entry:
   3196       1.7      gwr 	 *
   3197       1.7      gwr 	 *            1 2       3 4
   3198       1.7      gwr 	 * -+---+---+---+---+---+---+---+-
   3199       1.7      gwr 	 * -+---+---+---+---+---+---+---+-
   3200       1.7      gwr 	 *
   3201       1.7      gwr 	 * A range will always start on a granularity boundary, illustrated
   3202       1.7      gwr 	 * by '+' signs in the table above, or it will start at some point
   3203       1.7      gwr 	 * inbetween a granularity boundary, as illustrated by point 1.
   3204       1.7      gwr 	 * The first step in removing a range of addresses is to remove the
   3205       1.7      gwr 	 * range between 1 and 2, the nearest granularity boundary.  This
   3206       1.7      gwr 	 * job is handled by the section of code governed by the
   3207       1.7      gwr 	 * 'if (start < nstart)' statement.
   3208       1.7      gwr 	 *
   3209       1.7      gwr 	 * A range will always encompass zero or more intergral granules,
   3210       1.7      gwr 	 * illustrated by points 2 and 3.  Integral granules are easy to
   3211       1.7      gwr 	 * remove.  The removal of these granules is the second step, and
   3212       1.7      gwr 	 * is handled by the code block 'if (nstart < nend)'.
   3213       1.7      gwr 	 *
   3214       1.7      gwr 	 * Lastly, a range will always end on a granularity boundary,
   3215       1.7      gwr 	 * ill. by point 3, or it will fall just beyond one, ill. by point
   3216       1.7      gwr 	 * 4.  The last step involves removing this range and is handled by
   3217       1.7      gwr 	 * the code block 'if (nend < end)'.
   3218       1.7      gwr 	 */
   3219       1.1      gwr 	nstart = MMU_ROUND_UP_A(start);
   3220       1.1      gwr 	nend = MMU_ROUND_A(end);
   3221       1.1      gwr 
   3222       1.1      gwr 	if (start < nstart) {
   3223       1.7      gwr 		/*
   3224       1.7      gwr 		 * This block is executed if the range starts between
   3225       1.7      gwr 		 * a granularity boundary.
   3226       1.7      gwr 		 *
   3227       1.7      gwr 		 * First find the DTE which is responsible for mapping
   3228       1.7      gwr 		 * the start of the range.
   3229       1.7      gwr 		 */
   3230       1.1      gwr 		idx = MMU_TIA(start);
   3231       1.1      gwr 		a_dte = &a_tbl->at_dtbl[idx];
   3232       1.7      gwr 
   3233       1.7      gwr 		/*
   3234       1.7      gwr 		 * If the DTE is valid then delegate the removal of the sub
   3235       1.7      gwr 		 * range to pmap_remove_b(), which can remove addresses at
   3236       1.7      gwr 		 * a finer granularity.
   3237       1.7      gwr 		 */
   3238       1.1      gwr 		if (MMU_VALID_DT(*a_dte)) {
   3239       1.7      gwr 			b_dte = mmu_ptov(a_dte->addr.raw);
   3240       1.1      gwr 			b_tbl = mmuB2tmgr(b_dte);
   3241       1.7      gwr 
   3242       1.7      gwr 			/*
   3243       1.7      gwr 			 * The sub range to be removed starts at the start
   3244       1.7      gwr 			 * of the full range we were asked to remove, and ends
   3245       1.7      gwr 			 * at the greater of:
   3246       1.7      gwr 			 * 1. The end of the full range, -or-
   3247       1.7      gwr 			 * 2. The end of the full range, rounded down to the
   3248       1.7      gwr 			 *    nearest granularity boundary.
   3249       1.7      gwr 			 */
   3250       1.7      gwr 			if (end < nstart)
   3251       1.8      gwr 				empty = pmap_remove_b(b_tbl, start, end);
   3252       1.7      gwr 			else
   3253       1.8      gwr 				empty = pmap_remove_b(b_tbl, start, nstart);
   3254       1.7      gwr 
   3255       1.7      gwr 			/*
   3256       1.7      gwr 			 * If the removal resulted in an empty B table,
   3257       1.7      gwr 			 * invalidate the DTE that points to it and decrement
   3258       1.7      gwr 			 * the valid entry count of the A table.
   3259       1.7      gwr 			 */
   3260       1.7      gwr 			if (empty) {
   3261       1.7      gwr 				a_dte->attr.raw = MMU_DT_INVALID;
   3262       1.7      gwr 				a_tbl->at_ecnt--;
   3263       1.1      gwr 			}
   3264       1.1      gwr 		}
   3265       1.7      gwr 		/*
   3266       1.7      gwr 		 * If the DTE is invalid, the address range is already non-
   3267       1.7      gwr 		 * existant and can simply be skipped.
   3268       1.7      gwr 		 */
   3269       1.1      gwr 	}
   3270       1.1      gwr 	if (nstart < nend) {
   3271       1.7      gwr 		/*
   3272       1.8      gwr 		 * This block is executed if the range spans a whole number
   3273       1.7      gwr 		 * multiple of granules (A table entries.)
   3274       1.7      gwr 		 *
   3275       1.7      gwr 		 * First find the DTE which is responsible for mapping
   3276       1.7      gwr 		 * the start of the first granule involved.
   3277       1.7      gwr 		 */
   3278       1.1      gwr 		idx = MMU_TIA(nstart);
   3279       1.1      gwr 		a_dte = &a_tbl->at_dtbl[idx];
   3280       1.7      gwr 
   3281       1.7      gwr 		/*
   3282       1.7      gwr 		 * Remove entire sub-granules (B tables) one at a time,
   3283       1.7      gwr 		 * until reaching the end of the range.
   3284       1.7      gwr 		 */
   3285       1.7      gwr 		for (; nstart < nend; a_dte++, nstart += MMU_TIA_RANGE)
   3286       1.1      gwr 			if (MMU_VALID_DT(*a_dte)) {
   3287       1.7      gwr 				/*
   3288       1.7      gwr 				 * Find the B table manager for the
   3289       1.7      gwr 				 * entry and free it.
   3290       1.7      gwr 				 */
   3291       1.7      gwr 				b_dte = mmu_ptov(a_dte->addr.raw);
   3292       1.1      gwr 				b_tbl = mmuB2tmgr(b_dte);
   3293       1.7      gwr 				free_b_table(b_tbl, TRUE);
   3294       1.7      gwr 
   3295       1.7      gwr 				/*
   3296       1.7      gwr 				 * Invalidate the DTE that points to the
   3297       1.7      gwr 				 * B table and decrement the valid entry
   3298       1.7      gwr 				 * count of the A table.
   3299       1.7      gwr 				 */
   3300       1.1      gwr 				a_dte->attr.raw = MMU_DT_INVALID;
   3301       1.1      gwr 				a_tbl->at_ecnt--;
   3302       1.1      gwr 			}
   3303       1.1      gwr 	}
   3304       1.1      gwr 	if (nend < end) {
   3305       1.7      gwr 		/*
   3306       1.7      gwr 		 * This block is executed if the range ends beyond a
   3307       1.7      gwr 		 * granularity boundary.
   3308       1.7      gwr 		 *
   3309       1.7      gwr 		 * First find the DTE which is responsible for mapping
   3310       1.7      gwr 		 * the start of the nearest (rounded down) granularity
   3311       1.7      gwr 		 * boundary.
   3312       1.7      gwr 		 */
   3313       1.1      gwr 		idx = MMU_TIA(nend);
   3314       1.1      gwr 		a_dte = &a_tbl->at_dtbl[idx];
   3315       1.7      gwr 
   3316       1.7      gwr 		/*
   3317       1.7      gwr 		 * If the DTE is valid then delegate the removal of the sub
   3318       1.7      gwr 		 * range to pmap_remove_b(), which can remove addresses at
   3319       1.7      gwr 		 * a finer granularity.
   3320       1.7      gwr 		 */
   3321       1.1      gwr 		if (MMU_VALID_DT(*a_dte)) {
   3322       1.7      gwr 			/*
   3323       1.7      gwr 			 * Find the B table manager for the entry
   3324       1.7      gwr 			 * and hand it to pmap_remove_b() along with
   3325       1.7      gwr 			 * the sub range.
   3326       1.7      gwr 			 */
   3327       1.7      gwr 			b_dte = mmu_ptov(a_dte->addr.raw);
   3328       1.1      gwr 			b_tbl = mmuB2tmgr(b_dte);
   3329       1.7      gwr 
   3330       1.8      gwr 			empty = pmap_remove_b(b_tbl, nend, end);
   3331       1.7      gwr 
   3332       1.7      gwr 			/*
   3333       1.7      gwr 			 * If the removal resulted in an empty B table,
   3334       1.7      gwr 			 * invalidate the DTE that points to it and decrement
   3335       1.7      gwr 			 * the valid entry count of the A table.
   3336       1.7      gwr 			 */
   3337       1.7      gwr 			if (empty) {
   3338       1.7      gwr 				a_dte->attr.raw = MMU_DT_INVALID;
   3339       1.7      gwr 				a_tbl->at_ecnt--;
   3340       1.7      gwr 			}
   3341       1.1      gwr 		}
   3342       1.1      gwr 	}
   3343       1.7      gwr 
   3344       1.7      gwr 	/*
   3345       1.7      gwr 	 * If there are no more entries in the A table, release it
   3346       1.7      gwr 	 * back to the available pool and return TRUE.
   3347       1.7      gwr 	 */
   3348       1.7      gwr 	if (a_tbl->at_ecnt == 0) {
   3349       1.7      gwr 		a_tbl->at_parent = NULL;
   3350       1.7      gwr 		TAILQ_REMOVE(&a_pool, a_tbl, at_link);
   3351       1.7      gwr 		TAILQ_INSERT_HEAD(&a_pool, a_tbl, at_link);
   3352       1.7      gwr 		empty = TRUE;
   3353       1.7      gwr 	} else {
   3354       1.7      gwr 		empty = FALSE;
   3355       1.7      gwr 	}
   3356       1.7      gwr 
   3357       1.7      gwr 	return empty;
   3358       1.1      gwr }
   3359       1.1      gwr 
   3360       1.1      gwr /* pmap_remove_b			INTERNAL
   3361       1.1      gwr  **
   3362       1.1      gwr  * Remove a range of addresses from an address space, trying to remove entire
   3363       1.1      gwr  * C tables if possible.
   3364       1.7      gwr  *
   3365       1.7      gwr  * If the operation results in an empty B table, the function returns TRUE.
   3366       1.1      gwr  */
   3367       1.7      gwr boolean_t
   3368       1.8      gwr pmap_remove_b(b_tbl, start, end)
   3369       1.1      gwr 	b_tmgr_t *b_tbl;
   3370       1.1      gwr 	vm_offset_t start;
   3371       1.1      gwr 	vm_offset_t end;
   3372       1.1      gwr {
   3373       1.7      gwr 	boolean_t empty;
   3374       1.1      gwr 	int idx;
   3375       1.1      gwr 	vm_offset_t nstart, nend, rstart;
   3376       1.1      gwr 	c_tmgr_t *c_tbl;
   3377       1.1      gwr 	mmu_short_dte_t  *b_dte;
   3378       1.1      gwr 	mmu_short_pte_t  *c_dte;
   3379       1.1      gwr 
   3380       1.1      gwr 
   3381       1.1      gwr 	nstart = MMU_ROUND_UP_B(start);
   3382       1.1      gwr 	nend = MMU_ROUND_B(end);
   3383       1.1      gwr 
   3384       1.1      gwr 	if (start < nstart) {
   3385       1.1      gwr 		idx = MMU_TIB(start);
   3386       1.1      gwr 		b_dte = &b_tbl->bt_dtbl[idx];
   3387       1.1      gwr 		if (MMU_VALID_DT(*b_dte)) {
   3388       1.7      gwr 			c_dte = mmu_ptov(MMU_DTE_PA(*b_dte));
   3389       1.1      gwr 			c_tbl = mmuC2tmgr(c_dte);
   3390       1.7      gwr 			if (end < nstart)
   3391       1.8      gwr 				empty = pmap_remove_c(c_tbl, start, end);
   3392       1.7      gwr 			else
   3393       1.8      gwr 				empty = pmap_remove_c(c_tbl, start, nstart);
   3394       1.7      gwr 			if (empty) {
   3395       1.7      gwr 				b_dte->attr.raw = MMU_DT_INVALID;
   3396       1.7      gwr 				b_tbl->bt_ecnt--;
   3397       1.1      gwr 			}
   3398       1.1      gwr 		}
   3399       1.1      gwr 	}
   3400       1.1      gwr 	if (nstart < nend) {
   3401       1.1      gwr 		idx = MMU_TIB(nstart);
   3402       1.1      gwr 		b_dte = &b_tbl->bt_dtbl[idx];
   3403       1.1      gwr 		rstart = nstart;
   3404       1.1      gwr 		while (rstart < nend) {
   3405       1.1      gwr 			if (MMU_VALID_DT(*b_dte)) {
   3406       1.7      gwr 				c_dte = mmu_ptov(MMU_DTE_PA(*b_dte));
   3407       1.1      gwr 				c_tbl = mmuC2tmgr(c_dte);
   3408       1.7      gwr 				free_c_table(c_tbl, TRUE);
   3409       1.1      gwr 				b_dte->attr.raw = MMU_DT_INVALID;
   3410       1.1      gwr 				b_tbl->bt_ecnt--;
   3411       1.1      gwr 			}
   3412       1.1      gwr 			b_dte++;
   3413       1.1      gwr 			rstart += MMU_TIB_RANGE;
   3414       1.1      gwr 		}
   3415       1.1      gwr 	}
   3416       1.1      gwr 	if (nend < end) {
   3417       1.1      gwr 		idx = MMU_TIB(nend);
   3418       1.1      gwr 		b_dte = &b_tbl->bt_dtbl[idx];
   3419       1.1      gwr 		if (MMU_VALID_DT(*b_dte)) {
   3420       1.7      gwr 			c_dte = mmu_ptov(MMU_DTE_PA(*b_dte));
   3421       1.1      gwr 			c_tbl = mmuC2tmgr(c_dte);
   3422       1.8      gwr 			empty = pmap_remove_c(c_tbl, nend, end);
   3423       1.7      gwr 			if (empty) {
   3424       1.7      gwr 				b_dte->attr.raw = MMU_DT_INVALID;
   3425       1.7      gwr 				b_tbl->bt_ecnt--;
   3426       1.7      gwr 			}
   3427       1.1      gwr 		}
   3428       1.1      gwr 	}
   3429       1.7      gwr 
   3430       1.7      gwr 	if (b_tbl->bt_ecnt == 0) {
   3431       1.7      gwr 		b_tbl->bt_parent = NULL;
   3432       1.7      gwr 		TAILQ_REMOVE(&b_pool, b_tbl, bt_link);
   3433       1.7      gwr 		TAILQ_INSERT_HEAD(&b_pool, b_tbl, bt_link);
   3434       1.7      gwr 		empty = TRUE;
   3435       1.7      gwr 	} else {
   3436       1.7      gwr 		empty = FALSE;
   3437       1.7      gwr 	}
   3438       1.7      gwr 
   3439       1.7      gwr 	return empty;
   3440       1.1      gwr }
   3441       1.1      gwr 
   3442       1.1      gwr /* pmap_remove_c			INTERNAL
   3443       1.1      gwr  **
   3444       1.1      gwr  * Remove a range of addresses from the given C table.
   3445       1.1      gwr  */
   3446       1.7      gwr boolean_t
   3447       1.8      gwr pmap_remove_c(c_tbl, start, end)
   3448       1.1      gwr 	c_tmgr_t *c_tbl;
   3449       1.1      gwr 	vm_offset_t start;
   3450       1.1      gwr 	vm_offset_t end;
   3451       1.1      gwr {
   3452       1.7      gwr 	boolean_t empty;
   3453       1.1      gwr 	int idx;
   3454       1.1      gwr 	mmu_short_pte_t *c_pte;
   3455       1.1      gwr 
   3456       1.1      gwr 	idx = MMU_TIC(start);
   3457       1.1      gwr 	c_pte = &c_tbl->ct_dtbl[idx];
   3458       1.8      gwr 	for (;start < end; start += MMU_PAGE_SIZE, c_pte++) {
   3459       1.7      gwr 		if (MMU_VALID_DT(*c_pte)) {
   3460       1.1      gwr 			pmap_remove_pte(c_pte);
   3461       1.7      gwr 			c_tbl->ct_ecnt--;
   3462       1.7      gwr 		}
   3463       1.1      gwr 	}
   3464       1.7      gwr 
   3465       1.7      gwr 	if (c_tbl->ct_ecnt == 0) {
   3466       1.7      gwr 		c_tbl->ct_parent = NULL;
   3467       1.7      gwr 		TAILQ_REMOVE(&c_pool, c_tbl, ct_link);
   3468       1.9      gwr 		TAILQ_INSERT_HEAD(&c_pool, c_tbl, ct_link);
   3469       1.9      gwr 		empty = TRUE;
   3470       1.9      gwr 	} else {
   3471       1.9      gwr 		empty = FALSE;
   3472       1.9      gwr 	}
   3473       1.7      gwr 
   3474       1.9      gwr 	return empty;
   3475       1.1      gwr }
   3476       1.1      gwr 
   3477       1.1      gwr /* is_managed				INTERNAL
   3478       1.1      gwr  **
   3479       1.1      gwr  * Determine if the given physical address is managed by the PV system.
   3480       1.1      gwr  * Note that this logic assumes that no one will ask for the status of
   3481       1.1      gwr  * addresses which lie in-between the memory banks on the 3/80.  If they
   3482       1.1      gwr  * do so, it will falsely report that it is managed.
   3483       1.7      gwr  *
   3484       1.8      gwr  * Note: A "managed" address is one that was reported to the VM system as
   3485       1.8      gwr  * a "usable page" during system startup.  As such, the VM system expects the
   3486       1.8      gwr  * pmap module to keep an accurate track of the useage of those pages.
   3487       1.8      gwr  * Any page not given to the VM system at startup does not exist (as far as
   3488       1.8      gwr  * the VM system is concerned) and is therefore "unmanaged."  Examples are
   3489       1.8      gwr  * those pages which belong to the ROM monitor and the memory allocated before
   3490       1.8      gwr  * the VM system was started.
   3491       1.1      gwr  */
   3492       1.1      gwr boolean_t
   3493       1.1      gwr is_managed(pa)
   3494       1.1      gwr 	vm_offset_t pa;
   3495       1.1      gwr {
   3496       1.1      gwr 	if (pa >= avail_start && pa < avail_end)
   3497       1.1      gwr 		return TRUE;
   3498       1.1      gwr 	else
   3499       1.1      gwr 		return FALSE;
   3500       1.1      gwr }
   3501       1.1      gwr 
   3502       1.1      gwr /* pmap_bootstrap_alloc			INTERNAL
   3503       1.1      gwr  **
   3504       1.1      gwr  * Used internally for memory allocation at startup when malloc is not
   3505       1.1      gwr  * available.  This code will fail once it crosses the first memory
   3506       1.1      gwr  * bank boundary on the 3/80.  Hopefully by then however, the VM system
   3507       1.1      gwr  * will be in charge of allocation.
   3508       1.1      gwr  */
   3509       1.1      gwr void *
   3510       1.1      gwr pmap_bootstrap_alloc(size)
   3511       1.1      gwr 	int size;
   3512       1.1      gwr {
   3513       1.1      gwr 	void *rtn;
   3514       1.1      gwr 
   3515       1.8      gwr #ifdef	PMAP_DEBUG
   3516       1.7      gwr 	if (bootstrap_alloc_enabled == FALSE) {
   3517       1.7      gwr 		mon_printf("pmap_bootstrap_alloc: disabled\n");
   3518       1.7      gwr 		sunmon_abort();
   3519       1.7      gwr 	}
   3520       1.7      gwr #endif
   3521       1.7      gwr 
   3522       1.1      gwr 	rtn = (void *) virtual_avail;
   3523       1.1      gwr 	virtual_avail += size;
   3524       1.1      gwr 
   3525       1.8      gwr #ifdef	PMAP_DEBUG
   3526       1.7      gwr 	if (virtual_avail > virtual_contig_end) {
   3527       1.7      gwr 		mon_printf("pmap_bootstrap_alloc: out of mem\n");
   3528       1.7      gwr 		sunmon_abort();
   3529       1.1      gwr 	}
   3530       1.7      gwr #endif
   3531       1.1      gwr 
   3532       1.1      gwr 	return rtn;
   3533       1.1      gwr }
   3534       1.1      gwr 
   3535       1.1      gwr /* pmap_bootstap_aalign			INTERNAL
   3536       1.1      gwr  **
   3537       1.7      gwr  * Used to insure that the next call to pmap_bootstrap_alloc() will
   3538       1.7      gwr  * return a chunk of memory aligned to the specified size.
   3539       1.8      gwr  *
   3540       1.8      gwr  * Note: This function will only support alignment sizes that are powers
   3541       1.8      gwr  * of two.
   3542       1.1      gwr  */
   3543       1.1      gwr void
   3544       1.1      gwr pmap_bootstrap_aalign(size)
   3545       1.1      gwr 	int size;
   3546       1.1      gwr {
   3547       1.7      gwr 	int off;
   3548       1.7      gwr 
   3549       1.7      gwr 	off = virtual_avail & (size - 1);
   3550       1.7      gwr 	if (off) {
   3551       1.7      gwr 		(void) pmap_bootstrap_alloc(size - off);
   3552       1.1      gwr 	}
   3553       1.1      gwr }
   3554       1.7      gwr 
   3555       1.8      gwr /* pmap_pa_exists
   3556       1.8      gwr  **
   3557       1.8      gwr  * Used by the /dev/mem driver to see if a given PA is memory
   3558       1.8      gwr  * that can be mapped.  (The PA is not in a hole.)
   3559       1.8      gwr  */
   3560       1.8      gwr int
   3561       1.8      gwr pmap_pa_exists(pa)
   3562       1.8      gwr 	vm_offset_t pa;
   3563       1.8      gwr {
   3564      1.21      gwr 	register int i;
   3565      1.21      gwr 
   3566      1.21      gwr 	for (i = 0; i < SUN3X_NPHYS_RAM_SEGS; i++) {
   3567      1.21      gwr 		if ((pa >= avail_mem[i].pmem_start) &&
   3568      1.21      gwr 			(pa <  avail_mem[i].pmem_end))
   3569      1.21      gwr 			return (1);
   3570      1.21      gwr 		if (avail_mem[i].pmem_next == NULL)
   3571      1.21      gwr 			break;
   3572      1.21      gwr 	}
   3573       1.8      gwr 	return (0);
   3574       1.8      gwr }
   3575       1.8      gwr 
   3576      1.31      gwr /* Called only from locore.s and pmap.c */
   3577      1.31      gwr void	_pmap_switch __P((pmap_t pmap));
   3578      1.31      gwr 
   3579      1.31      gwr /*
   3580      1.31      gwr  * _pmap_switch			INTERNAL
   3581      1.31      gwr  *
   3582      1.31      gwr  * This is called by locore.s:cpu_switch() when it is
   3583      1.31      gwr  * switching to a new process.  Load new translations.
   3584      1.31      gwr  * Note: done in-line by locore.s unless PMAP_DEBUG
   3585      1.24   jeremy  *
   3586      1.31      gwr  * Note that we do NOT allocate a context here, but
   3587      1.31      gwr  * share the "kernel only" context until we really
   3588      1.31      gwr  * need our own context for user-space mappings in
   3589      1.31      gwr  * pmap_enter_user().  [ s/context/mmu A table/ ]
   3590       1.1      gwr  */
   3591       1.1      gwr void
   3592      1.31      gwr _pmap_switch(pmap)
   3593      1.31      gwr 	pmap_t pmap;
   3594       1.1      gwr {
   3595       1.7      gwr 	u_long rootpa;
   3596       1.7      gwr 
   3597      1.31      gwr 	/*
   3598      1.31      gwr 	 * Only do reload/flush if we have to.
   3599      1.31      gwr 	 * Note that if the old and new process
   3600      1.31      gwr 	 * were BOTH using the "null" context,
   3601      1.31      gwr 	 * then this will NOT flush the TLB.
   3602      1.31      gwr 	 */
   3603       1.7      gwr 	rootpa = pmap->pm_a_phys;
   3604      1.31      gwr 	if (kernel_crp.rp_addr != rootpa) {
   3605      1.31      gwr 		DPRINT(("pmap_activate(%p)\n", pmap));
   3606       1.7      gwr 		kernel_crp.rp_addr = rootpa;
   3607       1.7      gwr 		loadcrp(&kernel_crp);
   3608       1.8      gwr 		TBIAU();
   3609      1.31      gwr 	}
   3610      1.31      gwr }
   3611      1.31      gwr 
   3612      1.31      gwr /*
   3613      1.31      gwr  * Exported version of pmap_activate().  This is called from the
   3614      1.31      gwr  * machine-independent VM code when a process is given a new pmap.
   3615      1.31      gwr  * If (p == curproc) do like cpu_switch would do; otherwise just
   3616      1.31      gwr  * take this as notification that the process has a new pmap.
   3617      1.31      gwr  */
   3618      1.31      gwr void
   3619      1.31      gwr pmap_activate(p)
   3620      1.31      gwr 	struct proc *p;
   3621      1.31      gwr {
   3622      1.31      gwr 	pmap_t pmap = p->p_vmspace->vm_map.pmap;
   3623      1.31      gwr 	int s;
   3624      1.31      gwr 
   3625      1.31      gwr 	if (p == curproc) {
   3626  1.50.2.4   bouyer 		s = splvm();
   3627      1.31      gwr 		_pmap_switch(pmap);
   3628      1.31      gwr 		splx(s);
   3629       1.7      gwr 	}
   3630       1.1      gwr }
   3631       1.1      gwr 
   3632      1.30  thorpej /*
   3633      1.30  thorpej  * pmap_deactivate			INTERFACE
   3634      1.30  thorpej  **
   3635      1.30  thorpej  * This is called to deactivate the specified process's address space.
   3636      1.30  thorpej  * XXX The semantics of this function are currently not well-defined.
   3637      1.30  thorpej  */
   3638      1.30  thorpej void
   3639      1.30  thorpej pmap_deactivate(p)
   3640      1.30  thorpej struct proc *p;
   3641      1.30  thorpej {
   3642      1.30  thorpej 	/* not implemented. */
   3643      1.30  thorpej }
   3644       1.1      gwr 
   3645       1.1      gwr /* pmap_update
   3646       1.1      gwr  **
   3647       1.1      gwr  * Apply any delayed changes scheduled for all pmaps immediately.
   3648       1.1      gwr  *
   3649       1.1      gwr  * No delayed operations are currently done in this pmap.
   3650       1.1      gwr  */
   3651       1.1      gwr void
   3652       1.1      gwr pmap_update()
   3653       1.1      gwr {
   3654       1.1      gwr 	/* not implemented. */
   3655       1.1      gwr }
   3656       1.1      gwr 
   3657      1.17      gwr /*
   3658      1.28      gwr  * Fill in the sun3x-specific part of the kernel core header
   3659      1.28      gwr  * for dumpsys().  (See machdep.c for the rest.)
   3660      1.17      gwr  */
   3661      1.17      gwr void
   3662      1.28      gwr pmap_kcore_hdr(sh)
   3663      1.28      gwr 	struct sun3x_kcore_hdr *sh;
   3664      1.17      gwr {
   3665      1.17      gwr 	u_long spa, len;
   3666      1.17      gwr 	int i;
   3667      1.20  thorpej 
   3668      1.28      gwr 	sh->pg_frame = MMU_SHORT_PTE_BASEADDR;
   3669      1.28      gwr 	sh->pg_valid = MMU_DT_PAGE;
   3670      1.20  thorpej 	sh->contig_end = virtual_contig_end;
   3671      1.20  thorpej 	sh->kernCbase = (u_long) kernCbase;
   3672      1.20  thorpej 	for (i = 0; i < SUN3X_NPHYS_RAM_SEGS; i++) {
   3673      1.17      gwr 		spa = avail_mem[i].pmem_start;
   3674      1.25    veego 		spa = m68k_trunc_page(spa);
   3675      1.17      gwr 		len = avail_mem[i].pmem_end - spa;
   3676      1.25    veego 		len = m68k_round_page(len);
   3677      1.20  thorpej 		sh->ram_segs[i].start = spa;
   3678      1.20  thorpej 		sh->ram_segs[i].size  = len;
   3679      1.17      gwr 	}
   3680      1.17      gwr }
   3681      1.17      gwr 
   3682      1.17      gwr 
   3683       1.1      gwr /* pmap_virtual_space			INTERFACE
   3684       1.1      gwr  **
   3685       1.1      gwr  * Return the current available range of virtual addresses in the
   3686       1.1      gwr  * arguuments provided.  Only really called once.
   3687       1.1      gwr  */
   3688       1.1      gwr void
   3689       1.1      gwr pmap_virtual_space(vstart, vend)
   3690       1.1      gwr 	vm_offset_t *vstart, *vend;
   3691       1.1      gwr {
   3692       1.1      gwr 	*vstart = virtual_avail;
   3693       1.1      gwr 	*vend = virtual_end;
   3694       1.1      gwr }
   3695       1.1      gwr 
   3696      1.37      gwr /*
   3697      1.37      gwr  * Provide memory to the VM system.
   3698      1.37      gwr  *
   3699      1.37      gwr  * Assume avail_start is always in the
   3700      1.37      gwr  * first segment as pmap_bootstrap does.
   3701      1.37      gwr  */
   3702      1.37      gwr static void
   3703      1.37      gwr pmap_page_upload()
   3704      1.37      gwr {
   3705      1.37      gwr 	vm_offset_t	a, b;	/* memory range */
   3706      1.37      gwr 	int i;
   3707      1.37      gwr 
   3708      1.37      gwr 	/* Supply the memory in segments. */
   3709      1.37      gwr 	for (i = 0; i < SUN3X_NPHYS_RAM_SEGS; i++) {
   3710      1.37      gwr 		a = atop(avail_mem[i].pmem_start);
   3711      1.37      gwr 		b = atop(avail_mem[i].pmem_end);
   3712      1.37      gwr 		if (i == 0)
   3713      1.37      gwr 			a = atop(avail_start);
   3714      1.37      gwr 
   3715      1.39  thorpej 		uvm_page_physload(a, b, a, b, VM_FREELIST_DEFAULT);
   3716      1.37      gwr 
   3717      1.37      gwr 		if (avail_mem[i].pmem_next == NULL)
   3718      1.37      gwr 			break;
   3719      1.37      gwr 	}
   3720      1.37      gwr }
   3721      1.37      gwr 
   3722      1.37      gwr /* pmap_page_index			INTERFACE
   3723      1.37      gwr  **
   3724      1.37      gwr  * Return the index of the given physical page in a list of useable
   3725      1.37      gwr  * physical pages in the system.  Holes in physical memory may be counted
   3726      1.37      gwr  * if so desired.  As long as pmap_free_pages() and pmap_page_index()
   3727      1.37      gwr  * agree as to whether holes in memory do or do not count as valid pages,
   3728      1.37      gwr  * it really doesn't matter.  However, if you like to save a little
   3729      1.37      gwr  * memory, don't count holes as valid pages.  This is even more true when
   3730      1.37      gwr  * the holes are large.
   3731      1.37      gwr  *
   3732      1.37      gwr  * We will not count holes as valid pages.  We can generate page indices
   3733      1.37      gwr  * that conform to this by using the memory bank structures initialized
   3734      1.37      gwr  * in pmap_alloc_pv().
   3735      1.37      gwr  */
   3736      1.37      gwr int
   3737      1.37      gwr pmap_page_index(pa)
   3738      1.37      gwr 	vm_offset_t pa;
   3739      1.37      gwr {
   3740      1.37      gwr 	struct pmap_physmem_struct *bank = avail_mem;
   3741      1.37      gwr 	vm_offset_t off;
   3742      1.37      gwr 
   3743      1.37      gwr 	/* Search for the memory bank with this page. */
   3744      1.37      gwr 	/* XXX - What if it is not physical memory? */
   3745      1.37      gwr 	while (pa > bank->pmem_end)
   3746      1.37      gwr 		bank = bank->pmem_next;
   3747      1.37      gwr 	off = pa - bank->pmem_start;
   3748      1.37      gwr 
   3749      1.37      gwr 	return (bank->pmem_pvbase + m68k_btop(off));
   3750       1.1      gwr }
   3751       1.8      gwr 
   3752       1.8      gwr /* pmap_count			INTERFACE
   3753       1.8      gwr  **
   3754       1.8      gwr  * Return the number of resident (valid) pages in the given pmap.
   3755       1.8      gwr  *
   3756       1.8      gwr  * Note:  If this function is handed the kernel map, it will report
   3757       1.8      gwr  * that it has no mappings.  Hopefully the VM system won't ask for kernel
   3758       1.8      gwr  * map statistics.
   3759       1.8      gwr  */
   3760       1.8      gwr segsz_t
   3761       1.8      gwr pmap_count(pmap, type)
   3762       1.8      gwr 	pmap_t pmap;
   3763       1.8      gwr 	int    type;
   3764       1.8      gwr {
   3765       1.8      gwr 	u_int     count;
   3766       1.8      gwr 	int       a_idx, b_idx;
   3767       1.8      gwr 	a_tmgr_t *a_tbl;
   3768       1.8      gwr 	b_tmgr_t *b_tbl;
   3769       1.8      gwr 	c_tmgr_t *c_tbl;
   3770       1.8      gwr 
   3771       1.8      gwr 	/*
   3772       1.8      gwr 	 * If the pmap does not have its own A table manager, it has no
   3773       1.8      gwr 	 * valid entires.
   3774       1.8      gwr 	 */
   3775       1.8      gwr 	if (pmap->pm_a_tmgr == NULL)
   3776       1.8      gwr 		return 0;
   3777       1.8      gwr 
   3778       1.8      gwr 	a_tbl = pmap->pm_a_tmgr;
   3779       1.8      gwr 
   3780       1.8      gwr 	count = 0;
   3781       1.8      gwr 	for (a_idx = 0; a_idx < MMU_TIA(KERNBASE); a_idx++) {
   3782       1.8      gwr 	    if (MMU_VALID_DT(a_tbl->at_dtbl[a_idx])) {
   3783       1.8      gwr 	        b_tbl = mmuB2tmgr(mmu_ptov(a_tbl->at_dtbl[a_idx].addr.raw));
   3784       1.8      gwr 	        for (b_idx = 0; b_idx < MMU_B_TBL_SIZE; b_idx++) {
   3785       1.8      gwr 	            if (MMU_VALID_DT(b_tbl->bt_dtbl[b_idx])) {
   3786       1.8      gwr 	                c_tbl = mmuC2tmgr(
   3787       1.8      gwr 	                    mmu_ptov(MMU_DTE_PA(b_tbl->bt_dtbl[b_idx])));
   3788       1.8      gwr 	                if (type == 0)
   3789       1.8      gwr 	                    /*
   3790       1.8      gwr 	                     * A resident entry count has been requested.
   3791       1.8      gwr 	                     */
   3792       1.8      gwr 	                    count += c_tbl->ct_ecnt;
   3793       1.8      gwr 	                else
   3794       1.8      gwr 	                    /*
   3795       1.8      gwr 	                     * A wired entry count has been requested.
   3796       1.8      gwr 	                     */
   3797       1.8      gwr 	                    count += c_tbl->ct_wcnt;
   3798       1.8      gwr 	            }
   3799       1.8      gwr 	        }
   3800       1.8      gwr 	    }
   3801       1.8      gwr 	}
   3802       1.8      gwr 
   3803       1.8      gwr 	return count;
   3804       1.8      gwr }
   3805       1.8      gwr 
   3806       1.1      gwr /************************ SUN3 COMPATIBILITY ROUTINES ********************
   3807       1.1      gwr  * The following routines are only used by DDB for tricky kernel text    *
   3808       1.1      gwr  * text operations in db_memrw.c.  They are provided for sun3            *
   3809       1.1      gwr  * compatibility.                                                        *
   3810       1.1      gwr  *************************************************************************/
   3811       1.1      gwr /* get_pte			INTERNAL
   3812       1.1      gwr  **
   3813       1.1      gwr  * Return the page descriptor the describes the kernel mapping
   3814       1.1      gwr  * of the given virtual address.
   3815       1.1      gwr  */
   3816      1.14      gwr extern u_long ptest_addr __P((u_long));	/* XXX: locore.s */
   3817      1.33      gwr u_int
   3818      1.13      gwr get_pte(va)
   3819      1.13      gwr 	vm_offset_t va;
   3820      1.13      gwr {
   3821      1.13      gwr 	u_long pte_pa;
   3822      1.13      gwr 	mmu_short_pte_t *pte;
   3823      1.13      gwr 
   3824      1.13      gwr 	/* Get the physical address of the PTE */
   3825      1.13      gwr 	pte_pa = ptest_addr(va & ~PGOFSET);
   3826      1.13      gwr 
   3827      1.13      gwr 	/* Convert to a virtual address... */
   3828      1.13      gwr 	pte = (mmu_short_pte_t *) (KERNBASE + pte_pa);
   3829      1.13      gwr 
   3830      1.13      gwr 	/* Make sure it is in our level-C tables... */
   3831      1.13      gwr 	if ((pte < kernCbase) ||
   3832      1.13      gwr 		(pte >= &mmuCbase[NUM_USER_PTES]))
   3833      1.13      gwr 		return 0;
   3834      1.13      gwr 
   3835      1.13      gwr 	/* ... and just return its contents. */
   3836      1.13      gwr 	return (pte->attr.raw);
   3837      1.13      gwr }
   3838      1.13      gwr 
   3839       1.1      gwr 
   3840       1.1      gwr /* set_pte			INTERNAL
   3841       1.1      gwr  **
   3842       1.1      gwr  * Set the page descriptor that describes the kernel mapping
   3843       1.1      gwr  * of the given virtual address.
   3844       1.1      gwr  */
   3845       1.1      gwr void
   3846       1.1      gwr set_pte(va, pte)
   3847       1.1      gwr 	vm_offset_t va;
   3848      1.33      gwr 	u_int pte;
   3849       1.1      gwr {
   3850       1.1      gwr 	u_long idx;
   3851       1.1      gwr 
   3852       1.7      gwr 	if (va < KERNBASE)
   3853       1.7      gwr 		return;
   3854       1.7      gwr 
   3855      1.25    veego 	idx = (unsigned long) m68k_btop(va - KERNBASE);
   3856       1.1      gwr 	kernCbase[idx].attr.raw = pte;
   3857      1.33      gwr 	TBIS(va);
   3858       1.1      gwr }
   3859      1.42       is 
   3860      1.42       is /*
   3861      1.42       is  *	Routine:        pmap_procwr
   3862      1.42       is  *
   3863      1.42       is  *	Function:
   3864      1.42       is  *		Synchronize caches corresponding to [addr, addr+len) in p.
   3865      1.42       is  */
   3866      1.42       is void
   3867      1.42       is pmap_procwr(p, va, len)
   3868      1.42       is 	struct proc	*p;
   3869      1.42       is 	vaddr_t		va;
   3870      1.42       is 	size_t		len;
   3871      1.42       is {
   3872      1.42       is 	(void)cachectl1(0x80000004, va, len, p);
   3873      1.42       is }
   3874      1.42       is 
   3875       1.7      gwr 
   3876       1.8      gwr #ifdef	PMAP_DEBUG
   3877       1.7      gwr /************************** DEBUGGING ROUTINES **************************
   3878       1.7      gwr  * The following routines are meant to be an aid to debugging the pmap  *
   3879       1.7      gwr  * system.  They are callable from the DDB command line and should be   *
   3880       1.7      gwr  * prepared to be handed unstable or incomplete states of the system.   *
   3881       1.7      gwr  ************************************************************************/
   3882       1.7      gwr 
   3883       1.7      gwr /* pv_list
   3884       1.7      gwr  **
   3885       1.7      gwr  * List all pages found on the pv list for the given physical page.
   3886       1.8      gwr  * To avoid endless loops, the listing will stop at the end of the list
   3887       1.7      gwr  * or after 'n' entries - whichever comes first.
   3888       1.7      gwr  */
   3889       1.7      gwr void
   3890       1.7      gwr pv_list(pa, n)
   3891       1.7      gwr 	vm_offset_t pa;
   3892       1.7      gwr 	int n;
   3893       1.7      gwr {
   3894       1.7      gwr 	int  idx;
   3895       1.7      gwr 	vm_offset_t va;
   3896       1.7      gwr 	pv_t *pv;
   3897       1.7      gwr 	c_tmgr_t *c_tbl;
   3898       1.7      gwr 	pmap_t pmap;
   3899       1.7      gwr 
   3900       1.7      gwr 	pv = pa2pv(pa);
   3901       1.7      gwr 	idx = pv->pv_idx;
   3902       1.7      gwr 
   3903      1.32      gwr 	for (;idx != PVE_EOL && n > 0;
   3904      1.32      gwr 		 idx=pvebase[idx].pve_next, n--) {
   3905      1.32      gwr 
   3906       1.8      gwr 		va = pmap_get_pteinfo(idx, &pmap, &c_tbl);
   3907       1.7      gwr 		printf("idx %d, pmap 0x%x, va 0x%x, c_tbl %x\n",
   3908       1.7      gwr 			idx, (u_int) pmap, (u_int) va, (u_int) c_tbl);
   3909       1.7      gwr 	}
   3910       1.7      gwr }
   3911       1.8      gwr #endif	/* PMAP_DEBUG */
   3912       1.1      gwr 
   3913       1.1      gwr #ifdef NOT_YET
   3914       1.1      gwr /* and maybe not ever */
   3915       1.1      gwr /************************** LOW-LEVEL ROUTINES **************************
   3916       1.1      gwr  * These routines will eventualy be re-written into assembly and placed *
   3917       1.1      gwr  * in locore.s.  They are here now as stubs so that the pmap module can *
   3918       1.1      gwr  * be linked as a standalone user program for testing.                  *
   3919       1.1      gwr  ************************************************************************/
   3920       1.1      gwr /* flush_atc_crp			INTERNAL
   3921       1.1      gwr  **
   3922       1.1      gwr  * Flush all page descriptors derived from the given CPU Root Pointer
   3923       1.1      gwr  * (CRP), or 'A' table as it is known here, from the 68851's automatic
   3924       1.1      gwr  * cache.
   3925       1.1      gwr  */
   3926       1.1      gwr void
   3927       1.1      gwr flush_atc_crp(a_tbl)
   3928       1.1      gwr {
   3929       1.1      gwr 	mmu_long_rp_t rp;
   3930       1.1      gwr 
   3931       1.1      gwr 	/* Create a temporary root table pointer that points to the
   3932       1.1      gwr 	 * given A table.
   3933       1.1      gwr 	 */
   3934       1.1      gwr 	rp.attr.raw = ~MMU_LONG_RP_LU;
   3935       1.1      gwr 	rp.addr.raw = (unsigned int) a_tbl;
   3936       1.1      gwr 
   3937       1.1      gwr 	mmu_pflushr(&rp);
   3938       1.1      gwr 	/* mmu_pflushr:
   3939       1.1      gwr 	 * 	movel   sp(4)@,a0
   3940       1.1      gwr 	 * 	pflushr a0@
   3941       1.1      gwr 	 *	rts
   3942       1.1      gwr 	 */
   3943       1.1      gwr }
   3944       1.1      gwr #endif /* NOT_YET */
   3945