pmap_pvt.h revision 1.6
1 /* $NetBSD: pmap_pvt.h,v 1.6 1997/07/02 03:23:58 jeremy Exp $ */ 2 3 /*- 4 * Copyright (c) 1996 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jeremy Cooper. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 #ifndef _SUN3X_PMAPPVT_H 40 #define _SUN3X_PMAPPVT_H 41 42 /*************************** TMGR STRUCTURES *************************** 43 * The sun3x 'tmgr' structures contain MMU tables and additional * 44 * information about their current usage and availability. * 45 ***********************************************************************/ 46 typedef struct a_tmgr_struct a_tmgr_t; 47 typedef struct b_tmgr_struct b_tmgr_t; 48 typedef struct c_tmgr_struct c_tmgr_t; 49 50 /* A level A table manager contains a pointer to an MMU table of long 51 * format table descriptors (an 'A' table), a pointer to the pmap 52 * currently using the table, and the number of wired and active entries 53 * it contains. 54 */ 55 struct a_tmgr_struct { 56 pmap_t at_parent; /* pmap currently using this table */ 57 mmu_long_dte_t *at_dtbl; /* the MMU table being managed */ 58 u_char at_wcnt; /* no. of wired entries in this table */ 59 u_char at_ecnt; /* no. of valid entries in this table */ 60 TAILQ_ENTRY(a_tmgr_struct) at_link; /* list linker */ 61 }; 62 63 /* A level B table manager contains a pointer to an MMU table of 64 * short format table descriptors (a 'B' table), a pointer to the level 65 * A table manager currently using it, the index of this B table 66 * within that parent A table, and the number of wired and active entries 67 * it currently contains. 68 */ 69 struct b_tmgr_struct { 70 a_tmgr_t *bt_parent; /* Parent 'A' table manager */ 71 mmu_short_dte_t *bt_dtbl; /* the MMU table being managed */ 72 u_char bt_pidx; /* this table's index in the parent */ 73 u_char bt_wcnt; /* no. of wired entries in table */ 74 u_char bt_ecnt; /* no. of valid entries in table */ 75 TAILQ_ENTRY(b_tmgr_struct) bt_link; /* list linker */ 76 }; 77 78 /* A level 'C' table manager consists of pointer to an MMU table of short 79 * format page descriptors (a 'C' table), a pointer to the level B table 80 * manager currently using it, and the number of wired and active pages 81 * it currently contains. 82 * 83 * Additionally, the table manager contains a pointer to the pmap 84 * that is currently using it and the starting virtual address of the 85 * range that the MMU table manages. These two items can be obtained 86 * through the traversal of other table manager structures, but having 87 * them close at hand helps speed up operations in the PV system. 88 */ 89 struct c_tmgr_struct { 90 b_tmgr_t *ct_parent; /* Parent 'B' table manager */ 91 mmu_short_pte_t *ct_dtbl; /* the MMU table being managed */ 92 u_char ct_pidx; /* this table's index in the parent */ 93 u_char ct_wcnt; /* no. of wired entries in table */ 94 u_char ct_ecnt; /* no. of valid entries in table */ 95 TAILQ_ENTRY(c_tmgr_struct) ct_link; /* list linker */ 96 #define MMU_SHORT_PTE_WIRED MMU_SHORT_PTE_UN1 97 #define MMU_PTE_WIRED ((*pte)->attr.raw & MMU_SHORT_PTE_WIRED) 98 pmap_t ct_pmap; /* pmap currently using this table */ 99 vm_offset_t ct_va; /* starting va that this table maps */ 100 }; 101 102 /* The Mach VM code requires that the pmap module be able to apply 103 * several different operations on all page descriptors that map to a 104 * given physical address. A few of these are: 105 * + invalidate all mappings to a page. 106 * + change the type of protection on all mappings to a page. 107 * + determine if a physical page has been written to 108 * + determine if a physical page has been accessed (read from) 109 * + clear such information 110 * The collection of structures and tables which we used to make this 111 * possible is known as the 'Physical to Virtual' or 'PV' system. 112 * 113 * Every physical page of memory managed by the virtual memory system 114 * will have a structure which describes whether or not it has been 115 * modified or referenced, and contains a list of page descriptors that 116 * are currently mapped to it (if any). This array of structures is 117 * known as the 'PV' list. 118 * 119 ** Old PV Element structure 120 * To keep a list of page descriptors currently using the page, another 121 * structure had to be invented. Its sole purpose is to be a link in 122 * a chain of such structures. No other information is contained within 123 * the structure however! The other piece of information it holds is 124 * hidden within its address. By maintaining a one-to-one correspondence 125 * of page descriptors in the system and such structures, this address can 126 * readily be translated into its associated page descriptor by using a 127 * simple macro. This bizzare structure is simply known as a 'PV 128 * Element', or 'pve' for short. 129 * 130 ** New PV Element structure 131 * To keep a list of page descriptors currently using the page, another 132 * structure had to be invented. Its sole purpose is to indicate the index 133 * of the next PTE currently referencing the page. By maintaining a one-to- 134 * one correspondence of page descriptors in the system and such structures, 135 * this same index is also the index of the next PV element, which describes 136 * the index of yet another page mapped to the same address and so on. The 137 * special index 'PVE_EOL' is used to represent the end of the list. 138 */ 139 struct pv_struct { 140 u_short pv_idx; /* Index of PTE using this page */ 141 u_short pv_flags; /* Physical page status flags */ 142 #define PV_FLAGS_USED MMU_SHORT_PTE_USED 143 #define PV_FLAGS_MDFY MMU_SHORT_PTE_M 144 }; 145 typedef struct pv_struct pv_t; 146 147 struct pv_elem_struct { 148 u_short pve_next; 149 #define PVE_EOL 0xffff /* End-of-list marker */ 150 }; 151 typedef struct pv_elem_struct pv_elem_t; 152 153 /* Physical memory on the 3/80 is not contiguous. The ROM Monitor 154 * provides us with a linked list of memory segments describing each 155 * segment with its base address and its size. 156 */ 157 struct pmap_physmem_struct { 158 vm_offset_t pmem_start; /* Starting physical address */ 159 vm_offset_t pmem_end; /* First byte outside of range */ 160 int pmem_pvbase; /* Offset within the pv list */ 161 struct pmap_physmem_struct *pmem_next; /* Next block of memory */ 162 }; 163 164 /* Internal function definitions. */ 165 a_tmgr_t *get_a_table __P((void)); 166 b_tmgr_t *get_b_table __P((void)); 167 c_tmgr_t *get_c_table __P((void)); 168 int free_a_table __P((a_tmgr_t *, boolean_t)); 169 int free_b_table __P((b_tmgr_t *, boolean_t)); 170 int free_c_table __P((c_tmgr_t *, boolean_t)); 171 void pmap_bootstrap_aalign __P((int)); 172 void pmap_alloc_usermmu __P((void)); 173 void pmap_alloc_usertmgr __P((void)); 174 void pmap_alloc_pv __P((void)); 175 void pmap_init_a_tables __P((void)); 176 void pmap_init_b_tables __P((void)); 177 void pmap_init_c_tables __P((void)); 178 void pmap_init_pv __P((void)); 179 void pmap_clear_pv __P((vm_offset_t, int)); 180 boolean_t pmap_remove_a __P((a_tmgr_t *, vm_offset_t, vm_offset_t)); 181 boolean_t pmap_remove_b __P((b_tmgr_t *, vm_offset_t, vm_offset_t)); 182 boolean_t pmap_remove_c __P((c_tmgr_t *, vm_offset_t, vm_offset_t)); 183 void pmap_remove_pte __P((mmu_short_pte_t *)); 184 void pmap_enter_kernel __P((vm_offset_t, vm_offset_t, vm_prot_t)); 185 void pmap_remove_kernel __P((vm_offset_t, vm_offset_t)); 186 void pmap_protect_kernel __P((vm_offset_t, vm_offset_t, vm_prot_t)); 187 vm_offset_t pmap_extract_kernel __P((vm_offset_t)); 188 vm_offset_t pmap_get_pteinfo __P((u_int, pmap_t *, c_tmgr_t **)); 189 void pmap_pinit __P((pmap_t)); 190 int pmap_dereference __P((pmap_t)); 191 boolean_t is_managed __P((vm_offset_t)); 192 boolean_t pmap_stroll __P((pmap_t, vm_offset_t, a_tmgr_t **, b_tmgr_t **,\ 193 c_tmgr_t **, mmu_short_pte_t **, int *, int *, int *)); 194 void pmap_bootstrap_copyprom __P((void)); 195 void pmap_takeover_mmu __P((void)); 196 void pmap_bootstrap_setprom __P((void)); 197 198 /* Debugging function definitions */ 199 void pv_list __P((vm_offset_t, int)); 200 201 /* These are defined in pmap.c */ 202 extern struct pmap_physmem_struct avail_mem[]; 203 204 #endif /* _SUN3X_MYPMAP_H */ 205
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