pmap_pvt.h revision 1.8.16.1
1 /* $NetBSD: pmap_pvt.h,v 1.8.16.1 2001/09/13 01:15:04 thorpej Exp $ */ 2 3 /*- 4 * Copyright (c) 1996 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jeremy Cooper. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 #ifndef _SUN3X_PMAPPVT_H 40 #define _SUN3X_PMAPPVT_H 41 42 /*************************** TMGR STRUCTURES *************************** 43 * The sun3x 'tmgr' structures contain MMU tables and additional * 44 * information about their current usage and availability. * 45 ***********************************************************************/ 46 typedef struct a_tmgr_struct a_tmgr_t; 47 typedef struct b_tmgr_struct b_tmgr_t; 48 typedef struct c_tmgr_struct c_tmgr_t; 49 50 /* A level A table manager contains a pointer to an MMU table of long 51 * format table descriptors (an 'A' table), a pointer to the pmap 52 * currently using the table, and the number of wired and active entries 53 * it contains. 54 */ 55 struct a_tmgr_struct { 56 pmap_t at_parent; /* pmap currently using this table */ 57 mmu_long_dte_t *at_dtbl; /* the MMU table being managed */ 58 u_char at_wcnt; /* no. of wired entries in this table */ 59 u_char at_ecnt; /* no. of valid entries in this table */ 60 u_int16_t at_dum1; /* structure padding */ 61 TAILQ_ENTRY(a_tmgr_struct) at_link; /* list linker */ 62 }; 63 64 /* A level B table manager contains a pointer to an MMU table of 65 * short format table descriptors (a 'B' table), a pointer to the level 66 * A table manager currently using it, the index of this B table 67 * within that parent A table, and the number of wired and active entries 68 * it currently contains. 69 */ 70 struct b_tmgr_struct { 71 a_tmgr_t *bt_parent; /* Parent 'A' table manager */ 72 mmu_short_dte_t *bt_dtbl; /* the MMU table being managed */ 73 u_char bt_pidx; /* this table's index in the parent */ 74 u_char bt_wcnt; /* no. of wired entries in table */ 75 u_char bt_ecnt; /* no. of valid entries in table */ 76 u_char bt_dum1; /* structure padding */ 77 TAILQ_ENTRY(b_tmgr_struct) bt_link; /* list linker */ 78 }; 79 80 /* A level 'C' table manager consists of pointer to an MMU table of short 81 * format page descriptors (a 'C' table), a pointer to the level B table 82 * manager currently using it, and the number of wired and active pages 83 * it currently contains. 84 * 85 * Additionally, the table manager contains a pointer to the pmap 86 * that is currently using it and the starting virtual address of the 87 * range that the MMU table manages. These two items can be obtained 88 * through the traversal of other table manager structures, but having 89 * them close at hand helps speed up operations in the PV system. 90 */ 91 struct c_tmgr_struct { 92 b_tmgr_t *ct_parent; /* Parent 'B' table manager */ 93 mmu_short_pte_t *ct_dtbl; /* the MMU table being managed */ 94 u_char ct_pidx; /* this table's index in the parent */ 95 u_char ct_wcnt; /* no. of wired entries in table */ 96 u_char ct_ecnt; /* no. of valid entries in table */ 97 u_char ct_dum1; /* structure padding */ 98 TAILQ_ENTRY(c_tmgr_struct) ct_link; /* list linker */ 99 #define MMU_SHORT_PTE_WIRED MMU_SHORT_PTE_UN1 100 #define MMU_PTE_WIRED ((*pte)->attr.raw & MMU_SHORT_PTE_WIRED) 101 pmap_t ct_pmap; /* pmap currently using this table */ 102 vaddr_t ct_va; /* starting va that this table maps */ 103 }; 104 105 /* The Mach VM code requires that the pmap module be able to apply 106 * several different operations on all page descriptors that map to a 107 * given physical address. A few of these are: 108 * + invalidate all mappings to a page. 109 * + change the type of protection on all mappings to a page. 110 * + determine if a physical page has been written to 111 * + determine if a physical page has been accessed (read from) 112 * + clear such information 113 * The collection of structures and tables which we used to make this 114 * possible is known as the 'Physical to Virtual' or 'PV' system. 115 * 116 * Every physical page of memory managed by the virtual memory system 117 * will have a structure which describes whether or not it has been 118 * modified or referenced, and contains a list of page descriptors that 119 * are currently mapped to it (if any). This array of structures is 120 * known as the 'PV' list. 121 * 122 ** Old PV Element structure 123 * To keep a list of page descriptors currently using the page, another 124 * structure had to be invented. Its sole purpose is to be a link in 125 * a chain of such structures. No other information is contained within 126 * the structure however! The other piece of information it holds is 127 * hidden within its address. By maintaining a one-to-one correspondence 128 * of page descriptors in the system and such structures, this address can 129 * readily be translated into its associated page descriptor by using a 130 * simple macro. This bizzare structure is simply known as a 'PV 131 * Element', or 'pve' for short. 132 * 133 ** New PV Element structure 134 * To keep a list of page descriptors currently using the page, another 135 * structure had to be invented. Its sole purpose is to indicate the index 136 * of the next PTE currently referencing the page. By maintaining a one-to- 137 * one correspondence of page descriptors in the system and such structures, 138 * this same index is also the index of the next PV element, which describes 139 * the index of yet another page mapped to the same address and so on. The 140 * special index 'PVE_EOL' is used to represent the end of the list. 141 */ 142 struct pv_struct { 143 u_short pv_idx; /* Index of PTE using this page */ 144 u_short pv_flags; /* Physical page status flags */ 145 #define PV_FLAGS_USED MMU_SHORT_PTE_USED 146 #define PV_FLAGS_MDFY MMU_SHORT_PTE_M 147 }; 148 typedef struct pv_struct pv_t; 149 150 struct pv_elem_struct { 151 u_short pve_next; 152 #define PVE_EOL 0xffff /* End-of-list marker */ 153 }; 154 typedef struct pv_elem_struct pv_elem_t; 155 156 /* Physical memory on the 3/80 is not contiguous. The ROM Monitor 157 * provides us with a linked list of memory segments describing each 158 * segment with its base address and its size. 159 */ 160 struct pmap_physmem_struct { 161 paddr_t pmem_start; /* Starting physical address */ 162 paddr_t pmem_end; /* First byte outside of range */ 163 int pmem_pvbase; /* Offset within the pv list */ 164 struct pmap_physmem_struct *pmem_next; /* Next block of memory */ 165 }; 166 167 /* Internal function definitions. */ 168 a_tmgr_t *get_a_table __P((void)); 169 b_tmgr_t *get_b_table __P((void)); 170 c_tmgr_t *get_c_table __P((void)); 171 int free_a_table __P((a_tmgr_t *, boolean_t)); 172 int free_b_table __P((b_tmgr_t *, boolean_t)); 173 int free_c_table __P((c_tmgr_t *, boolean_t)); 174 void pmap_bootstrap_aalign __P((int)); 175 void pmap_alloc_usermmu __P((void)); 176 void pmap_alloc_usertmgr __P((void)); 177 void pmap_alloc_pv __P((void)); 178 void pmap_init_a_tables __P((void)); 179 void pmap_init_b_tables __P((void)); 180 void pmap_init_c_tables __P((void)); 181 void pmap_init_pv __P((void)); 182 void pmap_clear_pv __P((paddr_t, int)); 183 boolean_t pmap_remove_a __P((a_tmgr_t *, vaddr_t, vaddr_t)); 184 boolean_t pmap_remove_b __P((b_tmgr_t *, vaddr_t, vaddr_t)); 185 boolean_t pmap_remove_c __P((c_tmgr_t *, vaddr_t, vaddr_t)); 186 void pmap_remove_pte __P((mmu_short_pte_t *)); 187 void pmap_enter_kernel __P((vaddr_t, paddr_t, vm_prot_t)); 188 void pmap_remove_kernel __P((vaddr_t, vaddr_t)); 189 void pmap_protect_kernel __P((vaddr_t, vaddr_t, vm_prot_t)); 190 boolean_t pmap_extract_kernel __P((vaddr_t, paddr_t *)); 191 vaddr_t pmap_get_pteinfo __P((u_int, pmap_t *, c_tmgr_t **)); 192 void pmap_pinit __P((pmap_t)); 193 int pmap_dereference __P((pmap_t)); 194 boolean_t is_managed __P((paddr_t)); 195 boolean_t pmap_stroll __P((pmap_t, vaddr_t, a_tmgr_t **, b_tmgr_t **,\ 196 c_tmgr_t **, mmu_short_pte_t **, int *, int *, int *)); 197 void pmap_bootstrap_copyprom __P((void)); 198 void pmap_takeover_mmu __P((void)); 199 void pmap_bootstrap_setprom __P((void)); 200 201 #ifdef PMAP_DEBUG 202 /* Debugging function definitions */ 203 void pv_list __P((paddr_t, int)); 204 #endif /* PMAP_DEBUG */ 205 206 /* These are defined in pmap.c */ 207 extern struct pmap_physmem_struct avail_mem[]; 208 209 #endif /* _SUN3X_MYPMAP_H */ 210
Indexes created Sun Oct 26 21:10:03 GMT 2025