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intr.h revision 1.18
      1  1.18   tsutsui /*	$NetBSD: intr.h,v 1.18 2008/01/26 14:02:54 tsutsui Exp $	*/
      2   1.1  fredette 
      3   1.1  fredette /*
      4   1.1  fredette  * Copyright (c) 2001 Matt Fredette.
      5   1.1  fredette  * Copyright (c) 1998 Matt Thomas.
      6   1.1  fredette  * All rights reserved.
      7   1.1  fredette  *
      8   1.1  fredette  * Redistribution and use in source and binary forms, with or without
      9   1.1  fredette  * modification, are permitted provided that the following conditions
     10   1.1  fredette  * are met:
     11   1.1  fredette  * 1. Redistributions of source code must retain the above copyright
     12   1.1  fredette  *    notice, this list of conditions and the following disclaimer.
     13   1.1  fredette  * 2. Redistributions in binary form must reproduce the above copyright
     14   1.1  fredette  *    notice, this list of conditions and the following disclaimer in the
     15   1.1  fredette  *    documentation and/or other materials provided with the distribution.
     16   1.1  fredette  * 3. The name of the company nor the names of the authors may be used to
     17   1.1  fredette  *    endorse or promote products derived from this software without specific
     18   1.1  fredette  *    prior written permission.
     19   1.1  fredette  *
     20   1.1  fredette  * THIS SOFTWARE IS PROVIDED BY THE AUTHORS ``AS IS'' AND ANY EXPRESS OR IMPLIED
     21   1.1  fredette  * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
     22   1.1  fredette  * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
     23   1.1  fredette  * IN NO EVENT SHALL THE AUTHORS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
     24   1.1  fredette  * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
     25   1.1  fredette  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
     26   1.1  fredette  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
     27   1.1  fredette  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
     28   1.1  fredette  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
     29   1.1  fredette  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
     30   1.1  fredette  * SUCH DAMAGE.
     31   1.1  fredette  */
     32   1.1  fredette 
     33   1.1  fredette #ifndef _SUN68K_INTR_H_
     34   1.1  fredette #define _SUN68K_INTR_H_
     35   1.1  fredette 
     36   1.1  fredette #include <sys/queue.h>
     37   1.3       chs #include <m68k/psl.h>
     38   1.1  fredette 
     39   1.1  fredette /*
     40  1.10      yamt  * Interrupt levels.
     41   1.1  fredette  */
     42  1.10      yamt #define	IPL_NONE	0
     43  1.10      yamt #define	IPL_SOFTCLOCK	1
     44  1.16        ad #define	IPL_SOFTBIO	2
     45  1.16        ad #define	IPL_SOFTNET	3
     46  1.16        ad #define	IPL_SOFTSERIAL	4
     47  1.16        ad #define	IPL_VM		5
     48  1.16        ad #define	IPL_SCHED	6
     49  1.16        ad #define	IPL_HIGH	7
     50  1.10      yamt 
     51   1.1  fredette #define _IPL_SOFT_LEVEL1	1
     52   1.1  fredette #define _IPL_SOFT_LEVEL2	2
     53   1.1  fredette #define _IPL_SOFT_LEVEL3	3
     54   1.1  fredette #define _IPL_SOFT_LEVEL_MIN	1
     55   1.1  fredette #define _IPL_SOFT_LEVEL_MAX	3
     56   1.7      yamt 
     57  1.10      yamt #ifdef _KERNEL
     58  1.10      yamt 
     59  1.18   tsutsui extern int idepth;
     60  1.18   tsutsui 
     61  1.10      yamt typedef int ipl_t;
     62  1.10      yamt typedef struct {
     63  1.13   thorpej 	uint16_t _psl;
     64  1.10      yamt } ipl_cookie_t;
     65  1.10      yamt 
     66  1.10      yamt ipl_cookie_t makeiplcookie(ipl_t ipl);
     67  1.10      yamt 
     68  1.10      yamt static inline int
     69  1.10      yamt splraiseipl(ipl_cookie_t icookie)
     70  1.10      yamt {
     71  1.10      yamt 
     72  1.10      yamt 	return _splraise(icookie._psl);
     73  1.10      yamt }
     74   1.1  fredette 
     75   1.1  fredette /* These connect interrupt handlers. */
     76   1.2       chs typedef int (*isr_func_t)(void *);
     77   1.9   tsutsui void isr_add_autovect(isr_func_t, void *, int);
     78   1.9   tsutsui void isr_add_vectored(isr_func_t, void *, int, int);
     79   1.9   tsutsui void isr_add_custom(int, void *);
     80   1.1  fredette 
     81   1.3       chs /*
     82   1.3       chs  * Define inline functions for PSL manipulation.
     83   1.3       chs  * These are as close to macros as one can get.
     84   1.3       chs  * When not optimizing gcc will call the locore.s
     85   1.3       chs  * functions by the same names, so breakpoints on
     86   1.3       chs  * these functions will work normally, etc.
     87   1.3       chs  * (See the GCC extensions info document.)
     88   1.3       chs  */
     89   1.3       chs 
     90   1.6     perry static __inline int _getsr(void);
     91   1.3       chs 
     92   1.3       chs /* Get current sr value. */
     93   1.6     perry static __inline int
     94   1.3       chs _getsr(void)
     95   1.3       chs {
     96   1.3       chs 	int rv;
     97   1.3       chs 
     98   1.5     perry 	__asm volatile ("clrl %0; movew %%sr,%0" : "=&d" (rv));
     99   1.3       chs 	return (rv);
    100   1.3       chs }
    101   1.3       chs 
    102   1.3       chs /*
    103   1.3       chs  * The rest of this is sun68k specific, because other ports may
    104   1.3       chs  * need to do special things in spl0() (i.e. simulate SIR).
    105   1.3       chs  * Suns have a REAL interrupt register, so spl0() and splx(s)
    106   1.3       chs  * have no need to check for any simulated interrupts, etc.
    107   1.3       chs  */
    108   1.3       chs 
    109   1.3       chs #define spl0()  _spl0()		/* we have real software interrupts */
    110   1.3       chs #define splx(x)	_spl(x)
    111   1.3       chs 
    112   1.3       chs /* IPL used by soft interrupts: netintr(), softclock() */
    113  1.10      yamt #define splsoftclock()  splraise1()
    114  1.16        ad #define splsoftbio()    splraise1()
    115  1.10      yamt #define splsoftnet()    splraise1()
    116  1.10      yamt #define	splsoftserial()	splraise3()
    117  1.10      yamt 
    118  1.10      yamt /*
    119  1.10      yamt  * Note that the VM code runs at spl7 during kernel
    120  1.10      yamt  * initialization, and later at spl0, so we have to
    121  1.10      yamt  * use splraise to avoid enabling interrupts early.
    122  1.10      yamt  */
    123  1.14   tsutsui #define splvm()         splraise4()
    124  1.10      yamt 
    125   1.3       chs /* Zilog Serial hardware interrupts (hard-wired at 6) */
    126  1.17   tsutsui #define splzs()		splserial()
    127  1.15        ad #define	IPL_ZS		IPL_SERIAL
    128  1.10      yamt 
    129  1.10      yamt /* Block out all interrupts (except NMI of course). */
    130  1.10      yamt #define splhigh()       spl7()
    131  1.10      yamt #define splsched()      spl7()
    132   1.3       chs 
    133   1.3       chs /* This returns true iff the spl given is spl0. */
    134   1.3       chs #define	is_spl0(s)	(((s) & PSL_IPL7) == 0)
    135   1.3       chs 
    136   1.3       chs #endif	/* _KERNEL */
    137   1.3       chs 
    138   1.1  fredette #endif	/* _SUN68K_INTR_H */
    139