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intr.h revision 1.16 
      1 /*	$NetBSD: intr.h,v 1.16 2007/12/03 15:34:23 ad Exp $	*/
      2 
      3 /*
      4  * Copyright (c) 2001 Matt Fredette.
      5  * Copyright (c) 1998 Matt Thomas.
      6  * All rights reserved.
      7  *
      8  * Redistribution and use in source and binary forms, with or without
      9  * modification, are permitted provided that the following conditions
     10  * are met:
     11  * 1. Redistributions of source code must retain the above copyright
     12  *    notice, this list of conditions and the following disclaimer.
     13  * 2. Redistributions in binary form must reproduce the above copyright
     14  *    notice, this list of conditions and the following disclaimer in the
     15  *    documentation and/or other materials provided with the distribution.
     16  * 3. The name of the company nor the names of the authors may be used to
     17  *    endorse or promote products derived from this software without specific
     18  *    prior written permission.
     19  *
     20  * THIS SOFTWARE IS PROVIDED BY THE AUTHORS ``AS IS'' AND ANY EXPRESS OR IMPLIED
     21  * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
     22  * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
     23  * IN NO EVENT SHALL THE AUTHORS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
     24  * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
     25  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
     26  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
     27  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
     28  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
     29  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
     30  * SUCH DAMAGE.
     31  */
     32 
     33 #ifndef _SUN68K_INTR_H_
     34 #define _SUN68K_INTR_H_
     35 
     36 #include <sys/queue.h>
     37 #include <m68k/psl.h>
     38 
     39 /*
     40  * Interrupt levels.
     41  */
     42 #define	IPL_NONE	0
     43 #define	IPL_SOFTCLOCK	1
     44 #define	IPL_SOFTBIO	2
     45 #define	IPL_SOFTNET	3
     46 #define	IPL_SOFTSERIAL	4
     47 #define	IPL_VM		5
     48 #define	IPL_SCHED	6
     49 #define	IPL_HIGH	7
     50 
     51 #define _IPL_SOFT_LEVEL1	1
     52 #define _IPL_SOFT_LEVEL2	2
     53 #define _IPL_SOFT_LEVEL3	3
     54 #define _IPL_SOFT_LEVEL_MIN	1
     55 #define _IPL_SOFT_LEVEL_MAX	3
     56 
     57 #ifdef _KERNEL
     58 
     59 typedef int ipl_t;
     60 typedef struct {
     61 	uint16_t _psl;
     62 } ipl_cookie_t;
     63 
     64 ipl_cookie_t makeiplcookie(ipl_t ipl);
     65 
     66 static inline int
     67 splraiseipl(ipl_cookie_t icookie)
     68 {
     69 
     70 	return _splraise(icookie._psl);
     71 }
     72 
     73 /* These connect interrupt handlers. */
     74 typedef int (*isr_func_t)(void *);
     75 void isr_add_autovect(isr_func_t, void *, int);
     76 void isr_add_vectored(isr_func_t, void *, int, int);
     77 void isr_add_custom(int, void *);
     78 
     79 /*
     80  * Define inline functions for PSL manipulation.
     81  * These are as close to macros as one can get.
     82  * When not optimizing gcc will call the locore.s
     83  * functions by the same names, so breakpoints on
     84  * these functions will work normally, etc.
     85  * (See the GCC extensions info document.)
     86  */
     87 
     88 static __inline int _getsr(void);
     89 
     90 /* Get current sr value. */
     91 static __inline int
     92 _getsr(void)
     93 {
     94 	int rv;
     95 
     96 	__asm volatile ("clrl %0; movew %%sr,%0" : "=&d" (rv));
     97 	return (rv);
     98 }
     99 
    100 /*
    101  * The rest of this is sun68k specific, because other ports may
    102  * need to do special things in spl0() (i.e. simulate SIR).
    103  * Suns have a REAL interrupt register, so spl0() and splx(s)
    104  * have no need to check for any simulated interrupts, etc.
    105  */
    106 
    107 #define spl0()  _spl0()		/* we have real software interrupts */
    108 #define splx(x)	_spl(x)
    109 
    110 /* IPL used by soft interrupts: netintr(), softclock() */
    111 #define splsoftclock()  splraise1()
    112 #define splsoftbio()    splraise1()
    113 #define splsoftnet()    splraise1()
    114 #define	splsoftserial()	splraise3()
    115 
    116 /*
    117  * Note that the VM code runs at spl7 during kernel
    118  * initialization, and later at spl0, so we have to
    119  * use splraise to avoid enabling interrupts early.
    120  */
    121 #define splvm()         splraise4()
    122 
    123 /* Zilog Serial hardware interrupts (hard-wired at 6) */
    124 #define splzs()		splraise6()
    125 #define splserial()	splraise6()
    126 #define	IPL_ZS		IPL_SERIAL
    127 
    128 /* Block out all interrupts (except NMI of course). */
    129 #define splhigh()       spl7()
    130 #define splsched()      spl7()
    131 
    132 /* This returns true iff the spl given is spl0. */
    133 #define	is_spl0(s)	(((s) & PSL_IPL7) == 0)
    134 
    135 #endif	/* _KERNEL */
    136 
    137 #endif	/* _SUN68K_INTR_H */
    138