autoconf.c revision 1.5 1 1.5 ragge /* $NetBSD: autoconf.c,v 1.5 1999/08/23 19:09:27 ragge Exp $ */
2 1.1 ragge /*
3 1.1 ragge * Copyright (c) 1994, 1998 Ludd, University of Lule}, Sweden.
4 1.1 ragge * All rights reserved.
5 1.1 ragge *
6 1.1 ragge * Redistribution and use in source and binary forms, with or without
7 1.1 ragge * modification, are permitted provided that the following conditions
8 1.1 ragge * are met:
9 1.1 ragge * 1. Redistributions of source code must retain the above copyright
10 1.1 ragge * notice, this list of conditions and the following disclaimer.
11 1.1 ragge * 2. Redistributions in binary form must reproduce the above copyright
12 1.1 ragge * notice, this list of conditions and the following disclaimer in the
13 1.1 ragge * documentation and/or other materials provided with the distribution.
14 1.1 ragge * 3. All advertising materials mentioning features or use of this software
15 1.1 ragge * must display the following acknowledgement:
16 1.1 ragge * This product includes software developed at Ludd, University of Lule}.
17 1.1 ragge * 4. The name of the author may not be used to endorse or promote products
18 1.1 ragge * derived from this software without specific prior written permission
19 1.1 ragge *
20 1.1 ragge * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
21 1.1 ragge * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
22 1.1 ragge * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
23 1.1 ragge * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
24 1.1 ragge * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
25 1.1 ragge * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
26 1.1 ragge * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
27 1.1 ragge * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
28 1.1 ragge * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
29 1.1 ragge * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
30 1.1 ragge */
31 1.1 ragge
32 1.1 ragge /* All bugs are subject to removal without further notice */
33 1.1 ragge
34 1.1 ragge
35 1.1 ragge
36 1.1 ragge #include "sys/param.h"
37 1.1 ragge #include "../include/mtpr.h"
38 1.1 ragge #include "../include/sid.h"
39 1.5 ragge #include "../include/trap.h"
40 1.5 ragge #include "../include/frame.h"
41 1.1 ragge #include "vaxstand.h"
42 1.1 ragge
43 1.1 ragge int nmba=0, nuba=0, nbi=0,nsbi=0,nuda=0;
44 1.1 ragge int *mbaaddr, *ubaaddr, *biaddr;
45 1.1 ragge int *udaaddr, *uioaddr, tmsaddr, *bioaddr;
46 1.1 ragge
47 1.1 ragge static int mba750[]={0xf28000,0xf2a000,0xf2c000};
48 1.1 ragge static int uba750[]={0xf30000,0xf32000};
49 1.1 ragge static int uio750[]={0xfc0000,0xf80000};
50 1.1 ragge static int uda750[]={0772150};
51 1.1 ragge
52 1.1 ragge /* 11/780's only have 4, 8600 have 8 of these. */
53 1.1 ragge /* XXX - all of these should be bound to physical addresses */
54 1.1 ragge static int mba780[]={0x20010000,0x20012000,0x20014000,0x20016000,
55 1.1 ragge 0x22010000,0x22012000,0x22014000,0x22016000};
56 1.1 ragge static int uba780[]={0, 0, 0, 0x20006000,0x20008000,0x2000a000,0x2000c000, 0,
57 1.1 ragge 0, 0, 0, 0, 0, 0, 0, 0,
58 1.1 ragge 0, 0, 0, 0x22006000,0x22008000,0x2200a000,0x2200c000};
59 1.1 ragge static int uio780[]={0, 0, 0, 0x20100000,0x20140000,0x20180000,0x201c0000, 0,
60 1.1 ragge 0, 0, 0, 0, 0, 0, 0, 0,
61 1.1 ragge 0, 0, 0, 0x22100000,0x22140000,0x22180000,0x221c0000};
62 1.1 ragge static int bi8200[]={0x20000000, 0x22000000, 0x24000000, 0x26000000,
63 1.1 ragge 0x28000000, 0x2a000000};
64 1.1 ragge static int bio8200[]={0x20400000};
65 1.1 ragge
66 1.1 ragge static int uba630[]={0x20087800};
67 1.1 ragge static int uio630[]={0x30000000};
68 1.1 ragge #define qbdev(csr) (((csr) & 017777)-0x10000000)
69 1.1 ragge static int uda630[]={qbdev(0772150),qbdev(0760334)};
70 1.1 ragge
71 1.1 ragge static int uba670[]={0x20040000};
72 1.1 ragge static int uio670[]={0x20000000};
73 1.1 ragge static int uda670[]={0x20004030,0x20004230};
74 1.1 ragge #define qb670dev(csr) (((csr) & 017777)+0x20000000)
75 1.1 ragge
76 1.1 ragge /*
77 1.1 ragge * Autoconf routine is really stupid; but it actually don't
78 1.1 ragge * need any intelligence. We just assume that all possible
79 1.1 ragge * devices exists on each cpu. Fast & easy.
80 1.1 ragge */
81 1.1 ragge
82 1.1 ragge autoconf()
83 1.1 ragge {
84 1.1 ragge extern int memsz;
85 1.1 ragge
86 1.3 ragge findcpu(); /* Configures CPU variables */
87 1.3 ragge consinit(); /* Allow us to print out things */
88 1.3 ragge scbinit(); /* Fix interval clock etc */
89 1.3 ragge
90 1.3 ragge switch (vax_boardtype) {
91 1.1 ragge
92 1.1 ragge default:
93 1.3 ragge printf("\nCPU type %d not supported by boot\n",vax_cputype);
94 1.1 ragge printf("trying anyway...\n");
95 1.1 ragge break;
96 1.1 ragge
97 1.3 ragge case VAX_BTYP_780:
98 1.3 ragge case VAX_BTYP_790:
99 1.1 ragge memsz = 0;
100 1.1 ragge nmba = 8;
101 1.1 ragge nuba = 32; /* XXX */
102 1.1 ragge nuda = 1;
103 1.1 ragge mbaaddr = mba780;
104 1.1 ragge ubaaddr = uba780;
105 1.1 ragge udaaddr = uda750;
106 1.1 ragge uioaddr = uio780;
107 1.1 ragge tmsaddr = 0774500;
108 1.1 ragge break;
109 1.1 ragge
110 1.3 ragge case VAX_BTYP_750:
111 1.1 ragge memsz = 0;
112 1.1 ragge nmba = 3;
113 1.1 ragge nuba = 2;
114 1.1 ragge nuda = 1;
115 1.1 ragge mbaaddr = mba750;
116 1.1 ragge ubaaddr = uba750;
117 1.1 ragge udaaddr = uda750;
118 1.1 ragge uioaddr = uio750;
119 1.1 ragge tmsaddr = 0774500;
120 1.1 ragge break;
121 1.1 ragge
122 1.3 ragge case VAX_BTYP_630: /* the same for uvaxIII */
123 1.3 ragge case VAX_BTYP_650:
124 1.4 ragge case VAX_BTYP_660:
125 1.3 ragge case VAX_BTYP_670:
126 1.1 ragge nuba = 1;
127 1.1 ragge nuda = 2;
128 1.1 ragge ubaaddr = uba630;
129 1.1 ragge udaaddr = uda630;
130 1.1 ragge uioaddr = uio630;
131 1.1 ragge tmsaddr = qbdev(0774500);
132 1.1 ragge break;
133 1.1 ragge
134 1.3 ragge case VAX_BTYP_8000:
135 1.1 ragge memsz = 0;
136 1.1 ragge nbi = 1;
137 1.1 ragge biaddr = bi8200;
138 1.1 ragge bioaddr = bio8200;
139 1.5 ragge break;
140 1.1 ragge
141 1.3 ragge case VAX_BTYP_46:
142 1.3 ragge case VAX_BTYP_48:
143 1.3 ragge {int *map, i;
144 1.3 ragge
145 1.3 ragge /* Map all 16MB of I/O space to low 16MB of memory */
146 1.3 ragge map = (int *)0x700000; /* XXX */
147 1.3 ragge *(int *)0x20080008 = (int)map; /* XXX */
148 1.3 ragge for (i = 0; i < 0x8000; i++)
149 1.3 ragge map[i] = 0x80000000 | i;
150 1.3 ragge }break;
151 1.3 ragge
152 1.3 ragge case VAX_BTYP_410:
153 1.3 ragge case VAX_BTYP_420:
154 1.3 ragge case VAX_BTYP_43:
155 1.5 ragge case VAX_BTYP_49:
156 1.5 ragge break;
157 1.1 ragge }
158 1.1 ragge }
159 1.1 ragge
160 1.1 ragge /*
161 1.1 ragge * Clock handling routines, needed to do timing in standalone programs.
162 1.1 ragge */
163 1.3 ragge
164 1.3 ragge volatile int tickcnt;
165 1.1 ragge
166 1.1 ragge getsecs()
167 1.1 ragge {
168 1.1 ragge volatile int loop;
169 1.1 ragge int todr;
170 1.1 ragge
171 1.3 ragge return tickcnt/100;
172 1.3 ragge }
173 1.3 ragge
174 1.5 ragge void scb_stray(), rtimer();
175 1.5 ragge struct ivec_dsp **scb;
176 1.5 ragge struct ivec_dsp *scb_vec;
177 1.3 ragge
178 1.5 ragge /*
179 1.5 ragge * Init the SCB and set up a handler for all vectors in the lower space,
180 1.5 ragge * to detect unwanted interrupts.
181 1.5 ragge */
182 1.3 ragge scbinit()
183 1.3 ragge {
184 1.3 ragge extern int timer;
185 1.3 ragge int i;
186 1.3 ragge
187 1.5 ragge /*
188 1.5 ragge * Allocate space. We need one page for the SCB, and 128*16 == 2k
189 1.5 ragge * for the vectors. The SCB must be on a page boundary.
190 1.5 ragge */
191 1.5 ragge i = alloc(VAX_NBPG * 6) + VAX_PGOFSET;
192 1.3 ragge i &= ~VAX_PGOFSET;
193 1.3 ragge
194 1.3 ragge mtpr(i, PR_SCBB);
195 1.5 ragge scb = (void *)i;
196 1.5 ragge scb_vec = (struct ivec_dsp *)(i + VAX_NBPG);
197 1.3 ragge
198 1.5 ragge for (i = 0; i < 128; i++) {
199 1.5 ragge scb[i] = &scb_vec[i];
200 1.5 ragge (int)scb[i] |= 1; /* Only interrupt stack */
201 1.5 ragge memcpy(&scb_vec[i], &idsptch, sizeof(struct ivec_dsp));
202 1.5 ragge scb_vec[i].hoppaddr = scb_stray;
203 1.5 ragge }
204 1.5 ragge scb_vec[0xc0/4].hoppaddr = rtimer;
205 1.3 ragge
206 1.3 ragge mtpr(-10000, PR_NICR); /* Load in count register */
207 1.3 ragge mtpr(0x800000d1, PR_ICCS); /* Start clock and enable interrupt */
208 1.3 ragge
209 1.5 ragge mtpr(20, PR_IPL);
210 1.5 ragge }
211 1.5 ragge
212 1.5 ragge void
213 1.5 ragge rtimer()
214 1.5 ragge {
215 1.5 ragge mtpr(31, PR_IPL);
216 1.5 ragge tickcnt++;
217 1.5 ragge mtpr(0xc1, PR_ICCS);
218 1.3 ragge }
219 1.1 ragge
220 1.3 ragge asm("
221 1.5 ragge .globl _idsptch, _eidsptch
222 1.5 ragge _idsptch:
223 1.5 ragge pushr $0x3f
224 1.5 ragge pushl $1
225 1.5 ragge .long 0x9f01fb01
226 1.5 ragge .long 0x12345678
227 1.5 ragge #
228 1.5 ragge # gas do not accept this :-/ use hexcode instead
229 1.5 ragge # nop
230 1.5 ragge # calls $1, *$0x12345678
231 1.5 ragge popr $0x3f
232 1.3 ragge rei
233 1.5 ragge _eidsptch:
234 1.3 ragge ");
235 1.5 ragge
236 1.5 ragge /*
237 1.5 ragge * Stray interrupt handler.
238 1.5 ragge * This function must _not_ save any registers (in the reg save mask).
239 1.5 ragge */
240 1.5 ragge void
241 1.5 ragge scb_stray(arg)
242 1.5 ragge int arg;
243 1.5 ragge {
244 1.5 ragge static struct callsframe *cf;
245 1.5 ragge static int vector, ipl, *a;
246 1.5 ragge
247 1.5 ragge cf = FRAMEOFFSET(arg);
248 1.5 ragge a = &cf->ca_arg1;
249 1.5 ragge ipl = mfpr(PR_IPL);
250 1.5 ragge vector = ((cf->ca_pc - (u_int)scb_vec)/4) & ~3;
251 1.5 ragge printf("stray interrupt: pc %x vector 0x%x, ipl %d\n",
252 1.5 ragge cf->ca_pc, vector, ipl);
253 1.5 ragge }
254 1.5 ragge
255