if_le_vsbus.c revision 1.7 1 1.7 matt /* $NetBSD: if_le_vsbus.c,v 1.7 2000/06/04 02:19:25 matt Exp $ */
2 1.1 ragge
3 1.1 ragge /*-
4 1.1 ragge * Copyright (c) 1998 The NetBSD Foundation, Inc.
5 1.1 ragge * All rights reserved.
6 1.1 ragge *
7 1.1 ragge * This code is derived from software contributed to The NetBSD Foundation
8 1.1 ragge * by Charles M. Hannum.
9 1.1 ragge *
10 1.1 ragge * Redistribution and use in source and binary forms, with or without
11 1.1 ragge * modification, are permitted provided that the following conditions
12 1.1 ragge * are met:
13 1.1 ragge * 1. Redistributions of source code must retain the above copyright
14 1.1 ragge * notice, this list of conditions and the following disclaimer.
15 1.1 ragge * 2. Redistributions in binary form must reproduce the above copyright
16 1.1 ragge * notice, this list of conditions and the following disclaimer in the
17 1.1 ragge * documentation and/or other materials provided with the distribution.
18 1.1 ragge * 3. All advertising materials mentioning features or use of this software
19 1.1 ragge * must display the following acknowledgement:
20 1.1 ragge * This product includes software developed by the NetBSD
21 1.1 ragge * Foundation, Inc. and its contributors.
22 1.1 ragge * 4. Neither the name of The NetBSD Foundation nor the names of its
23 1.1 ragge * contributors may be used to endorse or promote products derived
24 1.1 ragge * from this software without specific prior written permission.
25 1.1 ragge *
26 1.1 ragge * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
27 1.1 ragge * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
28 1.1 ragge * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
29 1.1 ragge * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
30 1.1 ragge * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
31 1.1 ragge * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
32 1.1 ragge * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
33 1.1 ragge * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
34 1.1 ragge * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
35 1.1 ragge * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
36 1.1 ragge * POSSIBILITY OF SUCH DAMAGE.
37 1.1 ragge */
38 1.1 ragge
39 1.1 ragge /*-
40 1.1 ragge * Copyright (c) 1992, 1993
41 1.1 ragge * The Regents of the University of California. All rights reserved.
42 1.1 ragge *
43 1.1 ragge * This code is derived from software contributed to Berkeley by
44 1.1 ragge * Ralph Campbell and Rick Macklem.
45 1.1 ragge *
46 1.1 ragge * Redistribution and use in source and binary forms, with or without
47 1.1 ragge * modification, are permitted provided that the following conditions
48 1.1 ragge * are met:
49 1.1 ragge * 1. Redistributions of source code must retain the above copyright
50 1.1 ragge * notice, this list of conditions and the following disclaimer.
51 1.1 ragge * 2. Redistributions in binary form must reproduce the above copyright
52 1.1 ragge * notice, this list of conditions and the following disclaimer in the
53 1.1 ragge * documentation and/or other materials provided with the distribution.
54 1.1 ragge * 3. All advertising materials mentioning features or use of this software
55 1.1 ragge * must display the following acknowledgement:
56 1.1 ragge * This product includes software developed by the University of
57 1.1 ragge * California, Berkeley and its contributors.
58 1.1 ragge * 4. Neither the name of the University nor the names of its contributors
59 1.1 ragge * may be used to endorse or promote products derived from this software
60 1.1 ragge * without specific prior written permission.
61 1.1 ragge *
62 1.1 ragge * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
63 1.1 ragge * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
64 1.1 ragge * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
65 1.1 ragge * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
66 1.1 ragge * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
67 1.1 ragge * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
68 1.1 ragge * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
69 1.1 ragge * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
70 1.1 ragge * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
71 1.1 ragge * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
72 1.1 ragge * SUCH DAMAGE.
73 1.1 ragge *
74 1.1 ragge * @(#)if_le.c 8.2 (Berkeley) 11/16/93
75 1.1 ragge */
76 1.1 ragge
77 1.1 ragge #include "opt_inet.h"
78 1.1 ragge #include "bpfilter.h"
79 1.1 ragge
80 1.1 ragge #include <sys/param.h>
81 1.1 ragge #include <sys/syslog.h>
82 1.1 ragge #include <sys/socket.h>
83 1.1 ragge #include <sys/device.h>
84 1.1 ragge #include <sys/reboot.h>
85 1.1 ragge
86 1.1 ragge #include <vm/vm.h>
87 1.1 ragge #include <vm/vm_kern.h>
88 1.1 ragge
89 1.1 ragge #include <net/if.h>
90 1.1 ragge #include <net/if_ether.h>
91 1.1 ragge #include <net/if_media.h>
92 1.1 ragge
93 1.1 ragge #if INET
94 1.1 ragge #include <netinet/in.h>
95 1.1 ragge #include <netinet/if_inarp.h>
96 1.1 ragge #endif
97 1.1 ragge
98 1.1 ragge #include <machine/cpu.h>
99 1.2 ragge #include <machine/sid.h>
100 1.3 matt #include <machine/scb.h>
101 1.1 ragge #include <machine/bus.h>
102 1.1 ragge #include <machine/vsbus.h>
103 1.1 ragge
104 1.1 ragge #include <dev/ic/lancereg.h>
105 1.1 ragge #include <dev/ic/lancevar.h>
106 1.1 ragge #include <dev/ic/am7990reg.h>
107 1.1 ragge #include <dev/ic/am7990var.h>
108 1.1 ragge
109 1.1 ragge #include "ioconf.h"
110 1.1 ragge
111 1.1 ragge struct le_softc {
112 1.1 ragge struct am7990_softc sc_am7990; /* Must be first */
113 1.7 matt struct evcnt sc_intrcnt;
114 1.4 matt bus_dmamap_t sc_dm;
115 1.1 ragge volatile u_short *sc_rap;
116 1.1 ragge volatile u_short *sc_rdp;
117 1.1 ragge };
118 1.1 ragge
119 1.4 matt static int le_vsbus_match __P((struct device *, struct cfdata *, void *));
120 1.4 matt static void le_vsbus_attach __P((struct device *, struct device *, void *));
121 1.1 ragge static void lewrcsr __P((struct lance_softc *, u_int16_t, u_int16_t));
122 1.1 ragge static u_int16_t lerdcsr __P((struct lance_softc *, u_int16_t));
123 1.1 ragge
124 1.1 ragge struct cfattach le_vsbus_ca = {
125 1.1 ragge sizeof(struct le_softc), le_vsbus_match, le_vsbus_attach
126 1.1 ragge };
127 1.1 ragge
128 1.4 matt static void
129 1.1 ragge lewrcsr(ls, port, val)
130 1.1 ragge struct lance_softc *ls;
131 1.1 ragge u_int16_t port, val;
132 1.1 ragge {
133 1.1 ragge struct le_softc *sc = (void *)ls;
134 1.1 ragge
135 1.1 ragge *sc->sc_rap = port;
136 1.1 ragge *sc->sc_rdp = val;
137 1.1 ragge }
138 1.1 ragge
139 1.4 matt static u_int16_t
140 1.1 ragge lerdcsr(ls, port)
141 1.1 ragge struct lance_softc *ls;
142 1.1 ragge u_int16_t port;
143 1.1 ragge {
144 1.1 ragge struct le_softc *sc = (void *)ls;
145 1.1 ragge
146 1.1 ragge *sc->sc_rap = port;
147 1.1 ragge return *sc->sc_rdp;
148 1.1 ragge }
149 1.1 ragge
150 1.4 matt static int
151 1.1 ragge le_vsbus_match(parent, cf, aux)
152 1.1 ragge struct device *parent;
153 1.1 ragge struct cfdata *cf;
154 1.1 ragge void *aux;
155 1.1 ragge {
156 1.4 matt struct vsbus_attach_args *va = aux;
157 1.1 ragge volatile short *rdp, *rap;
158 1.4 matt struct leinit initblock;
159 1.4 matt bus_dmamap_t map;
160 1.4 matt int i;
161 1.4 matt int rv = 0;
162 1.4 matt int error;
163 1.1 ragge
164 1.2 ragge if (vax_boardtype == VAX_BTYP_49)
165 1.2 ragge return 0;
166 1.4 matt
167 1.4 matt error = bus_dmamap_create(va->va_dmat, sizeof(initblock), 1,
168 1.5 ragge sizeof(initblock), 0, BUS_DMA_NOWAIT, &map);
169 1.4 matt if (error) {
170 1.4 matt return 0;
171 1.4 matt }
172 1.4 matt
173 1.4 matt error = bus_dmamap_load(va->va_dmat, map, &initblock,
174 1.4 matt sizeof(initblock), NULL, BUS_DMA_NOWAIT|BUS_DMA_COHERENT);
175 1.4 matt if (error) {
176 1.4 matt bus_dmamap_destroy(va->va_dmat, map);
177 1.4 matt return 0;
178 1.4 matt }
179 1.4 matt
180 1.4 matt memset(&initblock, 0, sizeof(initblock));
181 1.4 matt
182 1.1 ragge rdp = (short *)va->va_addr;
183 1.1 ragge rap = rdp + 2;
184 1.1 ragge
185 1.1 ragge /* Make sure the chip is stopped. */
186 1.1 ragge *rap = LE_CSR0;
187 1.1 ragge *rdp = LE_C0_STOP;
188 1.1 ragge DELAY(100);
189 1.4 matt *rap = LE_CSR1;
190 1.4 matt *rdp = map->dm_segs->ds_addr & 0xffff;
191 1.4 matt *rap = LE_CSR2;
192 1.4 matt *rdp = (map->dm_segs->ds_addr >> 16) & 0xffff;
193 1.4 matt *rap = LE_CSR0;
194 1.1 ragge *rdp = LE_C0_INIT|LE_C0_INEA;
195 1.1 ragge
196 1.1 ragge /* Wait for initialization to finish. */
197 1.4 matt for (i = 100; i >= 0; i--) {
198 1.4 matt DELAY(1000);
199 1.4 matt /* Should have interrupted by now */
200 1.4 matt if (*rdp & LE_C0_IDON)
201 1.4 matt rv = 1;
202 1.4 matt }
203 1.4 matt *rap = LE_CSR0;
204 1.4 matt *rdp = LE_C0_STOP;
205 1.1 ragge
206 1.4 matt bus_dmamap_unload(va->va_dmat, map);
207 1.4 matt bus_dmamap_destroy(va->va_dmat, map);
208 1.4 matt return rv;
209 1.1 ragge }
210 1.1 ragge
211 1.4 matt static void
212 1.1 ragge le_vsbus_attach(parent, self, aux)
213 1.1 ragge struct device *parent, *self;
214 1.1 ragge void *aux;
215 1.1 ragge {
216 1.4 matt struct vsbus_attach_args *va = aux;
217 1.1 ragge struct le_softc *sc = (void *)self;
218 1.1 ragge bus_dma_segment_t seg;
219 1.1 ragge int *lance_addr;
220 1.1 ragge int i, err, rseg;
221 1.1 ragge
222 1.1 ragge sc->sc_rdp = (short *)vax_map_physmem(NI_BASE, 1);
223 1.1 ragge sc->sc_rap = sc->sc_rdp + 2;
224 1.1 ragge
225 1.1 ragge /*
226 1.1 ragge * MD functions.
227 1.1 ragge */
228 1.1 ragge sc->sc_am7990.lsc.sc_rdcsr = lerdcsr;
229 1.1 ragge sc->sc_am7990.lsc.sc_wrcsr = lewrcsr;
230 1.1 ragge sc->sc_am7990.lsc.sc_nocarrier = NULL;
231 1.1 ragge
232 1.7 matt scb_vecalloc(va->va_cvec, (void (*)(void *)) am7990_intr, sc,
233 1.7 matt SCB_ISTACK, &sc->sc_intrcnt);
234 1.7 matt evcnt_attach(self, "intr", &sc->sc_intrcnt);
235 1.7 matt
236 1.1 ragge /*
237 1.1 ragge * Allocate a (DMA-safe) block for all descriptors and buffers.
238 1.1 ragge */
239 1.1 ragge
240 1.1 ragge #define ALLOCSIZ (64 * 1024)
241 1.1 ragge err = bus_dmamem_alloc(va->va_dmat, ALLOCSIZ, NBPG, 0,
242 1.1 ragge &seg, 1, &rseg, BUS_DMA_NOWAIT);
243 1.1 ragge if (err) {
244 1.1 ragge printf(": unable to alloc buffer block: err %d\n", err);
245 1.1 ragge return;
246 1.1 ragge }
247 1.1 ragge err = bus_dmamem_map(va->va_dmat, &seg, rseg, ALLOCSIZ,
248 1.1 ragge (caddr_t *)&sc->sc_am7990.lsc.sc_mem,
249 1.1 ragge BUS_DMA_NOWAIT|BUS_DMA_COHERENT);
250 1.1 ragge if (err) {
251 1.1 ragge printf(": unable to map buffer block: err %d\n", err);
252 1.1 ragge bus_dmamem_free(va->va_dmat, &seg, rseg);
253 1.1 ragge return;
254 1.1 ragge }
255 1.4 matt err = bus_dmamap_create(va->va_dmat, ALLOCSIZ, rseg, ALLOCSIZ,
256 1.4 matt 0, BUS_DMA_NOWAIT, &sc->sc_dm);
257 1.4 matt if (err) {
258 1.4 matt printf(": unable to create dma map: err %d\n", err);
259 1.4 matt bus_dmamem_free(va->va_dmat, &seg, rseg);
260 1.4 matt return;
261 1.4 matt }
262 1.4 matt err = bus_dmamap_load(va->va_dmat, sc->sc_dm, sc->sc_am7990.lsc.sc_mem,
263 1.4 matt ALLOCSIZ, NULL, BUS_DMA_NOWAIT);
264 1.4 matt if (err) {
265 1.4 matt printf(": unable to load dma map: err %d\n", err);
266 1.4 matt bus_dmamap_destroy(va->va_dmat, sc->sc_dm);
267 1.4 matt bus_dmamem_free(va->va_dmat, &seg, rseg);
268 1.4 matt return;
269 1.4 matt }
270 1.4 matt printf(" buf 0x%lx-0x%lx", sc->sc_dm->dm_segs->ds_addr,
271 1.4 matt sc->sc_dm->dm_segs->ds_addr + sc->sc_dm->dm_segs->ds_len - 1);
272 1.4 matt sc->sc_am7990.lsc.sc_addr = sc->sc_dm->dm_segs->ds_addr & 0xffffff;
273 1.4 matt sc->sc_am7990.lsc.sc_memsize = sc->sc_dm->dm_segs->ds_len;
274 1.1 ragge
275 1.1 ragge sc->sc_am7990.lsc.sc_copytodesc = lance_copytobuf_contig;
276 1.1 ragge sc->sc_am7990.lsc.sc_copyfromdesc = lance_copyfrombuf_contig;
277 1.1 ragge sc->sc_am7990.lsc.sc_copytobuf = lance_copytobuf_contig;
278 1.1 ragge sc->sc_am7990.lsc.sc_copyfrombuf = lance_copyfrombuf_contig;
279 1.1 ragge sc->sc_am7990.lsc.sc_zerobuf = lance_zerobuf_contig;
280 1.1 ragge
281 1.4 matt #ifdef LEDEBUG
282 1.4 matt sc->sc_am7990.lsc.sc_debug = 1;
283 1.4 matt #endif
284 1.1 ragge /*
285 1.1 ragge * Get the ethernet address out of rom
286 1.1 ragge */
287 1.1 ragge lance_addr = (int *)vax_map_physmem(NI_ADDR, 1);
288 1.1 ragge for (i = 0; i < 6; i++)
289 1.1 ragge sc->sc_am7990.lsc.sc_enaddr[i] = (u_char)lance_addr[i];
290 1.1 ragge vax_unmap_physmem((vaddr_t)lance_addr, 1);
291 1.1 ragge
292 1.1 ragge bcopy(self->dv_xname, sc->sc_am7990.lsc.sc_ethercom.ec_if.if_xname,
293 1.1 ragge IFNAMSIZ);
294 1.4 matt /* Prettier printout */
295 1.4 matt printf("\n%s", self->dv_xname);
296 1.4 matt
297 1.1 ragge am7990_config(&sc->sc_am7990);
298 1.1 ragge }
299