if_le_vsbus.c revision 1.6.2.1
1 /* $NetBSD: if_le_vsbus.c,v 1.6.2.1 2000/06/22 17:05:02 minoura Exp $ */ 2 3 /*- 4 * Copyright (c) 1998 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Charles M. Hannum. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 /*- 40 * Copyright (c) 1992, 1993 41 * The Regents of the University of California. All rights reserved. 42 * 43 * This code is derived from software contributed to Berkeley by 44 * Ralph Campbell and Rick Macklem. 45 * 46 * Redistribution and use in source and binary forms, with or without 47 * modification, are permitted provided that the following conditions 48 * are met: 49 * 1. Redistributions of source code must retain the above copyright 50 * notice, this list of conditions and the following disclaimer. 51 * 2. Redistributions in binary form must reproduce the above copyright 52 * notice, this list of conditions and the following disclaimer in the 53 * documentation and/or other materials provided with the distribution. 54 * 3. All advertising materials mentioning features or use of this software 55 * must display the following acknowledgement: 56 * This product includes software developed by the University of 57 * California, Berkeley and its contributors. 58 * 4. Neither the name of the University nor the names of its contributors 59 * may be used to endorse or promote products derived from this software 60 * without specific prior written permission. 61 * 62 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 63 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 64 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 65 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 66 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 67 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 68 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 69 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 70 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 71 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 72 * SUCH DAMAGE. 73 * 74 * @(#)if_le.c 8.2 (Berkeley) 11/16/93 75 */ 76 77 #include "opt_inet.h" 78 #include "bpfilter.h" 79 80 #include <sys/param.h> 81 #include <sys/syslog.h> 82 #include <sys/socket.h> 83 #include <sys/device.h> 84 #include <sys/reboot.h> 85 86 #include <vm/vm.h> 87 #include <vm/vm_kern.h> 88 89 #include <net/if.h> 90 #include <net/if_ether.h> 91 #include <net/if_media.h> 92 93 #if INET 94 #include <netinet/in.h> 95 #include <netinet/if_inarp.h> 96 #endif 97 98 #include <machine/cpu.h> 99 #include <machine/sid.h> 100 #include <machine/scb.h> 101 #include <machine/bus.h> 102 #include <machine/vsbus.h> 103 104 #include <dev/ic/lancereg.h> 105 #include <dev/ic/lancevar.h> 106 #include <dev/ic/am7990reg.h> 107 #include <dev/ic/am7990var.h> 108 109 #include "ioconf.h" 110 111 struct le_softc { 112 struct am7990_softc sc_am7990; /* Must be first */ 113 struct evcnt sc_intrcnt; 114 bus_dmamap_t sc_dm; 115 volatile u_short *sc_rap; 116 volatile u_short *sc_rdp; 117 }; 118 119 static int le_vsbus_match __P((struct device *, struct cfdata *, void *)); 120 static void le_vsbus_attach __P((struct device *, struct device *, void *)); 121 static void lewrcsr __P((struct lance_softc *, u_int16_t, u_int16_t)); 122 static u_int16_t lerdcsr __P((struct lance_softc *, u_int16_t)); 123 124 struct cfattach le_vsbus_ca = { 125 sizeof(struct le_softc), le_vsbus_match, le_vsbus_attach 126 }; 127 128 static void 129 lewrcsr(ls, port, val) 130 struct lance_softc *ls; 131 u_int16_t port, val; 132 { 133 struct le_softc *sc = (void *)ls; 134 135 *sc->sc_rap = port; 136 *sc->sc_rdp = val; 137 } 138 139 static u_int16_t 140 lerdcsr(ls, port) 141 struct lance_softc *ls; 142 u_int16_t port; 143 { 144 struct le_softc *sc = (void *)ls; 145 146 *sc->sc_rap = port; 147 return *sc->sc_rdp; 148 } 149 150 static int 151 le_vsbus_match(parent, cf, aux) 152 struct device *parent; 153 struct cfdata *cf; 154 void *aux; 155 { 156 struct vsbus_attach_args *va = aux; 157 volatile short *rdp, *rap; 158 struct leinit initblock; 159 bus_dmamap_t map; 160 int i; 161 int rv = 0; 162 int error; 163 164 if (vax_boardtype == VAX_BTYP_49) 165 return 0; 166 167 error = bus_dmamap_create(va->va_dmat, sizeof(initblock), 1, 168 sizeof(initblock), 0, BUS_DMA_NOWAIT, &map); 169 if (error) { 170 return 0; 171 } 172 173 error = bus_dmamap_load(va->va_dmat, map, &initblock, 174 sizeof(initblock), NULL, BUS_DMA_NOWAIT|BUS_DMA_COHERENT); 175 if (error) { 176 bus_dmamap_destroy(va->va_dmat, map); 177 return 0; 178 } 179 180 memset(&initblock, 0, sizeof(initblock)); 181 182 rdp = (short *)va->va_addr; 183 rap = rdp + 2; 184 185 /* Make sure the chip is stopped. */ 186 *rap = LE_CSR0; 187 *rdp = LE_C0_STOP; 188 DELAY(100); 189 *rap = LE_CSR1; 190 *rdp = map->dm_segs->ds_addr & 0xffff; 191 *rap = LE_CSR2; 192 *rdp = (map->dm_segs->ds_addr >> 16) & 0xffff; 193 *rap = LE_CSR0; 194 *rdp = LE_C0_INIT|LE_C0_INEA; 195 196 /* Wait for initialization to finish. */ 197 for (i = 100; i >= 0; i--) { 198 DELAY(1000); 199 /* Should have interrupted by now */ 200 if (*rdp & LE_C0_IDON) 201 rv = 1; 202 } 203 *rap = LE_CSR0; 204 *rdp = LE_C0_STOP; 205 206 bus_dmamap_unload(va->va_dmat, map); 207 bus_dmamap_destroy(va->va_dmat, map); 208 return rv; 209 } 210 211 static void 212 le_vsbus_attach(parent, self, aux) 213 struct device *parent, *self; 214 void *aux; 215 { 216 struct vsbus_attach_args *va = aux; 217 struct le_softc *sc = (void *)self; 218 bus_dma_segment_t seg; 219 int *lance_addr; 220 int i, err, rseg; 221 222 sc->sc_rdp = (short *)vax_map_physmem(NI_BASE, 1); 223 sc->sc_rap = sc->sc_rdp + 2; 224 225 /* 226 * MD functions. 227 */ 228 sc->sc_am7990.lsc.sc_rdcsr = lerdcsr; 229 sc->sc_am7990.lsc.sc_wrcsr = lewrcsr; 230 sc->sc_am7990.lsc.sc_nocarrier = NULL; 231 232 scb_vecalloc(va->va_cvec, (void (*)(void *)) am7990_intr, sc, 233 SCB_ISTACK, &sc->sc_intrcnt); 234 evcnt_attach_dynamic(&sc->sc_intrcnt, EVCNT_TYPE_INTR, NULL, 235 self->dv_xname, "intr"); 236 237 /* 238 * Allocate a (DMA-safe) block for all descriptors and buffers. 239 */ 240 241 #define ALLOCSIZ (64 * 1024) 242 err = bus_dmamem_alloc(va->va_dmat, ALLOCSIZ, NBPG, 0, 243 &seg, 1, &rseg, BUS_DMA_NOWAIT); 244 if (err) { 245 printf(": unable to alloc buffer block: err %d\n", err); 246 return; 247 } 248 err = bus_dmamem_map(va->va_dmat, &seg, rseg, ALLOCSIZ, 249 (caddr_t *)&sc->sc_am7990.lsc.sc_mem, 250 BUS_DMA_NOWAIT|BUS_DMA_COHERENT); 251 if (err) { 252 printf(": unable to map buffer block: err %d\n", err); 253 bus_dmamem_free(va->va_dmat, &seg, rseg); 254 return; 255 } 256 err = bus_dmamap_create(va->va_dmat, ALLOCSIZ, rseg, ALLOCSIZ, 257 0, BUS_DMA_NOWAIT, &sc->sc_dm); 258 if (err) { 259 printf(": unable to create dma map: err %d\n", err); 260 bus_dmamem_free(va->va_dmat, &seg, rseg); 261 return; 262 } 263 err = bus_dmamap_load(va->va_dmat, sc->sc_dm, sc->sc_am7990.lsc.sc_mem, 264 ALLOCSIZ, NULL, BUS_DMA_NOWAIT); 265 if (err) { 266 printf(": unable to load dma map: err %d\n", err); 267 bus_dmamap_destroy(va->va_dmat, sc->sc_dm); 268 bus_dmamem_free(va->va_dmat, &seg, rseg); 269 return; 270 } 271 printf(" buf 0x%lx-0x%lx", sc->sc_dm->dm_segs->ds_addr, 272 sc->sc_dm->dm_segs->ds_addr + sc->sc_dm->dm_segs->ds_len - 1); 273 sc->sc_am7990.lsc.sc_addr = sc->sc_dm->dm_segs->ds_addr & 0xffffff; 274 sc->sc_am7990.lsc.sc_memsize = sc->sc_dm->dm_segs->ds_len; 275 276 sc->sc_am7990.lsc.sc_copytodesc = lance_copytobuf_contig; 277 sc->sc_am7990.lsc.sc_copyfromdesc = lance_copyfrombuf_contig; 278 sc->sc_am7990.lsc.sc_copytobuf = lance_copytobuf_contig; 279 sc->sc_am7990.lsc.sc_copyfrombuf = lance_copyfrombuf_contig; 280 sc->sc_am7990.lsc.sc_zerobuf = lance_zerobuf_contig; 281 282 #ifdef LEDEBUG 283 sc->sc_am7990.lsc.sc_debug = 1; 284 #endif 285 /* 286 * Get the ethernet address out of rom 287 */ 288 lance_addr = (int *)vax_map_physmem(NI_ADDR, 1); 289 for (i = 0; i < 6; i++) 290 sc->sc_am7990.lsc.sc_enaddr[i] = (u_char)lance_addr[i]; 291 vax_unmap_physmem((vaddr_t)lance_addr, 1); 292 293 bcopy(self->dv_xname, sc->sc_am7990.lsc.sc_ethercom.ec_if.if_xname, 294 IFNAMSIZ); 295 /* Prettier printout */ 296 printf("\n%s", self->dv_xname); 297 298 am7990_config(&sc->sc_am7990); 299 } 300
Indexes created Mon Oct 20 16:09:52 GMT 2025