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intr.h revision 1.10.2.1
      1  1.10.2.1  nathanw /* 	$NetBSD: intr.h,v 1.10.2.1 2001/06/21 19:38:12 nathanw Exp $	*/
      2       1.1     matt 
      3       1.1     matt /*
      4       1.1     matt  * Copyright (c) 1998 Matt Thomas.
      5       1.1     matt  * All rights reserved.
      6       1.1     matt  *
      7       1.1     matt  * Redistribution and use in source and binary forms, with or without
      8       1.1     matt  * modification, are permitted provided that the following conditions
      9       1.1     matt  * are met:
     10       1.1     matt  * 1. Redistributions of source code must retain the above copyright
     11       1.1     matt  *    notice, this list of conditions and the following disclaimer.
     12       1.1     matt  * 2. Redistributions in binary form must reproduce the above copyright
     13       1.1     matt  *    notice, this list of conditions and the following disclaimer in the
     14       1.1     matt  *    documentation and/or other materials provided with the distribution.
     15       1.1     matt  * 3. The name of the company nor the name of the author may be used to
     16       1.1     matt  *    endorse or promote products derived from this software without specific
     17       1.1     matt  *    prior written permission.
     18       1.1     matt  *
     19       1.1     matt  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
     20       1.1     matt  * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
     21       1.1     matt  * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
     22       1.1     matt  * IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
     23       1.1     matt  * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
     24       1.1     matt  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
     25       1.1     matt  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
     26       1.1     matt  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
     27       1.1     matt  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
     28       1.1     matt  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
     29       1.1     matt  * SUCH DAMAGE.
     30       1.1     matt  */
     31       1.1     matt 
     32       1.1     matt #ifndef _VAX_INTR_H_
     33       1.1     matt #define _VAX_INTR_H_
     34       1.1     matt 
     35       1.2     matt #include <sys/queue.h>
     36       1.2     matt 
     37       1.1     matt /* Define the various Interrupt Priority Levels */
     38       1.1     matt 
     39       1.1     matt /* Interrupt Priority Levels are not mutually exclusive. */
     40       1.1     matt 
     41       1.2     matt /* Hardware interrupt levels are 16 (0x10) thru 31 (0x1f)
     42       1.2     matt  */
     43       1.2     matt #define IPL_HIGH	0x1f	/* high -- blocks all interrupts */
     44       1.2     matt #define IPL_CLOCK	0x18	/* clock */
     45       1.2     matt #define IPL_UBA		0x17	/* unibus adapters */
     46       1.2     matt #define IPL_IMP		0x17	/* memory allocation */
     47  1.10.2.1  nathanw #define IPL_NET		0x16	/* network */
     48       1.2     matt #define IPL_BIO		0x15	/* block I/O */
     49       1.2     matt #define IPL_TTY		0x15	/* terminal */
     50       1.2     matt #define IPL_AUDIO	0x15	/* audio */
     51  1.10.2.1  nathanw #define IPL_IPI		0x14	/* interprocessor interrupt */
     52       1.2     matt #define IPL_CONSMEDIA	0x14	/* console media */
     53       1.1     matt 
     54       1.2     matt /* Software interrupt level s are 0 (0x00) thru 15 (0x0f)
     55       1.2     matt  */
     56       1.2     matt #define IPL_SOFTDDB	0x0f	/* used by DDB on VAX */
     57       1.2     matt #define IPL_SOFTSERIAL	0x0d	/* soft serial */
     58       1.2     matt #define IPL_SOFTNET	0x0c	/* soft network */
     59       1.2     matt #define IPL_SOFTCLOCK	0x08
     60       1.2     matt #define IPL_NONE	0x00
     61       1.2     matt 
     62       1.2     matt #define IPL_LEVELS	32
     63       1.2     matt 
     64       1.2     matt #define IST_UNUSABLE	-1	/* interrupt cannot be used */
     65       1.2     matt #define IST_NONE	0	/* none (dummy) */
     66       1.2     matt #define IST_PULSE	1	/* pulsed */
     67       1.2     matt #define IST_EDGE	2	/* edge-triggered */
     68       1.2     matt #define IST_LEVEL	3	/* level-triggered */
     69       1.2     matt 
     70       1.2     matt 
     71       1.2     matt #ifdef _KERNEL
     72       1.2     matt #ifndef lint
     73       1.2     matt #define splx(reg)						\
     74       1.2     matt ({								\
     75       1.2     matt 	register int val;					\
     76       1.2     matt 	__asm __volatile ("mfpr $0x12,%0;mtpr %1,$0x12"		\
     77       1.5     matt 				: "=&g" (val)			\
     78       1.2     matt 				: "g" (reg));			\
     79       1.2     matt 	val;							\
     80       1.2     matt })
     81       1.2     matt 
     82       1.4     matt #define _splset(reg)						\
     83       1.4     matt ((void)({							\
     84       1.4     matt 	__asm __volatile ("mtpr %0,$0x12"			\
     85       1.4     matt 				: 				\
     86       1.4     matt 				: "g" (reg));			\
     87       1.4     matt }))
     88       1.4     matt 
     89       1.2     matt #define _splraise(reg)						\
     90       1.2     matt ({								\
     91       1.2     matt 	register int val;					\
     92       1.2     matt 	__asm __volatile ("mfpr $0x12,%0"			\
     93       1.5     matt 				: "=&g" (val)			\
     94       1.2     matt 				: );				\
     95       1.2     matt 	if ((reg) > val) {					\
     96       1.4     matt 		_splset(reg);					\
     97       1.2     matt 	}							\
     98       1.2     matt 	val;							\
     99       1.2     matt })
    100       1.4     matt 
    101       1.2     matt #define _setsirr(reg)						\
    102       1.4     matt do {								\
    103       1.2     matt 	__asm __volatile ("mtpr %0,$0x14"			\
    104       1.2     matt 				:				\
    105       1.2     matt 				: "g" (reg));			\
    106       1.4     matt } while (0)
    107       1.2     matt #endif
    108       1.2     matt 
    109       1.4     matt #define spl0()		_splset(IPL_NONE)		/* IPL00 */
    110       1.4     matt #define spllowersoftclock() _splset(IPL_SOFTCLOCK)	/* IPL08 */
    111       1.2     matt #define splsoftclock()	_splraise(IPL_SOFTCLOCK)	/* IPL08 */
    112       1.2     matt #define splsoftnet()	_splraise(IPL_SOFTNET)		/* IPL0C */
    113       1.2     matt #define splsoftserial()	_splraise(IPL_SOFTSERIAL)	/* IPL0D */
    114       1.2     matt #define splddb()	_splraise(IPL_SOFTDDB)		/* IPL0F */
    115       1.2     matt #define splconsmedia()	_splraise(IPL_CONSMEDIA)	/* IPL14 */
    116  1.10.2.1  nathanw #define	splipi()	_splraise(IPL_IPI)		/* IPL14 */
    117       1.2     matt #define splbio()	_splraise(IPL_BIO)		/* IPL15 */
    118       1.2     matt #define spltty()	_splraise(IPL_TTY)		/* IPL15 */
    119  1.10.2.1  nathanw #define splnet()	_splraise(IPL_NET)		/* IPL16 */
    120       1.8  thorpej #define splvm()		_splraise(IPL_IMP)		/* IPL17 */
    121       1.2     matt #define splclock()	_splraise(IPL_CLOCK)		/* IPL18 */
    122       1.2     matt #define splhigh()	_splraise(IPL_HIGH)		/* IPL1F */
    123       1.2     matt #define splstatclock()	splclock()
    124       1.6  thorpej 
    125       1.6  thorpej #define	splsched()	splhigh()
    126       1.7  thorpej #define	spllock()	splhigh()
    127       1.2     matt 
    128       1.2     matt /* These are better to use when playing with VAX buses */
    129  1.10.2.1  nathanw #define	spluba()	_splraise(IPL_UBA)		/* IPL17 */
    130       1.2     matt #define spl4()		splx(0x14)
    131       1.2     matt #define spl5()		splx(0x15)
    132       1.2     matt #define spl6()		splx(0x16)
    133       1.2     matt #define spl7()		splx(0x17)
    134       1.1     matt 
    135       1.2     matt /* schedule software interrupts
    136       1.2     matt  */
    137       1.2     matt #define setsoftddb()	_setsirr(IPL_SOFTDDB)
    138       1.2     matt #define setsoftserial()	_setsirr(IPL_SOFTSERIAL)
    139       1.2     matt #define setsoftnet()	_setsirr(IPL_SOFTNET)
    140       1.2     matt 
    141       1.2     matt #if !defined(_LOCORE)
    142       1.2     matt LIST_HEAD(sh_head, softintr_handler);
    143       1.2     matt 
    144       1.2     matt struct softintr_head {
    145       1.2     matt 	int shd_ipl;
    146       1.2     matt 	struct sh_head shd_intrs;
    147       1.2     matt };
    148       1.2     matt 
    149       1.2     matt struct softintr_handler {
    150       1.2     matt 	struct softintr_head *sh_head;
    151       1.2     matt 	LIST_ENTRY(softintr_handler) sh_link;
    152       1.2     matt 	void (*sh_func)(void *);
    153       1.2     matt 	void *sh_arg;
    154       1.2     matt 	int sh_pending;
    155       1.2     matt };
    156       1.2     matt 
    157       1.2     matt extern void *softintr_establish(int, void (*)(void *), void *);
    158       1.2     matt extern void softintr_disestablish(void *);
    159       1.2     matt 
    160       1.2     matt static __inline void
    161       1.2     matt softintr_schedule(void *arg)
    162       1.2     matt {
    163       1.2     matt 	struct softintr_handler * const sh = arg;
    164       1.2     matt 	sh->sh_pending = 1;
    165       1.2     matt 	_setsirr(sh->sh_head->shd_ipl);
    166       1.2     matt }
    167       1.2     matt #endif /* _LOCORE */
    168       1.2     matt #endif /* _KERNEL */
    169       1.1     matt #endif	/* _VAX_INTR_H */
    170