intr.h revision 1.2
1 /* $NetBSD: intr.h,v 1.2 2000/06/02 21:47:02 matt Exp $ */ 2 3 /* 4 * Copyright (c) 1998 Matt Thomas. 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. The name of the company nor the name of the author may be used to 16 * endorse or promote products derived from this software without specific 17 * prior written permission. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED 20 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 21 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 22 * IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, 23 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 24 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 25 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 26 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 27 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 28 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 29 * SUCH DAMAGE. 30 */ 31 32 #ifndef _VAX_INTR_H_ 33 #define _VAX_INTR_H_ 34 35 #include <sys/queue.h> 36 37 /* Define the various Interrupt Priority Levels */ 38 39 /* Interrupt Priority Levels are not mutually exclusive. */ 40 41 /* Hardware interrupt levels are 16 (0x10) thru 31 (0x1f) 42 */ 43 #define IPL_HIGH 0x1f /* high -- blocks all interrupts */ 44 #define IPL_CLOCK 0x18 /* clock */ 45 #define IPL_UBA 0x17 /* unibus adapters */ 46 #define IPL_IMP 0x17 /* memory allocation */ 47 #define IPL_BIO 0x15 /* block I/O */ 48 #define IPL_NET 0x15 /* network */ 49 #define IPL_TTY 0x15 /* terminal */ 50 #define IPL_AUDIO 0x15 /* audio */ 51 #define IPL_CONSMEDIA 0x14 /* console media */ 52 53 /* Software interrupt level s are 0 (0x00) thru 15 (0x0f) 54 */ 55 #define IPL_SOFTDDB 0x0f /* used by DDB on VAX */ 56 #define IPL_SOFTSERIAL 0x0d /* soft serial */ 57 #define IPL_SOFTNET 0x0c /* soft network */ 58 #define IPL_SOFTCLOCK 0x08 59 #define IPL_NONE 0x00 60 61 #define IPL_LEVELS 32 62 63 #define IST_UNUSABLE -1 /* interrupt cannot be used */ 64 #define IST_NONE 0 /* none (dummy) */ 65 #define IST_PULSE 1 /* pulsed */ 66 #define IST_EDGE 2 /* edge-triggered */ 67 #define IST_LEVEL 3 /* level-triggered */ 68 69 70 #ifdef _KERNEL 71 #ifndef lint 72 #define splx(reg) \ 73 ({ \ 74 register int val; \ 75 __asm __volatile ("mfpr $0x12,%0;mtpr %1,$0x12" \ 76 : "&=g" (val) \ 77 : "g" (reg)); \ 78 val; \ 79 }) 80 81 #define _splraise(reg) \ 82 ({ \ 83 register int val; \ 84 __asm __volatile ("mfpr $0x12,%0" \ 85 : "&=g" (val) \ 86 : ); \ 87 if ((reg) > val) { \ 88 __asm __volatile ("mtpr %0,$0x12" \ 89 : \ 90 : "g" (reg)); \ 91 } \ 92 val; \ 93 }) 94 #define _setsirr(reg) \ 95 ({ \ 96 __asm __volatile ("mtpr %0,$0x14" \ 97 : \ 98 : "g" (reg)); \ 99 }) 100 #endif 101 102 #define spl0() splx(IPL_NONE) /* IPL0 */ 103 #define spllowersoftclock() splx(IPL_SOFTCLOCK) /* IPL08 */ 104 #define splsoftclock() _splraise(IPL_SOFTCLOCK) /* IPL08 */ 105 #define splsoftnet() _splraise(IPL_SOFTNET) /* IPL0C */ 106 #define splsoftserial() _splraise(IPL_SOFTSERIAL) /* IPL0D */ 107 #define splddb() _splraise(IPL_SOFTDDB) /* IPL0F */ 108 #define splconsmedia() _splraise(IPL_CONSMEDIA) /* IPL14 */ 109 #define splbio() _splraise(IPL_BIO) /* IPL15 */ 110 #define splnet() _splraise(IPL_NET) /* IPL15 */ 111 #define spltty() _splraise(IPL_TTY) /* IPL15 */ 112 #define splimp() _splraise(IPL_IMP) /* IPL17 */ 113 #define splclock() _splraise(IPL_CLOCK) /* IPL18 */ 114 #define splhigh() _splraise(IPL_HIGH) /* IPL1F */ 115 #define splstatclock() splclock() 116 117 /* These are better to use when playing with VAX buses */ 118 #define spl4() splx(0x14) 119 #define spl5() splx(0x15) 120 #define spl6() splx(0x16) 121 #define spl7() splx(0x17) 122 123 /* schedule software interrupts 124 */ 125 #define setsoftddb() _setsirr(IPL_SOFTDDB) 126 #define setsoftserial() _setsirr(IPL_SOFTSERIAL) 127 #define setsoftnet() _setsirr(IPL_SOFTNET) 128 #define setsoftclock() _setsirr(IPL_SOFTCLOCK) 129 130 #define __GENERIC_SOFT_INTERRUPTS 131 132 #if !defined(_LOCORE) 133 LIST_HEAD(sh_head, softintr_handler); 134 135 struct softintr_head { 136 int shd_ipl; 137 struct sh_head shd_intrs; 138 }; 139 140 struct softintr_handler { 141 struct softintr_head *sh_head; 142 LIST_ENTRY(softintr_handler) sh_link; 143 void (*sh_func)(void *); 144 void *sh_arg; 145 int sh_pending; 146 }; 147 148 extern void *softintr_establish(int, void (*)(void *), void *); 149 extern void softintr_disestablish(void *); 150 151 static __inline void 152 softintr_schedule(void *arg) 153 { 154 struct softintr_handler * const sh = arg; 155 int s = _splraise(sh->sh_head->shd_ipl); /* movl @(r0), ... */ 156 sh->sh_pending = 1; 157 _setsirr(sh->sh_head->shd_ipl); 158 splx(s); 159 } 160 #endif /* _LOCORE */ 161 #endif /* _KERNEL */ 162 #endif /* _VAX_INTR_H */ 163
Indexes created Mon Sep 22 13:09:51 GMT 2025