intr.h revision 1.26 1 /* $NetBSD: intr.h,v 1.26 2008/02/03 08:32:25 matt Exp $ */
2
3 /*
4 * Copyright (c) 1998 Matt Thomas.
5 * All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 * 3. The name of the company nor the name of the author may be used to
16 * endorse or promote products derived from this software without specific
17 * prior written permission.
18 *
19 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
20 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
21 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
22 * IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
23 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
24 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
25 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
26 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
27 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
28 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
29 * SUCH DAMAGE.
30 */
31
32 #ifndef _VAX_INTR_H_
33 #define _VAX_INTR_H_
34
35 #include <sys/queue.h>
36 #include <machine/mtpr.h>
37
38 /* Define the various Interrupt Priority Levels */
39
40 /* Interrupt Priority Levels are not mutually exclusive. */
41
42 /* Hardware interrupt levels are 16 (0x10) thru 31 (0x1f)
43 */
44 #define IPL_HIGH 0x1f /* high -- blocks all interrupts */
45 #define IPL_SCHED 0x18 /* clock */
46 #define IPL_VM 0x17 /* memory allocation */
47
48 /* Software interrupt levels are 0 (0x00) thru 15 (0x0f)
49 */
50 #define IPL_SOFTDDB 0x0f /* used by DDB on VAX */
51 #define IPL_SOFTSERIAL 0x0d /* soft serial */
52 #define IPL_SOFTNET 0x0c /* soft network */
53 #define IPL_SOFTBIO 0x0b /* soft bio */
54 #define IPL_SOFTCLOCK 0x08
55 #define IPL_NONE 0x00
56
57 /* vax weirdness
58 */
59 #define IPL_UBA IPL_VM /* unibus adapters */
60 #define IPL_CONSMEDIA IPL_VM /* console media */
61
62 /* Misc
63 */
64
65 #define IPL_LEVELS 32
66
67 #define IST_UNUSABLE -1 /* interrupt cannot be used */
68 #define IST_NONE 0 /* none (dummy) */
69 #define IST_PULSE 1 /* pulsed */
70 #define IST_EDGE 2 /* edge-triggered */
71 #define IST_LEVEL 3 /* level-triggered */
72
73
74 #ifdef _KERNEL
75 typedef int ipl_t;
76
77 static inline void
78 _splset(ipl_t ipl)
79 {
80 mtpr(ipl, PR_IPL);
81 }
82
83 static inline ipl_t
84 _splget(void)
85 {
86 return mfpr(PR_IPL);
87 }
88
89 static inline ipl_t
90 splx(ipl_t new_ipl)
91 {
92 ipl_t old_ipl = _splget();
93 _splset(new_ipl);
94 return old_ipl;
95 }
96
97 typedef struct {
98 uint8_t _ipl;
99 } ipl_cookie_t;
100
101 static inline ipl_cookie_t
102 makeiplcookie(ipl_t ipl)
103 {
104 return (ipl_cookie_t){._ipl = (uint8_t)ipl};
105 }
106
107 static inline int
108 splraiseipl(ipl_cookie_t icookie)
109 {
110 ipl_t newipl = icookie._ipl;
111 ipl_t oldipl;
112
113 oldipl = _splget();
114 if (newipl > oldipl) {
115 _splset(newipl);
116 }
117 return oldipl;
118 }
119
120 #define _setsirr(reg) mtpr((reg), PR_SIRR)
121
122 #define spl0() _splset(IPL_NONE) /* IPL00 */
123 #define splddb() splraiseipl(makeiplcookie(IPL_SOFTDDB)) /* IPL0F */
124 #define splconsmedia() splraiseipl(makeiplcookie(IPL_CONSMEDIA)) /* IPL14 */
125
126 #include <sys/spl.h>
127
128 /* These are better to use when playing with VAX buses */
129 #define spluba() splraiseipl(makeiplcookie(IPL_UBA)) /* IPL17 */
130 #define spl4() splx(0x14)
131 #define spl5() splx(0x15)
132 #define spl6() splx(0x16)
133 #define spl7() splx(0x17)
134
135 /* schedule software interrupts
136 */
137 #define setsoftddb() _setsirr(IPL_SOFTDDB)
138 #define setsoftserial() _setsirr(IPL_SOFTSERIAL)
139 #define setsoftnet() _setsirr(IPL_SOFTNET)
140
141 #if !defined(_LOCORE)
142 LIST_HEAD(sh_head, softintr_handler);
143
144 struct softintr_head {
145 int shd_ipl;
146 struct sh_head shd_intrs;
147 };
148
149 struct softintr_handler {
150 struct softintr_head *sh_head;
151 LIST_ENTRY(softintr_handler) sh_link;
152 void (*sh_func)(void *);
153 void *sh_arg;
154 int sh_pending;
155 };
156
157 extern void *softintr_establish(int, void (*)(void *), void *);
158 extern void softintr_disestablish(void *);
159
160 static __inline void
161 softintr_schedule(void *arg)
162 {
163 struct softintr_handler * const sh = arg;
164 sh->sh_pending = 1;
165 _setsirr(sh->sh_head->shd_ipl);
166 }
167 #endif /* _LOCORE */
168 #endif /* _KERNEL */
169 #endif /* _VAX_INTR_H */
170