ka43.h revision 1.1
1 /* $NetBSD: ka43.h,v 1.1 1996/07/20 17:58:16 ragge Exp $ */ 2 /* 3 * Copyright (c) 1996 Ludd, University of Lule}, Sweden. 4 * All rights reserved. 5 * 6 * This code is derived from software contributed to Ludd by Bertram Barth. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. All advertising materials mentioning features or use of this software 17 * must display the following acknowledgement: 18 * This product includes software developed at Ludd, University of 19 * Lule}, Sweden and its contributors. 20 * 4. The name of the author may not be used to endorse or promote products 21 * derived from this software without specific prior written permission 22 * 23 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 24 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 25 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 26 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 27 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 28 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 29 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 30 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 32 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 33 */ 34 35 /* 36 * Definitions for I/O addresses of 37 * 38 * VAXstation 3100 model 76 (RigelMAX) 39 */ 40 41 #define KA43_SIDEX 0x20040004 /* SID extension register */ 42 43 #define KA43_CFGTST 0x20020000 /* Configuration and Test register */ 44 #define KA43_IORESET 0x20020000 /* I/O Reset register */ 45 46 #define KA43_ROMGETC 0x20040044 47 #define KA43_ROMPUTC 0x20040058 48 #define KA43_ROMPUTS 0x2004004C 49 50 #define KA43_CH2_BASE 0x10000000 /* 2nd level cache data area */ 51 #define KA43_CH2_END 0x1FFFFFFF 52 #define KA43_CH2_SIZE 0x10000000 53 #define KA43_CT2_BASE 0x21000000 /* 2nd level cache tag area */ 54 #define KA43_CT2_END 0x2101FFFF 55 #define KA43_CT2_SIZE 0x20000 56 #define KA43_CH2_CREG 0x21100000 /* 2nd level cache control register */ 57 #define KA43_SESR 0x21100000 /* ??? */ 58 59 #define KA43_ROM_BASE 0x20040000 /* System module ROM */ 60 #define KA43_ROM_END 0x2007FFFF 61 #define KA43_ROM_SIZE 0x40000 /* ??? */ 62 63 #define KA43_IVN_BASE 0x20040020 /* Interrupt Vector Numbers */ 64 #define KA43_IVN_END 0x2004003F 65 #define KA43_IVN_SIZE 0x20 66 67 #define KA43_HLTCOD 0x20080000 /* Halt Code Register */ 68 #define KA43_MSER 0x20080004 /* Memory System Error register */ 69 #define KA43_MEAR 0x20080008 /* Memory Error Address register */ 70 #define KA43_INTMSK 0x2008000C /* Interrupt Mask register */ 71 #define KA43_VDCORG 0x2008000D /* Video Controller Origin Register */ 72 #define KA43_VDCSEL 0x2008000E /* Video Controller Select Register */ 73 #define KA43_INTREQ 0x2008000F /* Interrupt Request register */ 74 #define KA43_INTCLR 0x2008000F /* Interrupt Request clear register */ 75 #define KA43_DIAGDSP 0x20080010 76 #define KA43_PARCTL 0x20080014 /* Parity Control Register */ 77 #define KA43_DIAGTME 0x2008001E 78 79 #define KA43_PCTL_DPEN 0x00000001 /* DMA parity enable (bit 0) */ 80 #define KA43_PCTL_CPEN 0x00000002 /* CPU Parity enable (bit 1) */ 81 #define KA43_PCTL_DMA 0x01000000 /* LANCE DMA control (bit 24) */ 82 83 #define KA43_SESR_CENB 0x00000001 84 #define KA43_SESR_SERR 0x00000002 85 #define KA43_SESR_LERR 0x00000004 86 #define KA43_SESR_CERR 0x00000008 87 #define KA43_SESR_DIRTY 0x00000010 88 #define KA43_SESR_MISS 0x00000020 89 #define KA43_SESR_DPE 0x00000040 90 #define KA43_SESR_TPE 0x00000080 91 #define KA43_SESR_WSB 0x00010000 92 #define KA43_SESR_CIEA 0x7FFC0000 93 94 #define KA43_PCS_FORCEHIT (1<<0) /* Force hit */ 95 #define KA43_PCS_ENABLE (1<<1) /* Enable primary cache */ 96 #define KA43_PCS_FLUSH (1<<2) /* Flush cache */ 97 #define KA43_PCS_REFRESH (1<<3) /* Enable refresh */ 98 #define KA43_PCS_HIT (1<<4) /* Cache hit */ 99 #define KA43_PCS_INTERRUPT (1<<5) /* Interrupt pending */ 100 #define KA43_PCS_TRAP2 (1<<6) /* Trap while trap */ 101 #define KA43_PCS_TRAP1 (1<<7) /* Micro trap / machine check */ 102 #define KA43_PCS_TPERR (1<<8) /* Tag parity error */ 103 #define KA43_PCS_DPERR (1<<9) /* Dal data parity error */ 104 #define KA43_PCS_PPERR (1<<10) /* P data parity error */ 105 #define KA43_PCS_BUSERR (1<<11) /* Bus error */ 106 #define KA43_PCS_BCHIT (1<<12) /* B cache hit */ 107 108 /* 109 * Other fixed addresses which should be mapped 110 */ 111 #define KA43_CPU_BASE 0x20080000 /* so called "CPU registers" */ 112 #define KA43_CPU_END 0x200800FF 113 #define KA43_CPU_SIZE 0x100 114 #define KA43_NWA_BASE 0x20090000 /* Network Address ROM */ 115 #define KA43_NWA_END 0x2009007F 116 #define KA43_NWA_SIZE 0x80 117 #define KA43_SER_BASE 0x200A0000 /* Serial line controller */ 118 #define KA43_SER_END 0x200A000F 119 #define KA43_SER_SIZE 0x10 120 #define KA43_WAT_BASE 0x200B0000 /* TOY clock and NV-RAM */ 121 #define KA43_WAT_END 0x200B00FF 122 #define KA43_WAT_SIZE 0x100 123 #define KA43_SC1_BASE 0x200C0080 /* 1st SCSI Controller Chip */ 124 #define KA43_SC1_END 0x200C009F 125 #define KA43_SC1_SIZE 0x20 126 #define KA43_SC2_BASE 0x200C0180 /* 2nd SCSI Controller Chip */ 127 #define KA43_SC2_END 0x200C019F 128 #define KA43_SC2_SIZE 0x20 129 #define KA43_SCS_BASE 0x200C0000 /* area occupied by SCSI 1+2 */ 130 #define KA43_SCS_END 0x200C01FF 131 #define KA43_SCS_SIZE 0x200 132 #define KA43_LAN_BASE 0x200E0000 /* LANCE chip registers */ 133 #define KA43_LAN_END 0x200E0007 134 #define KA43_LAN_SIZE 0x08 135 #define KA43_CUR_BASE 0x200F0000 /* Monochrome video cursor chip */ 136 #define KA43_CUR_END 0x200F003C 137 #define KA43_CUR_SIZE 0x40 138 #define KA43_DMA_BASE 0x202D0000 /* 128KB Data Buffer */ 139 #define KA43_DMA_END 0x202EFFFF 140 #define KA43_DMA_SIZE 0x20000 141 #define KA43_VME_BASE 0x30000000 142 #define KA43_VME_END 0x3003FFFF 143 #define KA43_VME_SIZE 0x40000 144 145 #define KA43_SC1_DADR 0x200C00A0 /* (1st SCSI) DMA address register */ 146 #define KA43_SC1_DCNT 0x200C00C0 /* (1st SCSI) DMA byte count reg. */ 147 #define KA43_SC1_DDIR 0x200C00C4 /* (1st SCSI) DMA transfer direction */ 148 #define KA43_SC2_DADR 0x200C01A0 149 #define KA43_SC2_DCNT 0x200C01C0 150 #define KA43_SC2_DDIR 0x200C01C4 151 152 #define KA43_CUR_CMD 0x200F0000 /* Cursor Command Register */ 153 #define KA43_CUR_XPOS 0x200F0004 /* Cursor X position */ 154 #define KA43_CUR_YPOS 0x200F0008 /* Cursor Y position */ 155 156 #define KA43_CUR_XMIN1 0x200F000C /* Region 1 left edge */ 157 #define KA43_CUR_XMAX1 0x200F0010 /* Region 1 right edge */ 158 #define KA43_CUR_YMIN1 0x200F0014 /* Region 1 top edge */ 159 #define KA43_CUR_YMAX1 0x200F0018 /* Region 1 bottom edge */ 160 161 #define KA43_CUR_XMIN2 0x200F002C /* Region 2 left edge */ 162 #define KA43_CUR_XMAX2 0x200F0030 /* Region 2 right edge */ 163 #define KA43_CUR_YMIN2 0x200F0034 /* Region 2 top edge */ 164 #define KA43_CUR_YMAX2 0x200F0038 /* Region 2 bottom edge */ 165 166 /* 167 * Clock-Chip data in NVRAM 168 */ 169 #define KA43_CPMBX 0x200B0038 /* Console Mailbox (1 byte) */ 170 #define KA43_CPFLG 0x200B003C /* Console Program Flags (1 byte) */ 171 #define KA43_LK201_ID 0x200B0040 /* Keyboard Variation (1 byte) */ 172 #define KA43_CONS_ID 0x200B0044 /* Console Device Type (1 byte) */ 173 #define KA43_SCR 0x200B0048 /* Console Scratch RAM */ 174 #define KA43_TEMP 0x200B0058 /* Used by System Firmware */ 175 #define KA43_BAT_CHK 0x200B0088 /* Battery Check Data */ 176 #define KA43_PASSWD 0x200B0098 /* ??? */ 177 #define KA43_BOOTFLG 0x200B00A8 /* Default Boot Flags (4 bytes) */ 178 #define KA43_SCRLEN 0x200B00B8 /* Number of pages of SCR (1 byte) */ 179 #define KA43_SCSIPORT 0x200B00BC /* Tape Controller Port Data */ 180 #define KA43_RESERVED 0x200B00C0 /* Reserved (16 bytes) */ 181 182 struct ka43_cpu { 183 u_long ka43_hltcod; 184 u_long ka43_mser; 185 u_long ka43_cear; 186 u_long ka43_intmsk; 187 }; 188 189 struct ka43_clock { 190 u_long :2; u_long sec :8; u_long :22; 191 u_long :2; u_long secalrm :8; u_long :22; 192 u_long :2; u_long min :8; u_long :22; 193 u_long :2; u_long minalrm :8; u_long :22; 194 u_long :2; u_long hr :8; u_long :22; 195 u_long :2; u_long hralrm :8; u_long :22; 196 u_long :2; u_long dayofwk :8; u_long :22; 197 u_long :2; u_long day :8; u_long :22; 198 u_long :2; u_long mon :8; u_long :22; 199 u_long :2; u_long yr :8; u_long :22; 200 u_long :2; u_long csr0 :8; u_long :22; 201 u_long :2; u_long csr1 :8; u_long :22; 202 u_long :2; u_long csr2 :8; u_long :22; 203 u_long :2; u_long csr3 :8; u_long :22; 204 u_long :2; u_long cpmbx :8; u_long :22; 205 }; 206 207 int ka43_setup __P((struct uvax_calls *p, int flags)); 208 static int ka43_clkread __P((time_t)); 209 static void ka43_clkwrite __P((void)); 210
Indexes created Tue Sep 23 07:09:52 GMT 2025