Home | History | Annotate | Line # | Download | only in include
ka670.h revision 1.3 
      1 /*	$NetBSD: ka670.h,v 1.3 2002/12/01 21:21:45 matt Exp $	*/
      2 /*
      3  * Copyright (c) 1999 Ludd, University of Lule}, Sweden.
      4  * All rights reserved.
      5  *
      6  * This code is derived from software contributed to Ludd by Bertram Barth.
      7  *
      8  * Redistribution and use in source and binary forms, with or without
      9  * modification, are permitted provided that the following conditions
     10  * are met:
     11  * 1. Redistributions of source code must retain the above copyright
     12  *    notice, this list of conditions and the following disclaimer.
     13  * 2. Redistributions in binary form must reproduce the above copyright
     14  *    notice, this list of conditions and the following disclaimer in the
     15  *    documentation and/or other materials provided with the distribution.
     16  * 3. All advertising materials mentioning features or use of this software
     17  *    must display the following acknowledgement:
     18  *	This product includes software developed at Ludd, University of
     19  *	Lule}, Sweden and its contributors.
     20  * 4. The name of the author may not be used to endorse or promote products
     21  *    derived from this software without specific prior written permission
     22  *
     23  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
     24  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
     25  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
     26  * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
     27  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
     28  * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
     29  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
     30  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
     31  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
     32  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
     33  */
     34 
     35 /*
     36  * Definitions for I/O addresses of
     37  *
     38  *	VAX 4000/300 (KA670)
     39  */
     40 #ifndef _VAX_KA670_H_
     41 #define _VAX_KA670_H_
     42 
     43 #define KA670_SIDEX	0x20040004	/* SID extension register */
     44 #define KA670_IORESET	0x20020000	/* I/O Reset register */
     45 
     46 #define KA670_ROM_BASE	0x20040000	/* System module ROM */
     47 #define KA670_ROM_END	0x2007FFFF
     48 #define KA670_ROM_SIZE	   0x40000
     49 
     50 /*
     51  * The following values refer to bits/bitfields within the 4 internal
     52  * registers controlling primary cache:
     53  * PR_PCTAG(124, tag-register)		PR_PCIDX(125, index-register)
     54  * PR_PCERR(126, error-register)	PR_PCSTS(127, status-register)
     55  */
     56 #define KA670_PCTAG_TAG		0x1FFFF800	/* bits 11-29 */
     57 #define KA670_PCTAG_PARITY	0x40000000
     58 #define KA670_PCTAG_VALID	0x80000000
     59 
     60 #define KA670_PCIDX_INDEX	0x000007F8	/* 0x100 Q-word entries */
     61 
     62 #define KA670_PCERR_ADDR		0x3FFFFFFF
     63 
     64 #define KA670_PCS_FORCEHIT	0x00000001	/* Force hit */
     65 #define KA670_PCS_ENABLE		0x00000002	/* Enable primary cache */
     66 #define KA670_PCS_FLUSH		0x00000004	/* Flush cache */
     67 #define KA670_PCS_REFRESH	0x00000008	/* Enable refresh */
     68 #define KA670_PCS_HIT		0x00000010	/* Cache hit */
     69 #define KA670_PCS_INTERRUPT	0x00000020	/* Interrupt pending */
     70 #define KA670_PCS_TRAP2		0x00000040	/* Trap while trap */
     71 #define KA670_PCS_TRAP1		0x00000080	/* Micro trap/machine check */
     72 #define KA670_PCS_TPERR		0x00000100	/* Tag parity error */
     73 #define KA670_PCS_DPERR		0x00000200	/* Dal data parity error */
     74 #define KA670_PCS_PPERR		0x00000400	/* P data parity error */
     75 #define KA670_PCS_BUSERR		0x00000800	/* Bus error */
     76 #define KA670_PCS_BCHIT		0x00001000	/* B cache hit */
     77 
     78 #define KA670_PCSTS_BITS \
     79 	"\020\015BCHIT\014BUSERR\013PPERR\012DPERR\011TPERR\010TRAP1" \
     80 	"\007TRAP2\006INTR\005HIT\004REFRESH\003FLUSH\002ENABLE\001FORCEHIT"
     81 
     82 #define KA670_BCSTS_BITS \
     83 	"\020\015BCHIT\014BUSERR\013PPERR\012DPERR\011TPERR\010TRAP1" \
     84 	"\007TRAP2\006INTR\005HIT\004REFRESH\003FLUSH\002ENABLE\001FORCEHIT"
     85 
     86 /*
     87  * Bits in PR_ACCS (Floating Point Accelerator Register)
     88  */
     89 #define KA670_ACCS_VECTOR	(1<<0)	/* Vector Unit Present */
     90 #define KA670_ACCS_FCHIP		(1<<1)	/* FPU chip present */
     91 #define KA670_ACCS_WEP		(1<<31) /* Write Even Parity */
     92 
     93 /*
     94  * CPU-specific definitions for VAX 6000/400 (Calypso/XRP).
     95  */
     96 
     97 /* Rigel SSC definitions */
     98 #define RSSC_ADDR	0x20140000	/* Phys address */
     99 #define RSSC_CONFIG	0x10		/* Offset */
    100 #define RSSC_BUSCTRL	0x20		/* Offset */
    101 #define RSSC_OPORT	0x30		/* Offset */
    102 #define RSSC_IPORT	0x40		/* Offset */
    103 
    104 #endif /* _VAX_KA670_H_ */
    105