1 1.5 martin /* $NetBSD: lcgreg.h,v 1.5 2008/04/28 20:23:39 martin Exp $ */ 2 1.1 matt 3 1.1 matt /*- 4 1.1 matt * Copyright (c) 2000 The NetBSD Foundation, Inc. 5 1.1 matt * All rights reserved. 6 1.1 matt * 7 1.1 matt * This code is derived from software contributed to The NetBSD Foundation 8 1.1 matt * by Matt Thomas of 3am Software Foundry. 9 1.1 matt * 10 1.1 matt * Redistribution and use in source and binary forms, with or without 11 1.1 matt * modification, are permitted provided that the following conditions 12 1.1 matt * are met: 13 1.1 matt * 1. Redistributions of source code must retain the above copyright 14 1.1 matt * notice, this list of conditions and the following disclaimer. 15 1.1 matt * 2. Redistributions in binary form must reproduce the above copyright 16 1.1 matt * notice, this list of conditions and the following disclaimer in the 17 1.1 matt * documentation and/or other materials provided with the distribution. 18 1.1 matt * 19 1.1 matt * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 1.1 matt * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 1.1 matt * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 1.1 matt * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 1.1 matt * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 1.1 matt * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 1.1 matt * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 1.1 matt * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 1.1 matt * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 1.1 matt * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 1.1 matt * POSSIBILITY OF SUCH DAMAGE. 30 1.1 matt */ 31 1.1 matt 32 1.1 matt #ifndef _VAX_LCGREG_H 33 1.1 matt #define _VAX_LCGREG_H 34 1.1 matt 35 1.1 matt /* The registers of the LCG used in the VS4000/60 and VS4000/VLC. 36 1.1 matt * All relative to 0x20100000 37 1.1 matt */ 38 1.1 matt 39 1.3 abs /* Memory Control, Flow Control, Configuration Registers 40 1.1 matt */ 41 1.1 matt #define LCG_REG_MEM_CONFIG 0x001800 42 1.1 matt #define LCG_REG_MEM_STATUS 0x001804 43 1.1 matt #define LCG_REG_MEM_CURRENT_STATE 0x001808 44 1.1 matt #define LCG_REG_MEM_ERROR 0x00180c 45 1.1 matt #define LCG_REG_SLOW_CONTROL_STATUS 0x001810 46 1.1 matt 47 1.1 matt /* Video Control Registers 48 1.1 matt */ 49 1.1 matt #define LCG_REG_VIDEO_CONFIG 0x001e00 50 1.1 matt #define LCG_REG_VIDEO_HTIMING 0x001e10 51 1.1 matt #define LCG_REG_VIDEO_VTIMING 0x001e14 52 1.1 matt #define LCG_REG_VIDEO_TIMING 0x001e18 53 1.1 matt #define LCG_REG_VIDEO_X 0x000e30 54 1.1 matt #define LCG_REG_VIDEO_Y 0x000e30 55 1.1 matt #define LCG_REG_VIDEO_REFRESH_BASE 0x000e34 56 1.1 matt #define LCG_REG_VIDEO_REFRESH_SHIFT 0x000e40 57 1.1 matt #define LCG_REG_VIDEO_LUT_LOAD_COUNT 0x000e40 58 1.1 matt #define LCG_REG_CURSOR_SCANLINE_LW0 0x000e50 59 1.1 matt #define LCG_REG_CURSOR_SCANLINE_LW1 0x000e54 60 1.1 matt #define LCG_REG_CURSOR_SCANLINE_LW2 0x000e58 61 1.1 matt #define LCG_REG_CURSOR_SCANLINE_LW3 0x000e5c 62 1.1 matt #define LCG_REG_CURSOR_BASE 0x000e80 63 1.1 matt #define LCG_REG_CURSOR_XY 0x000e84 64 1.1 matt #define LCG_REG_CURSOR_X 0x000e84 65 1.1 matt #define LCG_REG_CURSOR_Y 0x000e84 66 1.1 matt #define LCG_REG_LUT_CONSOLE_SEL 0x000ee0 67 1.1 matt #define LCG_REG_LUT_COLOR_BASE_W 0x0006e4 68 1.1 matt #define LCG_REG_LUT_COLOR_BASE_R 0x0006e4 69 1.1 matt #define LCG_REG_LUT_CONTROL_BASE 0x000ee8 70 1.1 matt #define LCG_REG_VIDEO_COUNTER_TEST 0x000f00 71 1.1 matt #define LCG_REG_MEM_REFRESH_BASE 0x000f04 72 1.1 matt 73 1.1 matt /* Graphics Control and VM Registers 74 1.1 matt */ 75 1.1 matt #define LCG_REG_LCG_GO 0x000c80 76 1.1 matt #define LCG_REG_NEXT_ADDRESS 0x001334 77 1.1 matt #define LCG_REG_PA_SPTE_PTE 0x001338 78 1.1 matt #define LCG_REG_TB_INVALIDATE_SINGLE 0x001a00 79 1.1 matt #define LCG_REG_TB_INVALIDATE_ALL 0x001a08 80 1.1 matt #define LCG_REG_TB_INVALIDATE_STATUS 0x001a10 81 1.1 matt #define LCG_REG_TB_STATUS 0x001c00 82 1.1 matt #define LCG_REG_TB_VPN_COUNT 0x001c04 83 1.1 matt #define LCG_REG_TB_DEST_VPN 0x001c14 84 1.1 matt #define LCG_REG_TB_SOURCE_VPN 0x001c18 85 1.1 matt #define LCG_REG_TB_STENCIL_VPN 0x001c1c 86 1.1 matt #define LCG_REG_TB_DEST_DATA_PFN_R 0x001c24 87 1.1 matt #define LCG_REG_TB_DEST_DATA_PFN_W 0x001c24 88 1.1 matt #define LCG_REG_TB_SOURCE_DATA_PFN_R 0x001c28 89 1.1 matt #define LCG_REG_TB_SOURCE_DATA_PFN_W 0x001c28 90 1.1 matt #define LCG_REG_TB_STENCIL_DATA_PFN_R 0x001c2c 91 1.1 matt #define LCG_REG_TB_STENCIL_DATA_PFN_W 0x001c2c 92 1.1 matt #define LCG_REG_TB_DEST_PRE_PFN_R 0x001c34 93 1.1 matt #define LCG_REG_TB_DEST_PRE_PFN_W 0x001c34 94 1.1 matt #define LCG_REG_TB_SOURCE_PTE_PFN_R 0x001c38 95 1.1 matt #define LCG_REG_TB_SOURCE_PTE_PFN_W 0x001c38 96 1.1 matt #define LCG_REG_TB_STENCIL_PTE_PFN_R 0x001c3c 97 1.1 matt #define LCG_REG_TB_STENCIL_PTE_PFN_W 0x001c3c 98 1.1 matt #define LCG_REG_GRAPHICS_CONFIG 0x001c90 99 1.1 matt #define LCG_REG_GRAPHICS_INT_STATUS 0x001c94 100 1.1 matt #define LCG_REG_GRAPHICS_INT_SET_ENABLE 0x001c98 101 1.1 matt #define LCG_REG_GRAPHICS_INT_CLR_ENABLE 0x001c9c 102 1.1 matt #define LCG_REG_GRAPHICS_SUB_STATUS 0x001ca0 103 1.1 matt #define LCG_REG_GRAPHICS_CONTROL 0x001ca4 104 1.1 matt #define LCG_REG_BREAKPT_ADDRESS 0x001cb0 105 1.1 matt #define LCG_REG_BREAKPT_VIRTUAL 0x001cb0 106 1.1 matt #define LCG_REG_WRITE_PROTECT_LOW_HIGH 0x001cc0 107 1.1 matt #define LCG_REG_WRITE_PROTECT_LOW 0x001cc0 108 1.1 matt #define LCG_REG_WRITE_PROTECT_HIGH 0x001cc0 109 1.1 matt #define LCG_REG_MAX_VIRTUAL_ADDRESS 0x002350 110 1.1 matt #define LCG_REG_PA_SPTE_POBR 0x002354 111 1.1 matt 112 1.1 matt /* Clip List / Command FIFO Registers 113 1.1 matt */ 114 1.1 matt #define LCG_REG_CLIP_LIST_OFFSET 0x0004e4 115 1.1 matt #define LCG_REG_CLIP_LIST_BASE 0x0004e4 116 1.1 matt #define LCG_REG_CLIP_LIST 0x0004e4 117 1.1 matt #define LCG_REG_FIFO_MASKS 0x000570 118 1.1 matt #define LCG_REG_FIFO_HEAD_OFFSET 0x000574 119 1.1 matt #define LCG_REG_FIFO_BASE 0x000574 120 1.1 matt #define LCG_REG_FIFO_HEAD 0x000574 121 1.1 matt #define LCG_REG_FIFO_TAIL_OFFSET 0x000578 122 1.1 matt #define LCG_REG_FIFO_BASE2 0x000578 123 1.1 matt #define LCG_REG_FIFO_TAIL 0x000578 124 1.1 matt #define LCG_REG_CLIP_LIST_SAVE_OFFSET 0x000ce4 125 1.2 matt #define LCG_REG_FIFO_RESIDUE_LW0 0x000d04 126 1.2 matt #define LCG_REG_FIFO_RESIDUE_LW1 0x000d08 127 1.1 matt #define LCG_REG_FIFO_RESIDUE_LW2 0x000d0c 128 1.1 matt #define LCG_REG_FIFO_LENGTH 0x000d70 129 1.1 matt #define LCG_REG_FIFO_SAVE_HEAD_OFFSET 0x000d74 130 1.1 matt #define LCG_REG_FIFO_WINDOW_BASE 0x080000 131 1.1 matt #define LCG_REG_FIFO_WINDOW_END 0x100000 132 1.1 matt 133 1.1 matt /* Graphics Data Buffer and Pixel SLU Registers 134 1.1 matt */ 135 1.1 matt #define LCG_REG_LOGICAL_FUNCTION 0x000220 136 1.1 matt #define LCG_REG_PLANE_MASK 0x000234 137 1.1 matt #define LCG_REG_SOURCE_PLANE_INDEX 0x00026c 138 1.1 matt #define LCG_REG_FOREGROUND_PIXEL 0x0002c0 139 1.1 matt #define LCG_REG_BACKGROUND_PIXEL 0x0004c0 140 1.1 matt #define LCG_REG_GDB_LW0 0x000d80 141 1.1 matt #define LCG_REG_GDB_LW1 0x000d84 142 1.1 matt #define LCG_REG_GDB_LW2 0x000d88 143 1.1 matt #define LCG_REG_GDB_LW3 0x000d8c 144 1.1 matt #define LCG_REG_GDB_LW4 0x000d90 145 1.1 matt #define LCG_REG_GDB_LW5 0x000d94 146 1.1 matt #define LCG_REG_GDB_LW6 0x000d98 147 1.1 matt #define LCG_REG_GDB_LW7 0x000d9c 148 1.1 matt #define LCG_REG_SLU_STATE 0x000da0 149 1.1 matt 150 1.1 matt /* Address Generator Registers 151 1.1 matt */ 152 1.1 matt #define LCG_REG_CLIP_MIN_Y 0x000244 153 1.1 matt #define LCG_REG_CLIP_MIN_MAX_X 0x000248 154 1.1 matt #define LCG_REG_CLIP_MIN_X 0x000248 155 1.1 matt #define LCG_REG_CLIP_MAX_X 0x000248 156 1.1 matt #define LCG_REG_CLIP_MAX_Y 0x00024c 157 1.1 matt #define LCG_REG_DEST_X_BIAS 0x000250 158 1.1 matt #define LCG_REG_DEST_Y_ORIGIN 0x000254 159 1.1 matt #define LCG_REG_DEST_Y_STEP 0x000258 160 1.1 matt #define LCG_REG_SOURCE_X_BIAS 0x000260 161 1.1 matt #define LCG_REG_SOURCE_Y_BASE 0x000264 162 1.1 matt #define LCG_REG_SOURCE_Y_STEP_WIDTH 0x000268 163 1.1 matt #define LCG_REG_SOURCE_Y_STEP 0x000268 164 1.1 matt #define LCG_REG_SOURCE_WIDTH 0x000268 165 1.1 matt #define LCG_REG_STENCIL_X_BIAS 0x000270 166 1.1 matt #define LCG_REG_STENCIL_Y_BASE 0x000274 167 1.1 matt #define LCG_REG_STENCIL_Y_STEP 0x000278 168 1.1 matt #define LCG_REG_DEST_Y_BASE 0x000284 169 1.1 matt #define LCG_REG_DEST_X 0x000290 170 1.1 matt #define LCG_REG_DEST_WIDTH_HEIGHT 0x000294 171 1.1 matt #define LCG_REG_DEST_WIDTH 0x000294 172 1.1 matt #define LCG_REG_DEST_HEIGHT 0x000294 173 1.1 matt #define LCG_REG_AG_STATUS2 0x000320 174 1.1 matt #define LCG_REG_AG_CURRENT_STATE 0x000320 175 1.1 matt #define LCG_REG_CURRENT_OPCODE 0x000320 176 1.1 matt #define LCG_REG_OP_ACTION_CODE 0x000320 177 1.1 matt #define LCG_REG_AG_STATUS 0x000324 178 1.1 matt #define LCG_REG_NEXT_X 0x000330 179 1.1 matt #define LCG_REG_CLIP_X_DIFF 0x000330 180 1.1 matt #define LCG_REG_SOURCE_X_BIAS0 0x000460 181 1.1 matt #define LCG_REG_SOURCE_WIDTH0 0x000468 182 1.1 matt #define LCG_REG_DEST_X0 0x000490 183 1.1 matt #define LCG_REG_DEST_WIDTH0 0x000494 184 1.1 matt #define LCG_REG_TILE_ROTATION 0x000660 185 1.1 matt #define LCG_REG_TILE_WIDTH 0x000668 186 1.1 matt 187 1.1 matt #endif /* _VAX_LCGREG_H */ 188