lock.h revision 1.7 1 1.7 ragge /* $NetBSD: lock.h,v 1.7 2001/06/04 15:37:05 ragge Exp $ */
2 1.1 ragge
3 1.1 ragge /*
4 1.1 ragge * Copyright (c) 2000 Ludd, University of Lule}, Sweden.
5 1.1 ragge * All rights reserved.
6 1.1 ragge *
7 1.1 ragge * Redistribution and use in source and binary forms, with or without
8 1.1 ragge * modification, are permitted provided that the following conditions
9 1.1 ragge * are met:
10 1.1 ragge * 1. Redistributions of source code must retain the above copyright
11 1.1 ragge * notice, this list of conditions and the following disclaimer.
12 1.1 ragge * 2. Redistributions in binary form must reproduce the above copyright
13 1.1 ragge * notice, this list of conditions and the following disclaimer in the
14 1.1 ragge * documentation and/or other materials provided with the distribution.
15 1.1 ragge * 3. All advertising materials mentioning features or use of this software
16 1.1 ragge * must display the following acknowledgement:
17 1.1 ragge * This product includes software developed at Ludd, University of Lule}.
18 1.1 ragge * 4. The name of the author may not be used to endorse or promote products
19 1.1 ragge * derived from this software without specific prior written permission
20 1.1 ragge *
21 1.1 ragge * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
22 1.1 ragge * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
23 1.1 ragge * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
24 1.1 ragge * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
25 1.1 ragge * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
26 1.1 ragge * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
27 1.1 ragge * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
28 1.1 ragge * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
29 1.1 ragge * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
30 1.1 ragge * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
31 1.1 ragge */
32 1.1 ragge
33 1.1 ragge #ifndef _VAX_LOCK_H_
34 1.1 ragge #define _VAX_LOCK_H_
35 1.3 ragge
36 1.6 ragge typedef __volatile int __cpu_simple_lock_t;
37 1.4 thorpej
38 1.6 ragge #define __SIMPLELOCK_LOCKED 1
39 1.6 ragge #define __SIMPLELOCK_UNLOCKED 0
40 1.3 ragge
41 1.2 thorpej static __inline void
42 1.4 thorpej __cpu_simple_lock_init(__cpu_simple_lock_t *alp)
43 1.1 ragge {
44 1.6 ragge __asm__ __volatile ("movl %0,r1;jsb Sunlock"
45 1.6 ragge : /* No output */
46 1.6 ragge : "g"(alp)
47 1.6 ragge : "r1","cc","memory");
48 1.6 ragge #if 0
49 1.6 ragge __asm__ __volatile ("bbcci $0, %0, 1f;1:"
50 1.6 ragge : /* No output */
51 1.6 ragge : "m"(*alp));
52 1.6 ragge #endif
53 1.1 ragge }
54 1.1 ragge
55 1.7 ragge static __inline int
56 1.7 ragge __cpu_simple_lock_try(__cpu_simple_lock_t *alp)
57 1.7 ragge {
58 1.7 ragge int ret;
59 1.7 ragge
60 1.7 ragge __asm__ __volatile ("movl %1,r1;jsb Slocktry;movl r0,%0"
61 1.7 ragge : "=&r"(ret)
62 1.7 ragge : "g"(alp)
63 1.7 ragge : "r0","r1","cc","memory");
64 1.7 ragge #if 0
65 1.7 ragge __asm__ __volatile ("movl $0,%0;bbssi $0,%1,1f;incl %0;1:"
66 1.7 ragge : "=&r"(ret)
67 1.7 ragge : "m"(*alp));
68 1.7 ragge #endif
69 1.7 ragge
70 1.7 ragge return ret;
71 1.7 ragge }
72 1.7 ragge
73 1.7 ragge #define __cpu_simple_lock(alp) \
74 1.7 ragge { \
75 1.7 ragge struct cpu_info *__ci = curcpu(); \
76 1.7 ragge \
77 1.7 ragge while (__cpu_simple_lock_try(alp) == 0) { \
78 1.7 ragge int __s; \
79 1.7 ragge \
80 1.7 ragge if (__ci->ci_ipimsgs & (1 << IPI_SEND_CNCHAR)) { \
81 1.7 ragge __s = splipi(); \
82 1.7 ragge cpu_handle_ipi(); \
83 1.7 ragge splx(__s); \
84 1.7 ragge } \
85 1.7 ragge } \
86 1.7 ragge }
87 1.7 ragge
88 1.7 ragge #if 0
89 1.2 thorpej static __inline void
90 1.4 thorpej __cpu_simple_lock(__cpu_simple_lock_t *alp)
91 1.1 ragge {
92 1.7 ragge struct cpu_info *ci = curcpu();
93 1.7 ragge
94 1.7 ragge while (__cpu_simple_lock_try(alp) == 0) {
95 1.7 ragge int s;
96 1.7 ragge
97 1.7 ragge if (ci->ci_ipimsgs & IPI_SEND_CNCHAR) {
98 1.7 ragge s = splipi();
99 1.7 ragge cpu_handle_ipi();
100 1.7 ragge splx(s);
101 1.7 ragge }
102 1.7 ragge }
103 1.7 ragge
104 1.7 ragge #if 0
105 1.6 ragge __asm__ __volatile ("movl %0,r1;jsb Slock"
106 1.6 ragge : /* No output */
107 1.6 ragge : "g"(alp)
108 1.6 ragge : "r0","r1","cc","memory");
109 1.7 ragge #endif
110 1.6 ragge #if 0
111 1.5 matt __asm__ __volatile ("1:;bbssi $0, %0, 1b"
112 1.1 ragge : /* No output */
113 1.5 matt : "m"(*alp));
114 1.6 ragge #endif
115 1.1 ragge }
116 1.7 ragge #endif
117 1.1 ragge
118 1.2 thorpej static __inline void
119 1.4 thorpej __cpu_simple_unlock(__cpu_simple_lock_t *alp)
120 1.1 ragge {
121 1.6 ragge __asm__ __volatile ("movl %0,r1;jsb Sunlock"
122 1.6 ragge : /* No output */
123 1.6 ragge : "g"(alp)
124 1.6 ragge : "r1","cc","memory");
125 1.6 ragge #if 0
126 1.6 ragge __asm__ __volatile ("bbcci $0, %0, 1f;1:"
127 1.6 ragge : /* No output */
128 1.6 ragge : "m"(*alp));
129 1.6 ragge #endif
130 1.1 ragge }
131 1.1 ragge
132 1.6 ragge #if defined(MULTIPROCESSOR)
133 1.6 ragge /*
134 1.6 ragge * On the Vax, interprocessor interrupts can come in at device priority
135 1.6 ragge * level or lower. This can cause some problems while waiting for r/w
136 1.6 ragge * spinlocks from a high'ish priority level: IPIs that come in will not
137 1.6 ragge * be processed. This can lead to deadlock.
138 1.6 ragge *
139 1.6 ragge * This hook allows IPIs to be processed while a spinlock's interlock
140 1.6 ragge * is released.
141 1.6 ragge */
142 1.6 ragge #define SPINLOCK_SPIN_HOOK \
143 1.6 ragge do { \
144 1.6 ragge struct cpu_info *__ci = curcpu(); \
145 1.7 ragge int __s; \
146 1.6 ragge \
147 1.6 ragge if (__ci->ci_ipimsgs != 0) { \
148 1.6 ragge /* printf("CPU %lu has IPIs pending\n", \
149 1.6 ragge __ci->ci_cpuid); */ \
150 1.7 ragge __s = splipi(); \
151 1.6 ragge cpu_handle_ipi(); \
152 1.7 ragge splx(__s); \
153 1.6 ragge } \
154 1.6 ragge } while (0)
155 1.6 ragge #endif /* MULTIPROCESSOR */
156 1.1 ragge #endif /* _VAX_LOCK_H_ */
157