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lock.h revision 1.8.8.3
      1  1.8.8.3  nathanw /*	$NetBSD: lock.h,v 1.8.8.3 2002/10/18 02:40:30 nathanw Exp $	*/
      2  1.8.8.2  nathanw 
      3  1.8.8.2  nathanw /*
      4  1.8.8.2  nathanw  * Copyright (c) 2000 Ludd, University of Lule}, Sweden.
      5  1.8.8.2  nathanw  * All rights reserved.
      6  1.8.8.2  nathanw  *
      7  1.8.8.2  nathanw  * Redistribution and use in source and binary forms, with or without
      8  1.8.8.2  nathanw  * modification, are permitted provided that the following conditions
      9  1.8.8.2  nathanw  * are met:
     10  1.8.8.2  nathanw  * 1. Redistributions of source code must retain the above copyright
     11  1.8.8.2  nathanw  *    notice, this list of conditions and the following disclaimer.
     12  1.8.8.2  nathanw  * 2. Redistributions in binary form must reproduce the above copyright
     13  1.8.8.2  nathanw  *    notice, this list of conditions and the following disclaimer in the
     14  1.8.8.2  nathanw  *    documentation and/or other materials provided with the distribution.
     15  1.8.8.2  nathanw  * 3. All advertising materials mentioning features or use of this software
     16  1.8.8.2  nathanw  *    must display the following acknowledgement:
     17  1.8.8.2  nathanw  *     This product includes software developed at Ludd, University of Lule}.
     18  1.8.8.2  nathanw  * 4. The name of the author may not be used to endorse or promote products
     19  1.8.8.2  nathanw  *    derived from this software without specific prior written permission
     20  1.8.8.2  nathanw  *
     21  1.8.8.2  nathanw  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
     22  1.8.8.2  nathanw  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
     23  1.8.8.2  nathanw  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
     24  1.8.8.2  nathanw  * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
     25  1.8.8.2  nathanw  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
     26  1.8.8.2  nathanw  * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
     27  1.8.8.2  nathanw  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
     28  1.8.8.2  nathanw  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
     29  1.8.8.2  nathanw  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
     30  1.8.8.2  nathanw  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
     31  1.8.8.2  nathanw  */
     32  1.8.8.2  nathanw 
     33  1.8.8.2  nathanw #ifndef _VAX_LOCK_H_
     34  1.8.8.2  nathanw #define _VAX_LOCK_H_
     35  1.8.8.2  nathanw 
     36  1.8.8.2  nathanw typedef __volatile int		__cpu_simple_lock_t;
     37  1.8.8.2  nathanw 
     38  1.8.8.2  nathanw #define __SIMPLELOCK_LOCKED	1
     39  1.8.8.2  nathanw #define __SIMPLELOCK_UNLOCKED	0
     40  1.8.8.2  nathanw 
     41  1.8.8.2  nathanw static __inline void
     42  1.8.8.2  nathanw __cpu_simple_lock_init(__cpu_simple_lock_t *alp)
     43  1.8.8.2  nathanw {
     44  1.8.8.2  nathanw #ifdef _KERNEL
     45  1.8.8.3  nathanw 	__asm__ __volatile ("movl %0,%%r1;jsb Sunlock"
     46  1.8.8.2  nathanw 		: /* No output */
     47  1.8.8.2  nathanw 		: "g"(alp)
     48  1.8.8.2  nathanw 		: "r1","cc","memory");
     49  1.8.8.2  nathanw #else
     50  1.8.8.2  nathanw 	__asm__ __volatile ("bbcci $0,%0,1f;1:"
     51  1.8.8.2  nathanw 		: /* No output */
     52  1.8.8.2  nathanw 		: "m"(*alp)
     53  1.8.8.2  nathanw 		: "cc");
     54  1.8.8.2  nathanw #endif
     55  1.8.8.2  nathanw }
     56  1.8.8.2  nathanw 
     57  1.8.8.2  nathanw static __inline int
     58  1.8.8.2  nathanw __cpu_simple_lock_try(__cpu_simple_lock_t *alp)
     59  1.8.8.2  nathanw {
     60  1.8.8.2  nathanw 	int ret;
     61  1.8.8.2  nathanw 
     62  1.8.8.2  nathanw #ifdef _KERNEL
     63  1.8.8.3  nathanw 	__asm__ __volatile ("movl %1,%%r1;jsb Slocktry;movl %%r0,%0"
     64  1.8.8.2  nathanw 		: "=&r"(ret)
     65  1.8.8.2  nathanw 		: "g"(alp)
     66  1.8.8.2  nathanw 		: "r0","r1","cc","memory");
     67  1.8.8.2  nathanw #else
     68  1.8.8.2  nathanw 	__asm__ __volatile ("clrl %0;bbssi $0,%1,1f;incl %0;1:"
     69  1.8.8.2  nathanw 		: "=&r"(ret)
     70  1.8.8.2  nathanw 		: "m"(*alp)
     71  1.8.8.2  nathanw 		: "cc");
     72  1.8.8.2  nathanw #endif
     73  1.8.8.2  nathanw 
     74  1.8.8.2  nathanw 	return ret;
     75  1.8.8.2  nathanw }
     76  1.8.8.2  nathanw 
     77  1.8.8.2  nathanw #ifdef _KERNEL
     78  1.8.8.2  nathanw #define	VAX_LOCK_CHECKS ((1 << IPI_SEND_CNCHAR) | (1 << IPI_DDB))
     79  1.8.8.2  nathanw #define	__cpu_simple_lock(alp)						\
     80  1.8.8.2  nathanw do {									\
     81  1.8.8.2  nathanw 	struct cpu_info *__ci = curcpu();				\
     82  1.8.8.2  nathanw 									\
     83  1.8.8.2  nathanw 	while (__cpu_simple_lock_try(alp) == 0) {			\
     84  1.8.8.2  nathanw 		int __s;						\
     85  1.8.8.2  nathanw 									\
     86  1.8.8.2  nathanw 		if (__ci->ci_ipimsgs & VAX_LOCK_CHECKS) {		\
     87  1.8.8.2  nathanw 			__s = splipi();					\
     88  1.8.8.2  nathanw 			cpu_handle_ipi();				\
     89  1.8.8.2  nathanw 			splx(__s);					\
     90  1.8.8.2  nathanw 		}							\
     91  1.8.8.2  nathanw 	}								\
     92  1.8.8.2  nathanw } while (0)
     93  1.8.8.2  nathanw #else
     94  1.8.8.2  nathanw static __inline void
     95  1.8.8.2  nathanw __cpu_simple_lock(__cpu_simple_lock_t *alp)
     96  1.8.8.2  nathanw {
     97  1.8.8.2  nathanw 	__asm__ __volatile ("1:bbssi $0,%0,1b"
     98  1.8.8.2  nathanw 		: /* No outputs */
     99  1.8.8.2  nathanw 		: "m"(*alp)
    100  1.8.8.2  nathanw 		: "cc");
    101  1.8.8.2  nathanw }
    102  1.8.8.2  nathanw #endif /* _KERNEL */
    103  1.8.8.2  nathanw 
    104  1.8.8.2  nathanw #if 0
    105  1.8.8.2  nathanw static __inline void
    106  1.8.8.2  nathanw __cpu_simple_lock(__cpu_simple_lock_t *alp)
    107  1.8.8.2  nathanw {
    108  1.8.8.2  nathanw 	struct cpu_info *ci = curcpu();
    109  1.8.8.2  nathanw 
    110  1.8.8.2  nathanw 	while (__cpu_simple_lock_try(alp) == 0) {
    111  1.8.8.2  nathanw 		int s;
    112  1.8.8.2  nathanw 
    113  1.8.8.2  nathanw 		if (ci->ci_ipimsgs & IPI_SEND_CNCHAR) {
    114  1.8.8.2  nathanw 			s = splipi();
    115  1.8.8.2  nathanw 			cpu_handle_ipi();
    116  1.8.8.2  nathanw 			splx(s);
    117  1.8.8.2  nathanw 		}
    118  1.8.8.2  nathanw 	}
    119  1.8.8.2  nathanw 
    120  1.8.8.2  nathanw #if 0
    121  1.8.8.3  nathanw 	__asm__ __volatile ("movl %0,%%r1;jsb Slock"
    122  1.8.8.2  nathanw 		: /* No output */
    123  1.8.8.2  nathanw 		: "g"(alp)
    124  1.8.8.2  nathanw 		: "r0","r1","cc","memory");
    125  1.8.8.2  nathanw #endif
    126  1.8.8.2  nathanw #if 0
    127  1.8.8.2  nathanw 	__asm__ __volatile ("1:;bbssi $0, %0, 1b"
    128  1.8.8.2  nathanw 		: /* No output */
    129  1.8.8.2  nathanw 		: "m"(*alp));
    130  1.8.8.2  nathanw #endif
    131  1.8.8.2  nathanw }
    132  1.8.8.2  nathanw #endif
    133  1.8.8.2  nathanw 
    134  1.8.8.2  nathanw static __inline void
    135  1.8.8.2  nathanw __cpu_simple_unlock(__cpu_simple_lock_t *alp)
    136  1.8.8.2  nathanw {
    137  1.8.8.2  nathanw #ifdef _KERNEL
    138  1.8.8.3  nathanw 	__asm__ __volatile ("movl %0,%%r1;jsb Sunlock"
    139  1.8.8.2  nathanw 		: /* No output */
    140  1.8.8.2  nathanw 		: "g"(alp)
    141  1.8.8.2  nathanw 		: "r1","cc","memory");
    142  1.8.8.2  nathanw #else
    143  1.8.8.2  nathanw 	__asm__ __volatile ("bbcci $0,%0,1f;1:"
    144  1.8.8.2  nathanw 		: /* No output */
    145  1.8.8.2  nathanw 		: "m"(*alp)
    146  1.8.8.2  nathanw 		: "cc");
    147  1.8.8.2  nathanw #endif
    148  1.8.8.2  nathanw }
    149  1.8.8.2  nathanw 
    150  1.8.8.2  nathanw #if defined(MULTIPROCESSOR)
    151  1.8.8.2  nathanw /*
    152  1.8.8.2  nathanw  * On the Vax, interprocessor interrupts can come in at device priority
    153  1.8.8.2  nathanw  * level or lower. This can cause some problems while waiting for r/w
    154  1.8.8.2  nathanw  * spinlocks from a high'ish priority level: IPIs that come in will not
    155  1.8.8.2  nathanw  * be processed. This can lead to deadlock.
    156  1.8.8.2  nathanw  *
    157  1.8.8.2  nathanw  * This hook allows IPIs to be processed while a spinlock's interlock
    158  1.8.8.2  nathanw  * is released.
    159  1.8.8.2  nathanw  */
    160  1.8.8.2  nathanw #define SPINLOCK_SPIN_HOOK						\
    161  1.8.8.2  nathanw do {									\
    162  1.8.8.2  nathanw 	struct cpu_info *__ci = curcpu();				\
    163  1.8.8.2  nathanw 	int __s;							\
    164  1.8.8.2  nathanw 									\
    165  1.8.8.2  nathanw 	if (__ci->ci_ipimsgs != 0) {					\
    166  1.8.8.2  nathanw 		/* printf("CPU %lu has IPIs pending\n",			\
    167  1.8.8.2  nathanw 		    __ci->ci_cpuid); */					\
    168  1.8.8.2  nathanw 		__s = splipi();						\
    169  1.8.8.2  nathanw 		cpu_handle_ipi();					\
    170  1.8.8.2  nathanw 		splx(__s);						\
    171  1.8.8.2  nathanw 	}								\
    172  1.8.8.2  nathanw } while (0)
    173  1.8.8.2  nathanw #endif /* MULTIPROCESSOR */
    174  1.8.8.2  nathanw #endif /* _VAX_LOCK_H_ */
    175