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lock.h revision 1.9
      1  1.9     matt /*	$NetBSD: lock.h,v 1.9 2002/09/12 07:31:13 matt Exp $	*/
      2  1.1    ragge 
      3  1.1    ragge /*
      4  1.1    ragge  * Copyright (c) 2000 Ludd, University of Lule}, Sweden.
      5  1.1    ragge  * All rights reserved.
      6  1.1    ragge  *
      7  1.1    ragge  * Redistribution and use in source and binary forms, with or without
      8  1.1    ragge  * modification, are permitted provided that the following conditions
      9  1.1    ragge  * are met:
     10  1.1    ragge  * 1. Redistributions of source code must retain the above copyright
     11  1.1    ragge  *    notice, this list of conditions and the following disclaimer.
     12  1.1    ragge  * 2. Redistributions in binary form must reproduce the above copyright
     13  1.1    ragge  *    notice, this list of conditions and the following disclaimer in the
     14  1.1    ragge  *    documentation and/or other materials provided with the distribution.
     15  1.1    ragge  * 3. All advertising materials mentioning features or use of this software
     16  1.1    ragge  *    must display the following acknowledgement:
     17  1.1    ragge  *     This product includes software developed at Ludd, University of Lule}.
     18  1.1    ragge  * 4. The name of the author may not be used to endorse or promote products
     19  1.1    ragge  *    derived from this software without specific prior written permission
     20  1.1    ragge  *
     21  1.1    ragge  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
     22  1.1    ragge  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
     23  1.1    ragge  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
     24  1.1    ragge  * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
     25  1.1    ragge  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
     26  1.1    ragge  * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
     27  1.1    ragge  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
     28  1.1    ragge  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
     29  1.1    ragge  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
     30  1.1    ragge  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
     31  1.1    ragge  */
     32  1.1    ragge 
     33  1.1    ragge #ifndef _VAX_LOCK_H_
     34  1.1    ragge #define _VAX_LOCK_H_
     35  1.3    ragge 
     36  1.6    ragge typedef __volatile int		__cpu_simple_lock_t;
     37  1.4  thorpej 
     38  1.6    ragge #define __SIMPLELOCK_LOCKED	1
     39  1.6    ragge #define __SIMPLELOCK_UNLOCKED	0
     40  1.3    ragge 
     41  1.2  thorpej static __inline void
     42  1.4  thorpej __cpu_simple_lock_init(__cpu_simple_lock_t *alp)
     43  1.1    ragge {
     44  1.9     matt #ifdef _KERNEL
     45  1.6    ragge 	__asm__ __volatile ("movl %0,r1;jsb Sunlock"
     46  1.6    ragge 		: /* No output */
     47  1.6    ragge 		: "g"(alp)
     48  1.6    ragge 		: "r1","cc","memory");
     49  1.9     matt #else
     50  1.9     matt 	__asm__ __volatile ("bbcci $0,%0,1f;1:"
     51  1.6    ragge 		: /* No output */
     52  1.9     matt 		: "m"(*alp)
     53  1.9     matt 		: "cc");
     54  1.6    ragge #endif
     55  1.1    ragge }
     56  1.1    ragge 
     57  1.7    ragge static __inline int
     58  1.7    ragge __cpu_simple_lock_try(__cpu_simple_lock_t *alp)
     59  1.7    ragge {
     60  1.7    ragge 	int ret;
     61  1.7    ragge 
     62  1.9     matt #ifdef _KERNEL
     63  1.7    ragge 	__asm__ __volatile ("movl %1,r1;jsb Slocktry;movl r0,%0"
     64  1.7    ragge 		: "=&r"(ret)
     65  1.7    ragge 		: "g"(alp)
     66  1.7    ragge 		: "r0","r1","cc","memory");
     67  1.9     matt #else
     68  1.9     matt 	__asm__ __volatile ("clrl %0;bbssi $0,%1,1f;incl %0;1:"
     69  1.7    ragge 		: "=&r"(ret)
     70  1.9     matt 		: "m"(*alp)
     71  1.9     matt 		: "cc");
     72  1.7    ragge #endif
     73  1.7    ragge 
     74  1.7    ragge 	return ret;
     75  1.7    ragge }
     76  1.7    ragge 
     77  1.9     matt #ifdef _KERNEL
     78  1.8    ragge #define	VAX_LOCK_CHECKS ((1 << IPI_SEND_CNCHAR) | (1 << IPI_DDB))
     79  1.7    ragge #define	__cpu_simple_lock(alp)						\
     80  1.9     matt do {									\
     81  1.7    ragge 	struct cpu_info *__ci = curcpu();				\
     82  1.7    ragge 									\
     83  1.7    ragge 	while (__cpu_simple_lock_try(alp) == 0) {			\
     84  1.7    ragge 		int __s;						\
     85  1.7    ragge 									\
     86  1.8    ragge 		if (__ci->ci_ipimsgs & VAX_LOCK_CHECKS) {		\
     87  1.7    ragge 			__s = splipi();					\
     88  1.7    ragge 			cpu_handle_ipi();				\
     89  1.7    ragge 			splx(__s);					\
     90  1.7    ragge 		}							\
     91  1.7    ragge 	}								\
     92  1.9     matt } while (0)
     93  1.9     matt #else
     94  1.9     matt static __inline void
     95  1.9     matt __cpu_simple_lock(__cpu_simple_lock_t *alp)
     96  1.9     matt {
     97  1.9     matt 	__asm__ __volatile ("1:bbssi $0,%0,1b"
     98  1.9     matt 		: /* No outputs */
     99  1.9     matt 		: "m"(*alp)
    100  1.9     matt 		: "cc");
    101  1.7    ragge }
    102  1.9     matt #endif /* _KERNEL */
    103  1.7    ragge 
    104  1.7    ragge #if 0
    105  1.2  thorpej static __inline void
    106  1.4  thorpej __cpu_simple_lock(__cpu_simple_lock_t *alp)
    107  1.1    ragge {
    108  1.7    ragge 	struct cpu_info *ci = curcpu();
    109  1.7    ragge 
    110  1.7    ragge 	while (__cpu_simple_lock_try(alp) == 0) {
    111  1.7    ragge 		int s;
    112  1.7    ragge 
    113  1.7    ragge 		if (ci->ci_ipimsgs & IPI_SEND_CNCHAR) {
    114  1.7    ragge 			s = splipi();
    115  1.7    ragge 			cpu_handle_ipi();
    116  1.7    ragge 			splx(s);
    117  1.7    ragge 		}
    118  1.7    ragge 	}
    119  1.7    ragge 
    120  1.7    ragge #if 0
    121  1.6    ragge 	__asm__ __volatile ("movl %0,r1;jsb Slock"
    122  1.6    ragge 		: /* No output */
    123  1.6    ragge 		: "g"(alp)
    124  1.6    ragge 		: "r0","r1","cc","memory");
    125  1.7    ragge #endif
    126  1.6    ragge #if 0
    127  1.5     matt 	__asm__ __volatile ("1:;bbssi $0, %0, 1b"
    128  1.1    ragge 		: /* No output */
    129  1.5     matt 		: "m"(*alp));
    130  1.6    ragge #endif
    131  1.1    ragge }
    132  1.7    ragge #endif
    133  1.1    ragge 
    134  1.2  thorpej static __inline void
    135  1.4  thorpej __cpu_simple_unlock(__cpu_simple_lock_t *alp)
    136  1.1    ragge {
    137  1.9     matt #ifdef _KERNEL
    138  1.6    ragge 	__asm__ __volatile ("movl %0,r1;jsb Sunlock"
    139  1.6    ragge 		: /* No output */
    140  1.6    ragge 		: "g"(alp)
    141  1.6    ragge 		: "r1","cc","memory");
    142  1.9     matt #else
    143  1.9     matt 	__asm__ __volatile ("bbcci $0,%0,1f;1:"
    144  1.6    ragge 		: /* No output */
    145  1.9     matt 		: "m"(*alp)
    146  1.9     matt 		: "cc");
    147  1.6    ragge #endif
    148  1.1    ragge }
    149  1.1    ragge 
    150  1.6    ragge #if defined(MULTIPROCESSOR)
    151  1.6    ragge /*
    152  1.6    ragge  * On the Vax, interprocessor interrupts can come in at device priority
    153  1.6    ragge  * level or lower. This can cause some problems while waiting for r/w
    154  1.6    ragge  * spinlocks from a high'ish priority level: IPIs that come in will not
    155  1.6    ragge  * be processed. This can lead to deadlock.
    156  1.6    ragge  *
    157  1.6    ragge  * This hook allows IPIs to be processed while a spinlock's interlock
    158  1.6    ragge  * is released.
    159  1.6    ragge  */
    160  1.6    ragge #define SPINLOCK_SPIN_HOOK						\
    161  1.6    ragge do {									\
    162  1.6    ragge 	struct cpu_info *__ci = curcpu();				\
    163  1.7    ragge 	int __s;							\
    164  1.6    ragge 									\
    165  1.6    ragge 	if (__ci->ci_ipimsgs != 0) {					\
    166  1.6    ragge 		/* printf("CPU %lu has IPIs pending\n",			\
    167  1.6    ragge 		    __ci->ci_cpuid); */					\
    168  1.7    ragge 		__s = splipi();						\
    169  1.6    ragge 		cpu_handle_ipi();					\
    170  1.7    ragge 		splx(__s);						\
    171  1.6    ragge 	}								\
    172  1.6    ragge } while (0)
    173  1.6    ragge #endif /* MULTIPROCESSOR */
    174  1.1    ragge #endif /* _VAX_LOCK_H_ */
    175