macros.h revision 1.5 1 /* $NetBSD: macros.h,v 1.5 1995/10/20 12:55:06 ragge Exp $ */
2
3 /*
4 * Copyright (c) 1994 Ludd, University of Lule}, Sweden.
5 * All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 * 3. All advertising materials mentioning features or use of this software
16 * must display the following acknowledgement:
17 * This product includes software developed at Ludd, University of Lule}.
18 * 4. The name of the author may not be used to endorse or promote products
19 * derived from this software without specific prior written permission
20 *
21 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
22 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
23 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
24 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
25 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
26 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
27 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
28 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
29 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
30 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
31 */
32
33 /* All bugs are subject to removal without further notice */
34
35 #if !defined(_VAX_MACROS_H_) && (defined(STANDALONE) || \
36 (!defined(ASSEMBLER) && defined(_VAX_INLINE_)))
37 #define _VAX_MACROS_H_
38
39 /* Here general macros are supposed to be stored */
40
41 static __inline__ int ffs(int reg){
42 register int val;
43
44 asm __volatile ("ffs $0,$32,%1,%0
45 bneq 1f
46 mnegl $1,%0
47 1: incl %0"
48 : "&=r" (val)
49 : "r" (reg) );
50 return val;
51 }
52
53 static __inline__ void _remque(void*p){
54 asm __volatile ("remque (%0),%0;clrl 4(%0)"
55 :
56 : "r" (p)
57 : "memory" );
58 }
59
60 static __inline__ void _insque(void*p, void*q) {
61 asm __volatile ("insque (%0), (%1)"
62 :
63 : "r" (p),"r" (q)
64 : "memory" );
65 }
66
67 #define bitset(bitnr,var) \
68 ({ asm __volatile ("bbss %0,%1,1f;1:;" \
69 : \
70 : "g" (bitnr), "g" (var)); \
71 })
72
73 #define bitclear(bitnr,var) \
74 ({ asm __volatile ("bbsc %0,%1,1f;1:;" \
75 : \
76 : "g" (bitnr), "g" (var)); \
77 })
78
79 #define bitisset(bitnr,var) \
80 ({ \
81 register int val; \
82 asm __volatile ("clrl %0;bbc %1,%2,1f;incl %0;1:;" \
83 : "=g" (val) \
84 : "g" (bitnr), "g" (var)); \
85 val; \
86 })
87
88 #define bitisclear(bitnr,var) \
89 ({ \
90 register int val; \
91 asm __volatile ("clrl %0;bbs %1,%2,1f;incl %0;1:;" \
92 : "=g" (val) \
93 : "g" (bitnr), "g" (var)); \
94 val; \
95 })
96 static __inline__ void bcopy(const void*from, void*toe, u_int len) {
97 asm __volatile ("movc3 %0,(%1),(%2)"
98 :
99 : "r" (len),"r" (from),"r"(toe)
100 :"r0","r1","r2","r3","r4","r5");
101 }
102
103 static __inline__ void bzero(void*block, u_int len){
104 asm __volatile ("movc5 $0,(%0),$0,%1,(%0)"
105 :
106 : "r" (block), "r" (len)
107 :"r0","r1","r2","r3","r4","r5");
108 }
109
110 static __inline__ int bcmp(const void *b1, const void *b2, size_t len){
111 register ret;
112
113 asm __volatile("cmpc3 %3,(%1),(%2);movl r0,%0"
114 : "=r" (ret)
115 : "r" (b1), "r" (b2), "r" (len)
116 : "r0","r1","r2","r3" );
117 return ret;
118 }
119
120 static __inline__ int locc(int mask, char *cp,u_int size){
121 register ret;
122
123 asm __volatile("locc %1,%2,(%3);movl r0,%0"
124 : "=r" (ret)
125 : "r" (mask),"r"(size),"r"(cp)
126 : "r0","r1" );
127 return ret;
128 }
129
130 static __inline__ int scanc(u_int size, u_char *cp,u_char *table, int mask){
131 register ret;
132
133 asm __volatile("scanc %1,(%2),(%3),%4;movl r0,%0"
134 : "=g"(ret)
135 : "r"(size),"r"(cp),"r"(table),"r"(mask)
136 : "r0","r1","r2","r3" );
137 return ret;
138 }
139
140 static __inline__ int skpc(int mask, int size, char *cp){
141 register ret;
142
143 asm __volatile("skpc %1,%2,(%3);movl r0,%0"
144 : "=g"(ret)
145 : "r"(mask),"r"(size),"r"(cp)
146 : "r0","r1" );
147 return ret;
148 }
149 #if 0
150 static __inline__ int imin(int a, int b){
151 asm __volatile("cmpl %0,%2;bleq 1f;movl %2,%0;1:"
152 : "=r"(a)
153 : "r"(a),"r"(b) );
154 return a;
155 }
156
157 static __inline__ int imax(int a, int b){
158 asm __volatile("cmpl %0,%2;bgeq 1f;movl %2,%0;1:"
159 : "=r"(a)
160 : "r"(a),"r"(b) );
161 return a;
162 }
163
164 static __inline__ int min(int a, int b){
165 asm __volatile("cmpl %0,%2;bleq 1f;movl %2,%0;1:"
166 : "=r"(a)
167 : "r"(a),"r"(b) );
168 return a;
169 }
170
171 static __inline__ int max(int a, int b){
172 asm __volatile("cmpl %0,%2;bgeq 1f;movl %2,%0;1:"
173 : "=r"(a)
174 : "r"(a),"r"(b) );
175 return a;
176 }
177 #endif
178
179 #define waitabit(tid) \
180 ({ \
181 asm __volatile ("mfpr $27,r0;addl2 %0,r0;1:;mfpr $27,r1; \
182 cmpl r0,r1;bneq 1b;" \
183 : \
184 : "g"(tid) \
185 : "r0","r1"); \
186 })
187
188 static __inline__ void blkcpy(const void*from, void*to, u_int len) {
189 asm __volatile("
190 movl %0,r1
191 movl %1,r3
192 movl %2,r6
193 jbr 2f
194 1: subl2 r0,r6
195 movc3 r0,(r1),(r3)
196 2: movzwl $65535,r0
197 cmpl r6,r0
198 jgtr 1b
199 movc3 r6,(r1),(r3)"
200 :
201 : "g" (from), "g" (to), "g" (len)
202 : "r0","r1","r2","r3","r4","r5", "r6" );
203 }
204
205 static __inline__ void blkclr(void *blk, int len) {
206 asm __volatile("
207 movl %0, r3
208 movl %1, r6
209 jbr 2f
210 1: subl2 r0, r6
211 movc5 $0,(r3),$0,r0,(r3)
212 2: movzwl $65535,r0
213 cmpl r6, r0
214 jgtr 1b
215 movc5 $0,(r3),$0,r6,(r3)"
216 :
217 : "g" (blk), "g" (len)
218 : "r0","r1","r2","r3","r4","r5", "r6" );
219 }
220
221 #endif /* _VAX_MACROS_H_ */
222