qdreg.h revision 1.2
1 /* $NetBSD: qdreg.h,v 1.2 2002/09/29 23:23:59 wiz Exp $ */ 2 /*- 3 * Copyright (c) 1982, 1986 The Regents of the University of California. 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. All advertising materials mentioning features or use of this software 15 * must display the following acknowledgement: 16 * This product includes software developed by the University of 17 * California, Berkeley and its contributors. 18 * 4. Neither the name of the University nor the names of its contributors 19 * may be used to endorse or promote products derived from this software 20 * without specific prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 23 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 25 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 26 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 27 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 28 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 29 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 30 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 31 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 32 * SUCH DAMAGE. 33 * 34 * @(#)qdreg.h 7.1 (Berkeley) 5/9/91 35 */ 36 37 /************************************************************************ 38 * * 39 * Copyright (c) 1985, 1986 by * 40 * Digital Equipment Corporation, Maynard, MA * 41 * All rights reserved. * 42 * * 43 * This software is furnished under a license and may be used and * 44 * copied only in accordance with the terms of such license and * 45 * with the inclusion of the above copyright notice. This * 46 * software or any other copies thereof may not be provided or * 47 * otherwise made available to any other person. No title to and * 48 * ownership of the software is hereby transferred. * 49 * * 50 * The information in this software is subject to change without * 51 * notice and should not be construed as a commitment by Digital * 52 * Equipment Corporation. * 53 * * 54 * Digital assumes no responsibility for the use or reliability * 55 * of its software on equipment which is not supplied by Digital. * 56 * * 57 ************************************************************************/ 58 59 /* Dragon ADDER reg map */ 60 /* ADDER register bit definitions */ 61 /* Y_SCROLL_CONSTANT */ 62 63 #define SCROLL_ERASE 0x2000 64 #define ADDER_SCROLL_DOWN 0x1000 65 66 /* ADDER status and interrupt enable registers [1], [2], [3] */ 67 68 #define DISABLE 0x0000 69 #define PAUSE_COMPLETE 0x0001 70 #define FRAME_SYNC 0x0002 71 #define INIT_COMPLETE 0x0004 72 #define RASTEROP_COMPLETE 0x0008 73 74 #define ADDRESS_COMPLETE 0x0010 75 #define RX_READY 0x0020 76 #define TX_READY 0x0040 77 #define ID_SCROLL_READY 0x0080 78 79 #define TOP_CLIP 0x0100 80 #define BOTTOM_CLIP 0x0200 81 #define LEFT_CLIP 0x0400 82 #define RIGHT_CLIP 0x0800 83 #define NO_CLIP 0x1000 84 #define VSYNC 0x2000 85 86 /* ADDER command register [8], [10] */ 87 88 #define OCR_zero 0x0000 89 #define Z_BLOCK0 0x0000 90 #define OCRA 0x0000 91 #define OCRB 0x0004 92 #define RASTEROP 0x02c0 93 #define PBT 0x03c0 94 #define BTPZ 0x0bb0 95 #define PTBZ 0x07a0 96 #define DTE 0x0400 97 #define S1E 0x0800 98 #define S2E 0x1000 99 #define VIPER_Z_LOAD 0x01A0 100 #define ID_LOAD 0x0100 101 #define CANCEL 0x0000 102 #define LF_R1 0x0000 103 #define LF_R2 0x0010 104 #define LF_R3 0x0020 105 #define LF_R4 0x0030 106 107 /* ADDER rasterop mode register [9] */ 108 109 #define NORMAL 0x0000 110 #define LINEAR_PATTERN 0x0002 111 #define X_FILL 0x0003 112 #define Y_FILL 0x0007 113 #define BASELINE 0x0008 114 #define HOLE_ENABLE 0x0010 115 #define SRC_1_INDEX_ENABLE 0x0020 116 #define DST_INDEX_ENABLE 0x0040 117 #define DST_WRITE_ENABLE 0x0080 118 119 /* ADDER source 2 size register */ 120 121 #define NO_TILE 0x0080 122 123 /* External registers base addresses */ 124 125 #define CS_UPDATE_MASK 0x0060 126 #define CS_SCROLL_MASK 0x0040 127 128 /* VIPER registers */ 129 130 #define RESOLUTION_MODE 0x0080 131 #define MEMORY_BUS_WIDTH 0x0081 132 #define PLANE_ADDRESS 0x0083 133 #define LU_FUNCTION_R1 0x0084 134 #define LU_FUNCTION_R2 0x0085 135 #define LU_FUNCTION_R3 0x0086 136 #define LU_FUNCTION_R4 0x0087 137 #define MASK_1 0x0088 138 #define MASK_2 0x0089 139 #define SOURCE 0x008a 140 #define SOURCE_Z 0x0000 141 #define BACKGROUND_COLOR 0x008e 142 #define BACKGROUND_COLOR_Z 0x000C 143 #define FOREGROUND_COLOR 0x008f 144 #define FOREGROUND_COLOR_Z 0x0004 145 #define SRC1_OCR_A 0x0090 146 #define SRC2_OCR_A 0x0091 147 #define DST_OCR_A 0x0092 148 #define SRC1_OCR_B 0x0094 149 #define SRC2_OCR_B 0x0095 150 #define DST_OCR_B 0x0096 151 152 /* VIPER scroll registers */ 153 154 #define SCROLL_CONSTANT 0x0082 155 #define SCROLL_FILL 0x008b 156 #define SCROLL_FILL_Z 0x0008 157 #define LEFT_SCROLL_MASK 0x008c 158 #define RIGHT_SCROLL_MASK 0x008d 159 160 /* VIPER register bit definitions */ 161 162 #define EXT_NONE 0x0000 163 #define EXT_SOURCE 0x0001 164 #define EXT_M1_M2 0x0002 165 #define INT_NONE 0x0000 166 #define INT_SOURCE 0x0004 167 #define INT_M1_M2 0x0008 168 #define ID 0x0010 169 #define NO_ID 0x0000 170 #define WAIT 0x0020 171 #define NO_WAIT 0x0000 172 #define BAR_SHIFT_DELAY WAIT 173 #define NO_BAR_SHIFT_DELAY NO_WAIT 174 175 176 /* VIPER logical function unit codes */ 177 178 #define LF_ZEROS 0x0000 179 #define LF_D_XOR_S 0x0006 180 #define LF_SOURCE 0x000A 181 #define LF_D_OR_S 0x000E 182 #define LF_ONES 0x000F 183 #define INV_M1_M2 0x0030 184 #define FULL_SRC_RESOLUTION 0X00C0 /* makes second pass like first pass */ 185 186 /* VIPER scroll register [2] */ 187 188 #define SCROLL_DISABLE 0x0040 189 #define SCROLL_ENABLE 0x0020 190 #define VIPER_LEFT 0x0000 191 #define VIPER_RIGHT 0x0010 192 #define VIPER_UP 0x0040 193 #define VIPER_DOWN 0x0000 194 195 /* Adder scroll register */ 196 197 #define ADDER_UP 0x0000 198 #define ADDER_DOWN 0x1000 199 200 /* Misc scroll definitions */ 201 202 #define UP 0 203 #define DOWN 1 204 #define LEFT 2 205 #define RIGHT 3 206 #define NODIR 4 207 #define SCROLL_VMAX 31 208 #define SCROLL_HMAX 15 209 #define NEW 2 210 #define OLD 1 211 #define BUSY 1 212 #define DRAG 1 213 #define SCROLL 0 214 215 /* miscellaneous defines */ 216 217 #define ALL_PLANES 0xffffffff 218 #define UNITY 0x1fff /* Adder scale factor */ 219 #define MAX_SCREEN_X 1024 220 #define MAX_SCREEN_Y 864 221 #define FONT_HEIGHT 32 222 223 struct adder { 224 225 /* adder control registers */ 226 227 u_short register_address; /* ADDER reg pntr for use by DGA */ 228 u_short request_enable; /* DMA request enables */ 229 u_short interrupt_enable; /* interrupt enables */ 230 u_short status; /* ADDER status bits */ 231 u_short reserved1; /* test function only */ 232 u_short spare1; /* spare address (what else?) */ 233 234 u_short reserved2; /* test function only */ 235 u_short id_data; /* data path to I/D bus */ 236 u_short command; /* ADDER chip command register */ 237 u_short rasterop_mode; /* sets rasterop execution modes */ 238 u_short cmd; /* duplicate path to above cmd reg */ 239 u_short reserved3; /* test function only */ 240 241 /* scroll registers */ 242 243 u_short ID_scroll_data; /* I/D bus scroll data */ 244 u_short ID_scroll_command; /* I/D bus scroll command */ 245 u_short scroll_x_min; /* X scroll min - left boundary */ 246 u_short scroll_x_max; /* X scroll max - right boundary */ 247 u_short scroll_y_min; /* Y scroll min - upper boundary */ 248 u_short scroll_y_max; /* Y scroll max - lower boundary */ 249 u_short pause; /* Y coord to set stat when scanned */ 250 u_short y_offset_pending; /* vertical scroll control */ 251 u_short y_scroll_constant; 252 253 /* update control registers */ 254 255 u_short x_index_pending; /* x pending index */ 256 u_short y_index_pending; /* y pending index */ 257 u_short x_index_new; /* new x index */ 258 u_short y_index_new; /* new y index */ 259 u_short x_index_old; /* old x index */ 260 u_short y_index_old; /* old y index */ 261 u_short x_clip_min; /* left clipping boundary */ 262 u_short x_clip_max; /* right clipping boundary */ 263 u_short y_clip_min; /* upper clipping boundary */ 264 u_short y_clip_max; /* lower clipping boundary */ 265 u_short spare2; /* spare address (another!) */ 266 267 /* rasterop control registers */ 268 269 u_short source_1_dx; /* source #1 x vector */ 270 u_short source_1_dy; /* source #1 y vector*/ 271 u_short source_1_x; /* source #1 x origin */ 272 u_short source_1_y; /* source #1 y origin */ 273 u_short destination_x; /* destination x origin */ 274 u_short destination_y; /* destination y origin */ 275 u_short fast_dest_dx; /* destination x fast vector */ 276 u_short fast_dest_dy; /* destination y fast vector */ 277 u_short slow_dest_dx; /* destination x slow vector */ 278 u_short slow_dest_dy; /* destination y slow vector */ 279 u_short fast_scale; /* scale factor for fast vector */ 280 u_short slow_scale; /* scale factor for slow vector */ 281 u_short source_2_x; /* source #2 x origin */ 282 u_short source_2_y; /* source #2 y origin */ 283 u_short source_2_size; /* source #2 height & width */ 284 u_short error_1; /* error regs (?) */ 285 u_short error_2; 286 287 /* screen format control registers */ 288 289 u_short y_scan_count_0; /* y scan counts for vert timing */ 290 u_short y_scan_count_1; 291 u_short y_scan_count_2; 292 u_short y_scan_count_3; 293 u_short x_scan_conf; /* x scan configuration */ 294 u_short x_limit; 295 u_short y_limit; 296 u_short x_scan_count_0; /* x scan count for horiz timing */ 297 u_short x_scan_count_1; 298 u_short x_scan_count_2; 299 u_short x_scan_count_3; 300 u_short x_scan_count_4; 301 u_short x_scan_count_5; 302 u_short x_scan_count_6; 303 u_short sync_phase_adj; /* sync phase (horiz sync count) */ 304 }; 305 306 /*--------------------- 307 * DUART definitions */ 308 309 /* command definitions */ 310 311 #define EN_RCV 0x01 312 #define DIS_RCV 0x02 313 #define EN_XMT 0x04 314 #define DIS_XMT 0x08 315 #define RESET_M 0x10 316 #define RESET_RCV 0x20 317 #define RESET_XMT 0x30 318 #define RESET_ERR 0x40 319 #define RESET_BD 0x50 320 #define START_BREAK 0x60 321 #define STOP_BREAK 0x70 322 323 /* interupt bit definitions */ 324 325 #define EI_XMT_A 0x01 326 #define EI_RCV_A 0x02 327 #define EI_XMT_B 0x10 328 #define EI_RCV_B 0x20 329 330 #define XMT_RDY_A 0x01 331 #define RCV_RDY_A 0x02 332 #define XMT_RDY_B 0x10 333 #define RCV_RDY_B 0x20 334 335 /* status register bit definitions */ 336 337 #define RCV_RDY 0x01 338 #define FIFO_FULL 0x02 339 #define XMT_RDY 0x04 340 #define XMT_EMT 0x08 341 #define OVER_ERR 0x10 342 #define ERR_PARITY 0x20 343 #define FRAME_ERR 0x40 344 #define RCVD_BREAK 0x80 345 346 347 struct duart { 348 349 /* channel A - LK201 */ 350 351 short modeA; /* ch.A mode reg (read/write) */ 352 short statusA; /* ch.A status reg (read) */ 353 #define clkselA statusA /* ch.A clock slect reg (write) */ 354 short cmdA; /* ch.A command reg (write) */ 355 short dataA; /* rcv/xmt data ch.A (read/write) */ 356 short inchng; /* input change state reg (read) */ 357 #define auxctl inchng /* auxiliary control reg (write) */ 358 short istatus; /* interrupt status reg (read) */ 359 #define imask istatus /* interrupt mask reg (write) */ 360 short CThi; /* counter/timer hi byte (read) */ 361 #define CTRhi CThi /* counter/timer hi reg (write) */ 362 short CTlo; /* counter/timer lo byte (read) */ 363 #define CTRlo CTlo /* counter/timer lo reg (write) */ 364 365 /* channel B - pointing device */ 366 367 short modeB; /* ch.B mode reg (read/write) */ 368 short statusB; /* ch.B status reg (read) */ 369 #define clkselB statusB /* ch.B clock select reg (write) */ 370 short cmdB; /* ch.B command reg (write) */ 371 short dataB; /* ch.B rcv/xmt data (read/write) */ 372 short rsrvd; 373 short inport; /* input port (read) */ 374 #define outconf inport /* output port config reg (write) */ 375 short strctr; /* start counter command (read) */ 376 #define setbits setctr /* output bits set command (write) */ 377 short stpctr; /* stop counter command (read) */ 378 #define resetbits stpctr /* output bits reset cmd (write) */ 379 380 }; 381
Indexes created Mon Sep 29 21:09:56 GMT 2025