1 1.15 andvar /* $NetBSD: scb.h,v 1.15 2022/04/10 09:50:45 andvar Exp $ */ 2 1.2 cgd 3 1.1 ragge /* 4 1.1 ragge * Copyright (c) 1994 Ludd, University of Lule}, Sweden. 5 1.1 ragge * All rights reserved. 6 1.1 ragge * 7 1.1 ragge * Redistribution and use in source and binary forms, with or without 8 1.1 ragge * modification, are permitted provided that the following conditions 9 1.1 ragge * are met: 10 1.1 ragge * 1. Redistributions of source code must retain the above copyright 11 1.1 ragge * notice, this list of conditions and the following disclaimer. 12 1.1 ragge * 2. Redistributions in binary form must reproduce the above copyright 13 1.1 ragge * notice, this list of conditions and the following disclaimer in the 14 1.1 ragge * documentation and/or other materials provided with the distribution. 15 1.1 ragge * 16 1.1 ragge * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 17 1.1 ragge * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 18 1.1 ragge * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 19 1.1 ragge * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 20 1.1 ragge * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 21 1.1 ragge * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 22 1.1 ragge * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 23 1.1 ragge * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 24 1.1 ragge * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 25 1.1 ragge * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 26 1.1 ragge */ 27 1.13 matt 28 1.6 matt #ifndef _VAX_SCB_H 29 1.6 matt #define _VAX_SCB_H 30 1.1 ragge 31 1.13 matt #include <sys/evcnt.h> 32 1.13 matt 33 1.4 ragge /* 34 1.4 ragge * Definition of the System Control Block. More about it can be 35 1.4 ragge * found in the Vax Architecture Reference Manual, section 6.6. 36 1.4 ragge */ 37 1.1 ragge struct scb { 38 1.4 ragge void *scb_unused; /* First unused vector */ 39 1.4 ragge void *scb_mcheck; 40 1.4 ragge void *scb_kspinv; 41 1.4 ragge void *scb_powfail; 42 1.4 ragge void *scb_privinst; /* 10 Privileged Instruction fault */ 43 1.4 ragge void *scb_xfcinst; 44 1.4 ragge void *scb_resop; 45 1.4 ragge void *scb_resad; 46 1.4 ragge void *scb_accessv; /* 20 Access Control violation fault */ 47 1.4 ragge void *scb_transinv; 48 1.4 ragge void *scb_trace; 49 1.4 ragge void *scb_breakp; 50 1.4 ragge void *scb_compat; /* 30 Compatibility instruction fault */ 51 1.4 ragge void *scb_arith; 52 1.4 ragge void *scb_unused1; 53 1.4 ragge void *scb_unused2; 54 1.4 ragge void *scb_chmk; /* 40 CHMK */ 55 1.4 ragge void *scb_chme; 56 1.4 ragge void *scb_chms; 57 1.4 ragge void *scb_chmu; 58 1.4 ragge void *scb_sbisilo; /* 50 SBI Silo compare */ 59 1.4 ragge void *scb_cmrd; 60 1.4 ragge void *scb_sbialert; 61 1.4 ragge void *scb_sbifault; 62 1.4 ragge void *scb_memwtimo; /* 60 Memory write timeout */ 63 1.4 ragge void *scb_unused3; 64 1.4 ragge void *scb_unused4; 65 1.4 ragge void *scb_unused5; 66 1.4 ragge void *scb_unused6; /* 70 unused */ 67 1.4 ragge void *scb_unused7; 68 1.4 ragge void *scb_unused8; 69 1.4 ragge void *scb_unused9; 70 1.4 ragge void *scb_unused10; /* 80 unused */ 71 1.4 ragge void *scb_softint1; 72 1.4 ragge void *scb_softint2; 73 1.4 ragge void *scb_softint3; 74 1.4 ragge void *scb_softint4; /* 90 Software interrupt level 4 */ 75 1.4 ragge void *scb_softint5; 76 1.4 ragge void *scb_softint6; 77 1.4 ragge void *scb_softint7; 78 1.4 ragge void *scb_softint8; /* A0 Software interrupt level 8 */ 79 1.4 ragge void *scb_softint9; 80 1.4 ragge void *scb_softinta; 81 1.4 ragge void *scb_softintb; 82 1.4 ragge void *scb_softintc; /* B0 Software interrupt level C */ 83 1.4 ragge void *scb_softintd; 84 1.4 ragge void *scb_softinte; 85 1.4 ragge void *scb_softintf; 86 1.4 ragge void *scb_timer; /* C0 Interval timer */ 87 1.4 ragge void *scb_unused11; 88 1.4 ragge void *scb_unused12; 89 1.4 ragge void *scb_unused13; 90 1.4 ragge void *scb_unused14; /* D0 Unused */ 91 1.4 ragge void *scb_unused15; 92 1.4 ragge void *scb_unused16; 93 1.4 ragge void *scb_unused17; 94 1.4 ragge void *scb_unused18; /* E0 Unused */ 95 1.4 ragge void *scb_unused19; 96 1.4 ragge void *scb_unused20; 97 1.4 ragge void *scb_unused21; 98 1.4 ragge void *scb_csrint; 99 1.4 ragge void *scb_cstint; /* F0 Console storage transmit interrupt */ 100 1.4 ragge void *scb_ctrint; 101 1.4 ragge void *scb_cttint; 102 1.4 ragge struct ivec_dsp *scb_nexvec[4][16]; /* Nexus interrupt vectors */ 103 1.1 ragge }; 104 1.1 ragge 105 1.5 ragge #define SCB_KSTACK 0 106 1.5 ragge #define SCB_ISTACK 1 107 1.5 ragge 108 1.11 ragge #define vecnum(bus, ipl, tr) (256+(ipl-0x14)*64+tr*4+bus*256) 109 1.9 ragge 110 1.7 matt /* 111 1.7 matt * This struct is used when setting up interrupt vectors dynamically. 112 1.15 andvar * It put a opaque 32 bit quantity on the stack and also has a placeholder 113 1.7 matt * for evcnt structure. 114 1.7 matt */ 115 1.7 matt struct ivec_dsp { 116 1.7 matt char pushr; /* pushr */ 117 1.7 matt char pushrarg; /* $0x3f */ 118 1.7 matt char jsb; 119 1.7 matt char mode; 120 1.7 matt long displacement; 121 1.9 ragge void (*hoppaddr)(void *); 122 1.7 matt void *pushlarg; 123 1.7 matt struct evcnt *ev; 124 1.7 matt }; 125 1.7 matt 126 1.3 ragge #ifdef _KERNEL 127 1.7 matt extern const struct ivec_dsp idsptch; 128 1.3 ragge extern struct scb *scb; 129 1.8 matt extern struct ivec_dsp *scb_vec; 130 1.10 matt extern struct evcnt devipl_intrcnts[4]; /* IPL 2[0123] */ 131 1.5 ragge 132 1.12 matt paddr_t scb_init (paddr_t); 133 1.12 matt int scb_vecref (int *, int *); 134 1.12 matt void scb_fake (int, int); 135 1.12 matt void scb_vecalloc (int, void(*)(void *), void *, int, struct evcnt *); 136 1.6 matt #endif /* _KERNEL */ 137 1.6 matt 138 1.6 matt #endif /* _VAX_SCB_H */ 139