vsbus.h revision 1.2 1 /* $NetBSD: vsbus.h,v 1.2 1998/05/22 09:49:08 ragge Exp $ */
2 /*
3 * Copyright (c) 1996 Ludd, University of Lule}, Sweden.
4 * All rights reserved.
5 *
6 * This code is derived from software contributed to Ludd by Bertram Barth.
7 *
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions
10 * are met:
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
16 * 3. All advertising materials mentioning features or use of this software
17 * must display the following acknowledgement:
18 * This product includes software developed at Ludd, University of
19 * Lule}, Sweden and its contributors.
20 * 4. The name of the author may not be used to endorse or promote products
21 * derived from this software without specific prior written permission
22 *
23 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
24 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
25 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
26 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
27 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
28 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
29 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
30 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
32 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 */
34
35 /*
36 * Generic definitions for the (virtual) vsbus. contains common info
37 * used by all VAXstations.
38 */
39 struct confargs {
40 char ca_name[16]; /* device name */
41 int ca_intslot; /* device interrupt-slot */
42 int ca_intpri; /* device interrupt "priority" */
43 int ca_intvec; /* interrup-vector offset */
44 int ca_intbit; /* bit in interrupt-register */
45 int ca_ioaddr; /* device hardware I/O address */
46
47 int ca_aux1; /* additional info (DMA, etc.) */
48 int ca_aux2;
49 int ca_aux3;
50 int ca_aux4;
51 int ca_aux5;
52 int ca_aux6;
53 int ca_aux7;
54 int ca_aux8;
55
56 #define ca_recvslot ca_intslot /* DC/DZ: Receiver configuration */
57 #define ca_recvpri ca_intpri
58 #define ca_recvvec ca_intvec
59 #define ca_recvbit ca_intbit
60 #define ca_xmitslot ca_aux1 /* DC/DZ: transmitter configuration */
61 #define ca_xmitpri ca_aux2 /* DC/DZ: */
62 #define ca_xmitvec ca_aux3
63 #define ca_xmitbit ca_aux4
64 #define ca_dcflags ca_aux5
65
66 #define ca_dareg ca_aux1 /* SCSI: DMA address register */
67 #define ca_dcreg ca_aux2 /* SCSI: DMA byte count register */
68 #define ca_ddreg ca_aux3 /* SCSI: DMA transfer direction */
69 #define ca_dbase ca_aux4 /* SCSI: DMA buffer address */
70 #define ca_dsize ca_aux5 /* SCSI: DMA buffer size */
71 #define ca_dflag ca_aux6 /* SCSI: DMA flags (eg. shared) */
72 #define ca_idval ca_aux7 /* SCSI: host-ID to use/set */
73 #define ca_idreg ca_aux8 /* SCSI: host-ID port register */
74
75 #define ca_enaddr ca_aux1 /* LANCE: Ethernet address in ROM */
76 #define ca_leflags ca_aux2
77 };
78
79 struct vsbus_attach_args {
80 int va_type;
81 };
82
83 /*
84 * Some chip addresses and constants, same on all VAXstations.
85 */
86 #define NI_ADDR 0x20090000 /* Ethernet address */
87 #define DZ_CSR 0x200a0000 /* DZ11-compatible chip csr */
88 #define VS_CLOCK 0x200b0000 /* clock chip address */
89 #define NI_BASE 0x200e0000 /* LANCE CSRs */
90 #define NI_IOSIZE (128 * NBPG) /* IO address size */
91 #define VS_REGS 0x20080000 /* Misc cpu internal regs */
92
93 /*
94 * interrupt vector numbers
95 */
96 #define IVEC_BASE 0x20040020
97 #define IVEC_SR 0x000002C0
98 #define INR_SR 7
99 #define IVEC_ST 0x000002C4
100 #define INR_ST 6
101 #define IVEC_NP 0x00000250
102 #define INR_NP 5
103 #define IVEC_NS 0x00000254
104 #define INR_NS 4
105 #define IVEC_VF 0x00000244
106 #define INR_VF 3
107 #define IVEC_VS 0x00000248
108 #define INR_VS 2
109 #define IVEC_SC 0x000003F8
110 #define INR_SC 1
111 #define IVEC_DC 0x000003FC
112 #define INR_DC 0
113
114 caddr_t dz_regs; /* On-board serial line */
115 caddr_t le_iomem; /* base addr of RAM -- CPU's view */
116 short *lance_csr; /* LANCE CSR virtual address */
117 int *lance_addr; /* Ethernet address */
118 struct vs_cpu *vs_cpu; /* Common CPU registers */
119
120 void vsbus_intr_enable __P((int));
121 void vsbus_intr_disable __P((int));
122 void vsbus_intr_attach __P((int, void(*)(int), int));
123
124 int vsbus_lockDMA __P((struct confargs *));
125 int vsbus_unlockDMA __P((struct confargs *));
126
127