qvareg.h revision 1.1
1 /* $NetBSD: qvareg.h,v 1.1 2015/07/05 03:07:21 matt Exp $ */ 2 3 /* 4 * Copyright (c) 2015 Charles H. Dickman. All rights reserved. 5 * Derived from sgimips port 6 * Copyright (c) 1996, 1997 Philip L. Budne. 7 * Copyright (c) 1993 Philip A. Nelson. 8 * All rights reserved. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by Philip A. Nelson. 21 * 4. The name of Philip A. Nelson may not be used to endorse or promote 22 * products derived from this software without specific prior written 23 * permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY PHILIP NELSON ``AS IS'' AND ANY EXPRESS OR 26 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 27 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 28 * IN NO EVENT SHALL PHILIP NELSON BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 29 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 30 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; 31 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 32 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR 33 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF 34 * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 35 * 36 * scnreg.h: definitions for qvss scn2681 DUART 37 */ 38 39 /* 40 * register offsets 41 */ 42 43 /* per-channel regs (channel B's at SCN_REG(8-11)) */ 44 #define CH_MR(x) SCN_REG(0 + 8*(x)) /* rw mode register */ 45 #define CH_SR(x) SCN_REG(1 + 8*(x)) /* ro status register */ 46 #define CH_CSR(x) SCN_REG(1 + 8*(x)) /* wo clock select reg */ 47 #define CH_CR(x) SCN_REG(2 + 8*(x)) /* wo command reg */ 48 #define CH_DAT(x) SCN_REG(3 + 8*(x)) /* rw data reg */ 49 50 /* duart-wide regs */ 51 #define DU_IPCR SCN_REG(4) /* ro input port change reg */ 52 #define DU_ACR SCN_REG(4) /* wo aux control reg */ 53 #define DU_ISR SCN_REG(5) /* ro interrupt stat reg */ 54 #define DU_IMR SCN_REG(5) /* wo interrupt mask reg */ 55 #define DU_CTUR SCN_REG(6) /* rw counter timer upper reg */ 56 #define DU_CTLR SCN_REG(7) /* rw counter timer lower reg */ 57 /* SCN_REG(8-11) channel b (see above) */ 58 /* SCN_REG(12): reserved */ 59 #define DU_IP SCN_REG(13) /* ro input port */ 60 #define DU_OPCR SCN_REG(13) /* wo output port cfg reg */ 61 #define DU_CSTRT SCN_REG(14) /* ro start C/T cmd */ 62 #define DU_OPSET SCN_REG(14) /* wo output port set */ 63 #define DU_CSTOP SCN_REG(15) /* ro stop C/T cmd */ 64 #define DU_OPCLR SCN_REG(15) /* wo output port reset */ 65 66 67 68 struct qvaux_ch_regs { 69 bus_addr_t qr_mr; 70 bus_addr_t qr_sr; 71 bus_addr_t qr_csr; 72 bus_addr_t qr_cr; 73 bus_addr_t qr_dat; 74 }; 75 76 struct qvaux_regs { 77 bus_addr_t qr_ipcr; 78 bus_addr_t qr_acr; 79 bus_addr_t qr_isr; 80 bus_addr_t qr_imr; 81 bus_addr_t qr_ctur; 82 bus_addr_t qr_ctlr; 83 bus_addr_t qr_ip; 84 bus_addr_t qr_opcr; 85 bus_addr_t qr_cstrt; 86 bus_addr_t qr_opset; 87 bus_addr_t qr_cstop; 88 bus_addr_t qr_opclr; 89 struct qvaux_ch_regs qr_ch_regs[2]; 90 91 bus_addr_t qr_firstreg; 92 bus_addr_t qr_winsize; 93 }; 94 95 /* 96 * Data Values 97 */ 98 99 /* 100 * MR (mode register) -- per channel 101 */ 102 103 /* MR0 (scn26c92 only) need to use CR_CMD_MR0 before access */ 104 #define MR0_MODE 0x07 /* extended baud rate mode (MR0A only) */ 105 #define MR0_TXINT 0x30 /* Tx int threshold */ 106 #define MR0_RXINT 0x40 /* Rx int threshold (along with MR1_FFULL) */ 107 #define MR0_RXWD 0x80 /* Rx watchdog (8 byte-times after last rx) */ 108 109 #define MR0_MODE_0 0x00 /* Normal mode */ 110 #define MR0_MODE_1 0x01 /* Extended mode 1 */ 111 #define MR0_MODE_2 0x04 /* Extended mode 2 */ 112 113 #define MR0_TXINT_EMPTY 0x00 /* TxInt when 8 FIFO bytes empty (default) */ 114 #define MR0_TXINT_4 0x10 /* TxInt when 4 or more FIFO bytes empty */ 115 #define MR0_TXINT_6 0x20 /* TxInt when 6 or more FIFO bytes empty */ 116 #define MR0_TXINT_TXRDY 0x30 /* TxInt when 1 or more FIFO bytes empty */ 117 118 /* MR1 (need to use CR_CMD_MR1 before each access) */ 119 #define MR1_CS5 0x00 120 #define MR1_CS6 0x01 121 #define MR1_CS7 0x02 122 #define MR1_CS8 0x03 123 124 #define MR1_PEVEN 0x00 125 #define MR1_PODD 0x04 126 #define MR1_PNONE 0x10 127 128 #define MR1_RXBLK 0x20 /* "block" error mode */ 129 #define MR1_FFULL 0x40 /* wait until FIFO full for rxint (cf MR0) */ 130 #define MR1_RXRTS 0x80 /* auto RTS input flow ctrl */ 131 132 /* MR2 (any access to MR after MR1) */ 133 #define MR2_STOP 0x0f /* mask for stop bits */ 134 #define MR2_STOP1 0x07 135 #define MR2_STOP2 0x0f 136 137 #define MR2_TXCTS 0x10 /* transmitter follows CTS */ 138 #define MR2_TXRTS 0x20 /* RTS follows transmitter */ 139 #define MR2_MODE 0xc0 /* mode mask */ 140 141 /* 142 * IP (input port) 143 */ 144 #define IP_IP0 0x01 145 #define IP_IP1 0x02 146 #define IP_IP2 0x04 147 #define IP_IP3 0x08 148 #define IP_IP4 0x10 149 #define IP_IP5 0x20 150 #define IP_IP6 0x40 151 /* D7 is always 1 */ 152 153 /* 154 * ACR (Aux Control Register) 155 */ 156 157 #define ACR_DELTA_IP0 0x01 /* enable IP0 delta interrupt */ 158 #define ACR_DELTA_IP1 0x02 /* enable IP1 delta interrupt */ 159 #define ACR_DELTA_IP2 0x04 /* enable IP2 delta interrupt */ 160 #define ACR_DELTA_IP3 0x08 /* enable IP3 delta interrupt */ 161 #define ACR_CT 0x70 /* counter/timer mode (ACT_CT_xxx) */ 162 #define ACR_BRG 0x80 /* baud rate generator speed set */ 163 164 /* counter/timer mode */ 165 #define ACR_CT_CEXT 0x00 /* counter: external (IP2) */ 166 #define ACR_CT_CTXA 0x10 /* counter: TxCA x 1 */ 167 #define ACR_CT_CTXB 0x20 /* counter: TxCB x 1 */ 168 #define ACR_CT_CCLK 0x30 /* counter: X1/CLK div 16 */ 169 #define ACR_CT_TEXT1 0x40 /* timer: external (IP2) */ 170 #define ACR_CT_TEXT16 0x50 /* timer: external (IP2) div 16 */ 171 #define ACR_CT_TCLK1 0x60 /* timer: X1/CLK */ 172 #define ACR_CT_TCLK16 0x70 /* timer: X1/CLK div 16 */ 173 174 /* 175 * IPCR (Input Port Change Register) -- per channel 176 */ 177 #define IPCR_IP0 0x01 178 #define IPCR_IP1 0x02 179 #define IPCR_IP2 0x04 180 #define IPCR_IP3 0x08 181 #define IPCR_DELTA_IP0 0x10 182 #define IPCR_DELTA_IP1 0x20 183 #define IPCR_DELTA_IP2 0x40 184 #define IPCR_DELTA_IP3 0x80 185 186 /* 187 * output port config register 188 * if bit(s) clear OP line follows OP register OPn bit 189 */ 190 191 #define OPCR_OP7_TXRDYB 0x80 /* OP7: TxRDYB */ 192 #define OPCR_OP6_TXRDYA 0x40 /* OP6: TxRDYA */ 193 #define OPCR_OP5_RXRDYB 0x20 /* OP5: ch B RxRDY/FFULL */ 194 #define OPCR_OP4_RXRDYA 0x10 /* OP4: ch A RxRDY/FFULL */ 195 196 #define OPCR_OP3 0xC0 /* OP3: mask */ 197 #define OPCR_OP2 0x03 /* OP2: mask */ 198 199 /* 200 * output port 201 */ 202 #define OP_OP0 0x01 203 #define OP_OP1 0x02 204 #define OP_OP2 0x04 205 #define OP_OP3 0x08 206 #define OP_OP4 0x10 207 #define OP_OP5 0x20 208 #define OP_OP6 0x40 209 #define OP_OP7 0x80 210 211 /* 212 * CR (command register) -- per channel 213 */ 214 215 /* bits (may be or'ed together, with a command) */ 216 #define CR_ENA_RX 0x01 217 #define CR_DIS_RX 0x02 218 #define CR_ENA_TX 0x04 219 #define CR_DIS_TX 0x08 220 221 /* commands */ 222 #define CR_CMD_NOP 0x00 223 #define CR_CMD_MR1 0x10 224 #define CR_CMD_RESET_RX 0x20 225 #define CR_CMD_RESET_TX 0x30 226 #define CR_CMD_RESET_ERR 0x40 227 #define CR_CMD_RESET_BRK 0x50 228 #define CR_CMD_START_BRK 0x60 229 #define CR_CMD_STOP_BRK 0x70 230 231 /* 2692-only commands */ 232 #define CR_CMD_RTS_ON 0x80 /* raise RTS */ 233 #define CR_CMD_RTS_OFF 0x90 /* lower RTS */ 234 #define CR_CMD_TIM_ON 0xa0 /* enable timeout mode */ 235 #define CR_CMD_TIM_OFF 0xc0 /* reset timeout mode */ 236 #define CR_CMD_PDN_ON 0xe0 /* power down mode on */ 237 #define CR_CMD_PDN_RUN 0xf0 /* power down mode off (normal run) */ 238 239 /* 26C92-only commands */ 240 #define CR_CMD_MR0 0xb0 /* MR0 select */ 241 242 /* 243 * CSR (clock select register) -- per channel 244 */ 245 #define CSR_B75 0x0 246 #define CSR_B110 0x1 247 #define CSR_B134 0x2 248 #define CSR_B150 0x3 249 #define CSR_B300 0x4 250 #define CSR_B600 0x5 251 #define CSR_B1200 0x6 252 #define CSR_B2000 0x7 253 #define CSR_B2400 0x8 254 #define CSR_B4800 0x9 255 #define CSR_B7200 0xa 256 #define CSR_B9600 0xb 257 #define CSR_B19200 0xc 258 259 /* 260 * SR (status register) -- per channel 261 */ 262 #define SR_RX_RDY 0x01 263 #define SR_RX_FFULL 0x02 /* rx fifo full */ 264 #define SR_TX_RDY 0x04 /* tx room for more */ 265 #define SR_TX_EMPTY 0x08 /* tx dry */ 266 267 #define SR_OVERRUN 0x10 268 269 /* bits cleared by reset error (see MR1 error mode bit) */ 270 #define SR_PARITY 0x20 /* received parity error */ 271 #define SR_FRAME 0x40 /* received framing error */ 272 #define SR_BREAK 0x80 /* received break */ 273 274 /* 275 * Interrupt Mask Register (IMR) and ISR (Interrupt Status Register) 276 */ 277 #define INT_TXA 0x01 /* Tx Ready A */ 278 #define INT_RXA 0x02 /* Rx Ready/FIFO Full A */ 279 #define INT_BRKA 0x04 /* Delta Break A */ 280 #define INT_CTR 0x08 /* counter ready */ 281 #define INT_TXB 0x10 /* Tx Ready B */ 282 #define INT_RXB 0x20 /* Rx Ready/FIFO Full B */ 283 #define INT_BRKB 0x40 /* Delta Break B */ 284 #define INT_IP 0x80 /* input port change */ 285
Indexes created Tue Sep 30 17:09:57 GMT 2025