asc_vsbus.c revision 1.4 1 1.4 matt /* $NetBSD: asc_vsbus.c,v 1.4 2000/03/05 23:20:25 matt Exp $ */
2 1.1 matt
3 1.1 matt /*-
4 1.1 matt * Copyright (c) 1998 The NetBSD Foundation, Inc.
5 1.1 matt * All rights reserved.
6 1.1 matt *
7 1.1 matt * This code is derived from software contributed to The NetBSD Foundation
8 1.1 matt * by Charles M. Hannum.
9 1.1 matt *
10 1.1 matt * Redistribution and use in source and binary forms, with or without
11 1.1 matt * modification, are permitted provided that the following conditions
12 1.1 matt * are met:
13 1.1 matt * 1. Redistributions of source code must retain the above copyright
14 1.1 matt * notice, this list of conditions and the following disclaimer.
15 1.1 matt * 2. Redistributions in binary form must reproduce the above copyright
16 1.1 matt * notice, this list of conditions and the following disclaimer in the
17 1.1 matt * documentation and/or other materials provided with the distribution.
18 1.1 matt * 3. All advertising materials mentioning features or use of this software
19 1.1 matt * must display the following acknowledgement:
20 1.1 matt * This product includes software developed by the NetBSD
21 1.1 matt * Foundation, Inc. and its contributors.
22 1.1 matt * 4. Neither the name of The NetBSD Foundation nor the names of its
23 1.1 matt * contributors may be used to endorse or promote products derived
24 1.1 matt * from this software without specific prior written permission.
25 1.1 matt *
26 1.1 matt * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
27 1.1 matt * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
28 1.1 matt * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
29 1.1 matt * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
30 1.1 matt * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
31 1.1 matt * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
32 1.1 matt * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
33 1.1 matt * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
34 1.1 matt * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
35 1.1 matt * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
36 1.1 matt * POSSIBILITY OF SUCH DAMAGE.
37 1.1 matt */
38 1.1 matt
39 1.1 matt #include <sys/cdefs.h> /* RCS ID & Copyright macro defns */
40 1.1 matt
41 1.4 matt __KERNEL_RCSID(0, "$NetBSD: asc_vsbus.c,v 1.4 2000/03/05 23:20:25 matt Exp $");
42 1.1 matt
43 1.1 matt #include <sys/types.h>
44 1.1 matt #include <sys/param.h>
45 1.1 matt #include <sys/systm.h>
46 1.1 matt #include <sys/kernel.h>
47 1.1 matt #include <sys/errno.h>
48 1.1 matt #include <sys/ioctl.h>
49 1.1 matt #include <sys/device.h>
50 1.1 matt #include <sys/buf.h>
51 1.1 matt #include <sys/proc.h>
52 1.1 matt #include <sys/user.h>
53 1.1 matt #include <sys/reboot.h>
54 1.1 matt #include <sys/queue.h>
55 1.1 matt
56 1.1 matt #include <dev/scsipi/scsi_all.h>
57 1.1 matt #include <dev/scsipi/scsipi_all.h>
58 1.1 matt #include <dev/scsipi/scsiconf.h>
59 1.1 matt #include <dev/scsipi/scsi_message.h>
60 1.1 matt
61 1.1 matt #include <machine/bus.h>
62 1.1 matt
63 1.1 matt #include <dev/ic/ncr53c9xreg.h>
64 1.1 matt #include <dev/ic/ncr53c9xvar.h>
65 1.1 matt
66 1.1 matt #include <machine/cpu.h>
67 1.1 matt #include <machine/sid.h>
68 1.1 matt #include <machine/rpb.h>
69 1.1 matt #include <machine/scb.h>
70 1.1 matt #include <machine/vsbus.h>
71 1.1 matt
72 1.1 matt struct asc_vsbus_softc {
73 1.1 matt struct ncr53c9x_softc sc_ncr53c9x; /* Must be first */
74 1.1 matt bus_space_tag_t sc_bst; /* bus space tag */
75 1.1 matt bus_space_handle_t sc_bsh; /* bus space handle */
76 1.4 matt bus_space_handle_t sc_ncrh; /* ncr bus space handle */
77 1.1 matt bus_dma_tag_t sc_dmat; /* bus dma tag */
78 1.1 matt bus_dmamap_t sc_dmamap;
79 1.1 matt caddr_t *sc_dmaaddr;
80 1.1 matt size_t *sc_dmalen;
81 1.1 matt size_t sc_dmasize;
82 1.1 matt unsigned int sc_flags;
83 1.1 matt #define ASC_DMAACTIVE 0x0001
84 1.1 matt #define ASC_ISWRITE 0x0002
85 1.4 matt #define ASC_MAPLOADED 0x0004
86 1.1 matt };
87 1.1 matt
88 1.1 matt #define ASC_REG_ADR 0x0000
89 1.1 matt #define ASC_REG_DIR 0x000C
90 1.1 matt #define ASC_REG_NCR 0x0080
91 1.1 matt #define ASC_REG_END 0x00B0
92 1.1 matt
93 1.4 matt #define ASC_TOMEMORY 0x0000
94 1.4 matt #define ASC_FROMMEMORY 0x0001
95 1.1 matt
96 1.1 matt #define ASC_MAXXFERSIZE 65536
97 1.1 matt #define ASC_FREQUENCY 20000000
98 1.1 matt
99 1.1 matt static int asc_vsbus_match __P((struct device *, struct cfdata *, void *));
100 1.1 matt static void asc_vsbus_attach __P((struct device *, struct device *, void *));
101 1.1 matt
102 1.1 matt struct cfattach asc_vsbus_ca = {
103 1.1 matt sizeof(struct asc_vsbus_softc), asc_vsbus_match, asc_vsbus_attach
104 1.1 matt };
105 1.1 matt
106 1.1 matt static struct scsipi_device asc_vsbus_dev = {
107 1.1 matt NULL, /* Use the default error handler */
108 1.1 matt NULL, /* have a queue, served by this */
109 1.1 matt NULL, /* have no async handler */
110 1.1 matt NULL, /* use the default done handler */
111 1.1 matt };
112 1.1 matt
113 1.1 matt /*
114 1.1 matt * Functions and the switch for the MI code
115 1.1 matt */
116 1.1 matt static u_char asc_vsbus_read_reg __P((struct ncr53c9x_softc *, int));
117 1.1 matt static void asc_vsbus_write_reg __P((struct ncr53c9x_softc *, int, u_char));
118 1.1 matt static int asc_vsbus_dma_isintr __P((struct ncr53c9x_softc *));
119 1.1 matt static void asc_vsbus_dma_reset __P((struct ncr53c9x_softc *));
120 1.1 matt static int asc_vsbus_dma_intr __P((struct ncr53c9x_softc *));
121 1.1 matt static int asc_vsbus_dma_setup __P((struct ncr53c9x_softc *, caddr_t *,
122 1.1 matt size_t *, int, size_t *));
123 1.1 matt static void asc_vsbus_dma_go __P((struct ncr53c9x_softc *));
124 1.1 matt static void asc_vsbus_dma_stop __P((struct ncr53c9x_softc *));
125 1.1 matt static int asc_vsbus_dma_isactive __P((struct ncr53c9x_softc *));
126 1.1 matt
127 1.1 matt static struct ncr53c9x_glue asc_vsbus_glue = {
128 1.1 matt asc_vsbus_read_reg,
129 1.1 matt asc_vsbus_write_reg,
130 1.1 matt asc_vsbus_dma_isintr,
131 1.1 matt asc_vsbus_dma_reset,
132 1.1 matt asc_vsbus_dma_intr,
133 1.1 matt asc_vsbus_dma_setup,
134 1.1 matt asc_vsbus_dma_go,
135 1.1 matt asc_vsbus_dma_stop,
136 1.1 matt asc_vsbus_dma_isactive,
137 1.4 matt NULL,
138 1.1 matt };
139 1.1 matt
140 1.1 matt static int
141 1.1 matt asc_vsbus_match( struct device *parent, struct cfdata *cf, void *aux)
142 1.1 matt {
143 1.1 matt struct vsbus_attach_args *va = aux;
144 1.1 matt int dummy;
145 1.3 matt volatile u_int8_t *ncr_regs;
146 1.1 matt
147 1.1 matt if (vax_boardtype != VAX_BTYP_46
148 1.1 matt && vax_boardtype != VAX_BTYP_48
149 1.1 matt && vax_boardtype != VAX_BTYP_49)
150 1.1 matt return 0;
151 1.1 matt
152 1.3 matt ncr_regs = (volatile u_int8_t *) va->va_addr;
153 1.1 matt
154 1.1 matt /* *** need to generate an interrupt here
155 1.1 matt * From trial and error, I've determined that an INT is generated
156 1.1 matt * only when the following sequence of events occurs:
157 1.1 matt * 1) The interrupt status register (0x05) must be read.
158 1.1 matt * 2) SCSI bus reset interrupt must be enabled
159 1.1 matt * 3) SCSI bus reset command must be sent
160 1.1 matt * 4) NOP command must be sent
161 1.1 matt */
162 1.1 matt
163 1.3 matt dummy = ncr_regs[NCR_INTR << 2] & 0xFF;
164 1.3 matt ncr_regs[NCR_CFG1 << 2] = 0x07; /* we're ID 7, turn on INT for SCSI reset */
165 1.3 matt ncr_regs[NCR_CMD << 2] = NCRCMD_RSTSCSI; /* send the reset */
166 1.3 matt ncr_regs[NCR_CMD << 2] = NCRCMD_NOP; /* send a NOP */
167 1.1 matt DELAY(10000);
168 1.1 matt
169 1.3 matt dummy = ncr_regs[NCR_INTR << 2] & 0xFF;
170 1.3 matt return (dummy & NCRINTR_SBR) != 0;
171 1.1 matt }
172 1.1 matt
173 1.1 matt
174 1.1 matt /*
175 1.1 matt * Attach this instance, and then all the sub-devices
176 1.1 matt */
177 1.1 matt static void
178 1.1 matt asc_vsbus_attach(struct device *parent, struct device *self, void *aux)
179 1.1 matt {
180 1.1 matt struct vsbus_attach_args *va = aux;
181 1.1 matt struct asc_vsbus_softc *asc = (void *)self;
182 1.1 matt struct ncr53c9x_softc *sc = &asc->sc_ncr53c9x;
183 1.1 matt int error;
184 1.1 matt
185 1.1 matt /*
186 1.1 matt * Set up glue for MI code early; we use some of it here.
187 1.1 matt */
188 1.1 matt sc->sc_glue = &asc_vsbus_glue;
189 1.1 matt
190 1.1 matt asc->sc_bst = va->va_iot;
191 1.1 matt asc->sc_dmat = va->va_dmat;
192 1.1 matt
193 1.1 matt error = bus_space_map(asc->sc_bst, va->va_paddr - ASC_REG_NCR,
194 1.1 matt ASC_REG_END, 0, &asc->sc_bsh);
195 1.1 matt if (error) {
196 1.1 matt printf(": failed to map registers: error=%d\n", error);
197 1.1 matt return;
198 1.1 matt }
199 1.4 matt error = bus_space_subregion(asc->sc_bst, asc->sc_bsh, ASC_REG_NCR,
200 1.4 matt ASC_REG_END - ASC_REG_NCR, &asc->sc_ncrh);
201 1.4 matt if (error) {
202 1.4 matt printf(": failed to map ncr registers: error=%d\n", error);
203 1.4 matt return;
204 1.4 matt }
205 1.4 matt error = bus_dmamap_create(asc->sc_dmat, ASC_MAXXFERSIZE, 1,
206 1.4 matt ASC_MAXXFERSIZE, 0, BUS_DMA_NOWAIT, &asc->sc_dmamap);
207 1.1 matt
208 1.1 matt sc->sc_id = 7; /* XXX need to get this from VMB */
209 1.1 matt sc->sc_freq = ASC_FREQUENCY;
210 1.1 matt
211 1.1 matt /* gimme Mhz */
212 1.1 matt sc->sc_freq /= 1000000;
213 1.1 matt
214 1.4 matt scb_vecalloc(va->va_cvec, (void (*)(void *)) ncr53c9x_intr,
215 1.4 matt &asc->sc_ncr53c9x, SCB_ISTACK);
216 1.1 matt
217 1.1 matt /*
218 1.1 matt * XXX More of this should be in ncr53c9x_attach(), but
219 1.1 matt * XXX should we really poke around the chip that much in
220 1.1 matt * XXX the MI code? Think about this more...
221 1.1 matt */
222 1.1 matt
223 1.1 matt /*
224 1.1 matt * Set up static configuration info.
225 1.1 matt */
226 1.1 matt sc->sc_cfg1 = sc->sc_id | NCRCFG1_PARENB;
227 1.1 matt sc->sc_cfg2 = NCRCFG2_SCSI2;
228 1.4 matt sc->sc_cfg3 = 0;
229 1.1 matt sc->sc_rev = NCR_VARIANT_NCR53C94;
230 1.1 matt
231 1.1 matt /*
232 1.1 matt * XXX minsync and maxxfer _should_ be set up in MI code,
233 1.1 matt * XXX but it appears to have some dependency on what sort
234 1.1 matt * XXX of DMA we're hooked up to, etc.
235 1.1 matt */
236 1.1 matt
237 1.1 matt /*
238 1.1 matt * This is the value used to start sync negotiations
239 1.1 matt * Note that the NCR register "SYNCTP" is programmed
240 1.1 matt * in "clocks per byte", and has a minimum value of 4.
241 1.1 matt * The SCSI period used in negotiation is one-fourth
242 1.1 matt * of the time (in nanoseconds) needed to transfer one byte.
243 1.1 matt * Since the chip's clock is given in MHz, we have the following
244 1.1 matt * formula: 4 * period = (1000 / freq) * 4
245 1.1 matt */
246 1.1 matt sc->sc_minsync = (1000 / sc->sc_freq);
247 1.1 matt sc->sc_maxxfer = 64 * 1024;
248 1.1 matt
249 1.3 matt printf("\n%s", self->dv_xname); /* Pretty print */
250 1.3 matt
251 1.1 matt /* Do the common parts of attachment. */
252 1.1 matt sc->sc_adapter.scsipi_cmd = ncr53c9x_scsi_cmd;
253 1.1 matt sc->sc_adapter.scsipi_minphys = minphys;
254 1.1 matt ncr53c9x_attach(sc, &asc_vsbus_dev);
255 1.1 matt
256 1.1 matt /*
257 1.1 matt * Register this device as boot device if we booted from it.
258 1.1 matt * This will fail if there are more than one le in a machine,
259 1.1 matt * fortunately there may be only one.
260 1.1 matt */
261 1.1 matt if (B_TYPE(bootdev) == BDEV_SD)
262 1.1 matt booted_from = self;
263 1.1 matt }
264 1.1 matt
265 1.1 matt /*
266 1.1 matt * Glue functions.
267 1.1 matt */
268 1.1 matt
269 1.1 matt static u_char
270 1.1 matt asc_vsbus_read_reg(struct ncr53c9x_softc *sc, int reg)
271 1.1 matt {
272 1.1 matt struct asc_vsbus_softc *asc = (struct asc_vsbus_softc *)sc;
273 1.1 matt
274 1.4 matt return bus_space_read_1(asc->sc_bst, asc->sc_ncrh,
275 1.4 matt reg * sizeof(u_int32_t));
276 1.1 matt }
277 1.1 matt
278 1.1 matt static void
279 1.1 matt asc_vsbus_write_reg(sc, reg, val)
280 1.1 matt struct ncr53c9x_softc *sc;
281 1.1 matt int reg;
282 1.1 matt u_char val;
283 1.1 matt {
284 1.1 matt struct asc_vsbus_softc *asc = (struct asc_vsbus_softc *)sc;
285 1.1 matt
286 1.4 matt bus_space_write_1(asc->sc_bst, asc->sc_ncrh,
287 1.4 matt reg * sizeof(u_int32_t), val);
288 1.1 matt }
289 1.1 matt
290 1.1 matt static int
291 1.1 matt asc_vsbus_dma_isintr(sc)
292 1.1 matt struct ncr53c9x_softc *sc;
293 1.1 matt {
294 1.1 matt struct asc_vsbus_softc *asc = (struct asc_vsbus_softc *)sc;
295 1.4 matt return bus_space_read_1(asc->sc_bst, asc->sc_ncrh,
296 1.4 matt NCR_STAT * sizeof(u_int32_t)) & NCRSTAT_INT;
297 1.1 matt }
298 1.1 matt
299 1.1 matt static void
300 1.1 matt asc_vsbus_dma_reset(sc)
301 1.1 matt struct ncr53c9x_softc *sc;
302 1.1 matt {
303 1.1 matt struct asc_vsbus_softc *asc = (struct asc_vsbus_softc *)sc;
304 1.1 matt
305 1.4 matt if (asc->sc_flags & ASC_MAPLOADED)
306 1.4 matt bus_dmamap_unload(asc->sc_dmat, asc->sc_dmamap);
307 1.4 matt asc->sc_flags &= ~(ASC_DMAACTIVE|ASC_MAPLOADED);
308 1.1 matt }
309 1.1 matt
310 1.1 matt static int
311 1.1 matt asc_vsbus_dma_intr(sc)
312 1.1 matt struct ncr53c9x_softc *sc;
313 1.1 matt {
314 1.1 matt struct asc_vsbus_softc *asc = (struct asc_vsbus_softc *)sc;
315 1.4 matt u_int tcl, tcm;
316 1.4 matt int trans, resid;
317 1.4 matt
318 1.4 matt if ((asc->sc_flags & ASC_DMAACTIVE) == 0)
319 1.4 matt panic("asc_vsbus_dma_intr: DMA wasn't active");
320 1.4 matt
321 1.4 matt asc->sc_flags &= ~ASC_DMAACTIVE;
322 1.4 matt
323 1.4 matt if (asc->sc_dmasize == 0) {
324 1.4 matt /* A "Transfer Pad" operation completed */
325 1.4 matt tcl = NCR_READ_REG(sc, NCR_TCL);
326 1.4 matt tcm = NCR_READ_REG(sc, NCR_TCM);
327 1.4 matt NCR_DMA(("asc_vsbus_intr: discarded %d bytes (tcl=%d, tcm=%d)\n",
328 1.4 matt tcl | (tcm << 8), tcl, tcm));
329 1.4 matt return 0;
330 1.4 matt }
331 1.4 matt
332 1.4 matt resid = 0;
333 1.4 matt if ((resid = (NCR_READ_REG(sc, NCR_FFLAG) & NCRFIFO_FF)) != 0) {
334 1.4 matt NCR_DMA(("asc_vsbus_intr: empty FIFO of %d ", resid));
335 1.4 matt DELAY(1);
336 1.4 matt }
337 1.4 matt if (asc->sc_flags & ASC_MAPLOADED)
338 1.4 matt bus_dmamap_unload(asc->sc_dmat, asc->sc_dmamap);
339 1.4 matt asc->sc_flags &= ~ASC_MAPLOADED;
340 1.4 matt
341 1.4 matt resid += (tcl = NCR_READ_REG(sc, NCR_TCL));
342 1.4 matt resid += (tcm = NCR_READ_REG(sc, NCR_TCM)) << 8;
343 1.4 matt
344 1.4 matt trans = asc->sc_dmasize - resid;
345 1.4 matt if (trans < 0) { /* transferred < 0 ? */
346 1.4 matt printf("ioasic_intr: xfer (%d) > req (%d)\n",
347 1.4 matt trans, asc->sc_dmasize);
348 1.4 matt trans = asc->sc_dmasize;
349 1.4 matt }
350 1.4 matt NCR_DMA(("asc_vsbus_intr: tcl=%d, tcm=%d; trans=%d, resid=%d\n",
351 1.4 matt tcl, tcm, trans, resid));
352 1.1 matt
353 1.4 matt *asc->sc_dmalen -= trans;
354 1.4 matt *asc->sc_dmaaddr += trans;
355 1.4 matt
356 1.1 matt return 0;
357 1.1 matt }
358 1.1 matt
359 1.1 matt static int
360 1.1 matt asc_vsbus_dma_setup(struct ncr53c9x_softc *sc, caddr_t *addr, size_t *len,
361 1.1 matt int datain, size_t *dmasize)
362 1.1 matt {
363 1.1 matt struct asc_vsbus_softc *asc = (struct asc_vsbus_softc *)sc;
364 1.1 matt
365 1.1 matt asc->sc_dmaaddr = addr;
366 1.1 matt asc->sc_dmalen = len;
367 1.1 matt if (datain) {
368 1.1 matt asc->sc_flags |= ASC_ISWRITE;
369 1.1 matt } else {
370 1.1 matt asc->sc_flags &= ~ASC_ISWRITE;
371 1.1 matt }
372 1.1 matt
373 1.1 matt NCR_DMA(("%s: start %d@%p,%d\n", sc->sc_dev.dv_xname,
374 1.1 matt (int)*asc->sc_dmalen, *asc->sc_dmaaddr, (asc->sc_flags & ASC_ISWRITE)));
375 1.1 matt *dmasize = asc->sc_dmasize = min(*dmasize, ASC_MAXXFERSIZE);
376 1.1 matt
377 1.1 matt if (asc->sc_dmasize) {
378 1.1 matt if (bus_dmamap_load(asc->sc_dmat, asc->sc_dmamap,
379 1.1 matt *asc->sc_dmaaddr, asc->sc_dmasize,
380 1.1 matt NULL /* kernel address */,
381 1.1 matt BUS_DMA_NOWAIT))
382 1.1 matt panic("%s: cannot load dma map", sc->sc_dev.dv_xname);
383 1.1 matt bus_dmamap_sync(asc->sc_dmat, asc->sc_dmamap,
384 1.1 matt 0, asc->sc_dmasize, datain
385 1.1 matt ? BUS_DMASYNC_PREREAD
386 1.1 matt : BUS_DMASYNC_PREWRITE);
387 1.1 matt bus_space_write_4(asc->sc_bst, asc->sc_bsh, ASC_REG_ADR,
388 1.1 matt asc->sc_dmamap->dm_segs[0].ds_addr);
389 1.1 matt bus_space_write_4(asc->sc_bst, asc->sc_bsh, ASC_REG_DIR,
390 1.4 matt datain ? ASC_TOMEMORY : ASC_FROMMEMORY);
391 1.4 matt asc->sc_flags |= ASC_MAPLOADED;
392 1.1 matt }
393 1.1 matt
394 1.1 matt return 0;
395 1.1 matt }
396 1.1 matt
397 1.1 matt static void
398 1.1 matt asc_vsbus_dma_go(struct ncr53c9x_softc *sc)
399 1.1 matt {
400 1.1 matt struct asc_vsbus_softc *asc = (struct asc_vsbus_softc *)sc;
401 1.1 matt
402 1.4 matt asc->sc_flags |= ASC_DMAACTIVE;
403 1.1 matt }
404 1.1 matt
405 1.1 matt static void
406 1.1 matt asc_vsbus_dma_stop(struct ncr53c9x_softc *sc)
407 1.1 matt {
408 1.1 matt struct asc_vsbus_softc *asc = (struct asc_vsbus_softc *)sc;
409 1.1 matt
410 1.4 matt if (asc->sc_flags & ASC_MAPLOADED)
411 1.4 matt bus_dmamap_unload(asc->sc_dmat, asc->sc_dmamap);
412 1.4 matt
413 1.4 matt asc->sc_flags &= ~(ASC_DMAACTIVE|ASC_MAPLOADED);
414 1.1 matt }
415 1.1 matt
416 1.1 matt static int
417 1.1 matt asc_vsbus_dma_isactive(struct ncr53c9x_softc *sc)
418 1.1 matt {
419 1.1 matt struct asc_vsbus_softc *asc = (struct asc_vsbus_softc *)sc;
420 1.1 matt
421 1.1 matt return (asc->sc_flags & ASC_DMAACTIVE) != 0;
422 1.1 matt }
423