asc_vsbus.c revision 1.10
1 /* $NetBSD: asc_vsbus.c,v 1.10 2000/04/18 21:25:31 matt Exp $ */ 2 3 /*- 4 * Copyright (c) 1998 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Charles M. Hannum. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 #include "opt_vax46.h" 40 41 #include <sys/cdefs.h> /* RCS ID & Copyright macro defns */ 42 43 __KERNEL_RCSID(0, "$NetBSD: asc_vsbus.c,v 1.10 2000/04/18 21:25:31 matt Exp $"); 44 45 #include <sys/types.h> 46 #include <sys/param.h> 47 #include <sys/systm.h> 48 #include <sys/kernel.h> 49 #include <sys/errno.h> 50 #include <sys/ioctl.h> 51 #include <sys/device.h> 52 #include <sys/buf.h> 53 #include <sys/proc.h> 54 #include <sys/user.h> 55 #include <sys/reboot.h> 56 #include <sys/queue.h> 57 58 #include <dev/scsipi/scsi_all.h> 59 #include <dev/scsipi/scsipi_all.h> 60 #include <dev/scsipi/scsiconf.h> 61 #include <dev/scsipi/scsi_message.h> 62 63 #include <machine/bus.h> 64 #include <machine/vmparam.h> 65 66 #include <dev/ic/ncr53c9xreg.h> 67 #include <dev/ic/ncr53c9xvar.h> 68 69 #include <machine/cpu.h> 70 #include <machine/sid.h> 71 #include <machine/scb.h> 72 #include <machine/vsbus.h> 73 #include <machine/clock.h> /* for SCSI ctlr ID# XXX */ 74 75 struct asc_vsbus_softc { 76 struct ncr53c9x_softc sc_ncr53c9x; /* Must be first */ 77 bus_space_tag_t sc_bst; /* bus space tag */ 78 bus_space_handle_t sc_bsh; /* bus space handle */ 79 bus_space_handle_t sc_ncrh; /* ncr bus space handle */ 80 bus_dma_tag_t sc_dmat; /* bus dma tag */ 81 bus_dmamap_t sc_dmamap; 82 caddr_t *sc_dmaaddr; 83 size_t *sc_dmalen; 84 size_t sc_dmasize; 85 unsigned int sc_flags; 86 #define ASC_FROMMEMORY 0x0001 /* Must be 1 */ 87 #define ASC_DMAACTIVE 0x0002 88 #define ASC_MAPLOADED 0x0004 89 unsigned long sc_xfers; 90 }; 91 92 #define ASC_REG_ADR 0x0000 93 #define ASC_REG_DIR 0x000C 94 #define ASC_REG_NCR 0x0080 95 #define ASC_REG_END 0x00B0 96 97 #define ASC_MAXXFERSIZE 65536 98 #define ASC_FREQUENCY 25000000 99 100 static int asc_vsbus_match __P((struct device *, struct cfdata *, void *)); 101 static void asc_vsbus_attach __P((struct device *, struct device *, void *)); 102 103 struct cfattach asc_vsbus_ca = { 104 sizeof(struct asc_vsbus_softc), asc_vsbus_match, asc_vsbus_attach 105 }; 106 107 static struct scsipi_device asc_vsbus_dev = { 108 NULL, /* Use the default error handler */ 109 NULL, /* have a queue, served by this */ 110 NULL, /* have no async handler */ 111 NULL, /* use the default done handler */ 112 }; 113 114 /* 115 * Functions and the switch for the MI code 116 */ 117 static u_char asc_vsbus_read_reg __P((struct ncr53c9x_softc *, int)); 118 static void asc_vsbus_write_reg __P((struct ncr53c9x_softc *, int, u_char)); 119 static int asc_vsbus_dma_isintr __P((struct ncr53c9x_softc *)); 120 static void asc_vsbus_dma_reset __P((struct ncr53c9x_softc *)); 121 static int asc_vsbus_dma_intr __P((struct ncr53c9x_softc *)); 122 static int asc_vsbus_dma_setup __P((struct ncr53c9x_softc *, caddr_t *, 123 size_t *, int, size_t *)); 124 static void asc_vsbus_dma_go __P((struct ncr53c9x_softc *)); 125 static void asc_vsbus_dma_stop __P((struct ncr53c9x_softc *)); 126 static int asc_vsbus_dma_isactive __P((struct ncr53c9x_softc *)); 127 128 static struct ncr53c9x_glue asc_vsbus_glue = { 129 asc_vsbus_read_reg, 130 asc_vsbus_write_reg, 131 asc_vsbus_dma_isintr, 132 asc_vsbus_dma_reset, 133 asc_vsbus_dma_intr, 134 asc_vsbus_dma_setup, 135 asc_vsbus_dma_go, 136 asc_vsbus_dma_stop, 137 asc_vsbus_dma_isactive, 138 NULL, 139 }; 140 141 static int 142 asc_vsbus_match( struct device *parent, struct cfdata *cf, void *aux) 143 { 144 struct vsbus_attach_args *va = aux; 145 int dummy; 146 volatile u_int8_t *ncr_regs; 147 148 if (vax_boardtype != VAX_BTYP_46 149 && vax_boardtype != VAX_BTYP_48 150 /* && vax_boardtype != VAX_BTYP_49 */) 151 return 0; 152 153 ncr_regs = (volatile u_int8_t *) va->va_addr; 154 155 /* *** need to generate an interrupt here 156 * From trial and error, I've determined that an INT is generated 157 * only when the following sequence of events occurs: 158 * 1) The interrupt status register (0x05) must be read. 159 * 2) SCSI bus reset interrupt must be enabled 160 * 3) SCSI bus reset command must be sent 161 * 4) NOP command must be sent 162 */ 163 164 dummy = ncr_regs[NCR_INTR << 2] & 0xFF; 165 ncr_regs[NCR_CFG1 << 2] = 0x06; /* we're ID 6, turn on INT for SCSI reset */ 166 ncr_regs[NCR_CMD << 2] = NCRCMD_RSTSCSI; /* send the reset */ 167 ncr_regs[NCR_CMD << 2] = NCRCMD_NOP; /* send a NOP */ 168 DELAY(10000); 169 170 dummy = ncr_regs[NCR_INTR << 2] & 0xFF; 171 return (dummy & NCRINTR_SBR) != 0; 172 } 173 174 175 /* 176 * Attach this instance, and then all the sub-devices 177 */ 178 static void 179 asc_vsbus_attach(struct device *parent, struct device *self, void *aux) 180 { 181 struct vsbus_attach_args *va = aux; 182 struct asc_vsbus_softc *asc = (void *)self; 183 struct ncr53c9x_softc *sc = &asc->sc_ncr53c9x; 184 int error; 185 186 /* 187 * Set up glue for MI code early; we use some of it here. 188 */ 189 sc->sc_glue = &asc_vsbus_glue; 190 191 asc->sc_bst = va->va_iot; 192 asc->sc_dmat = va->va_dmat; 193 194 error = bus_space_map(asc->sc_bst, va->va_paddr - ASC_REG_NCR, 195 ASC_REG_END, 0, &asc->sc_bsh); 196 if (error) { 197 printf(": failed to map registers: error=%d\n", error); 198 return; 199 } 200 error = bus_space_subregion(asc->sc_bst, asc->sc_bsh, ASC_REG_NCR, 201 ASC_REG_END - ASC_REG_NCR, &asc->sc_ncrh); 202 if (error) { 203 printf(": failed to map ncr registers: error=%d\n", error); 204 return; 205 } 206 error = bus_dmamap_create(asc->sc_dmat, ASC_MAXXFERSIZE, 1, 207 ASC_MAXXFERSIZE, 0, BUS_DMA_NOWAIT, &asc->sc_dmamap); 208 209 switch (vax_boardtype) { 210 #if defined(VAX46) 211 case VAX_BTYP_46: 212 sc->sc_id = (clk_page[0xbc/2] >> clk_tweak) & 7; 213 break; 214 #endif 215 default: 216 sc->sc_id = 6; /* XXX need to get this from VMB */ 217 break; 218 } 219 220 sc->sc_freq = ASC_FREQUENCY; 221 222 /* gimme Mhz */ 223 sc->sc_freq /= 1000000; 224 225 scb_vecalloc(va->va_cvec, (void (*)(void *)) ncr53c9x_intr, 226 &asc->sc_ncr53c9x, SCB_ISTACK); 227 228 /* 229 * XXX More of this should be in ncr53c9x_attach(), but 230 * XXX should we really poke around the chip that much in 231 * XXX the MI code? Think about this more... 232 */ 233 234 /* 235 * Set up static configuration info. 236 */ 237 sc->sc_cfg1 = sc->sc_id | NCRCFG1_PARENB; 238 sc->sc_cfg2 = NCRCFG2_SCSI2; 239 sc->sc_cfg3 = 0; 240 sc->sc_rev = NCR_VARIANT_NCR53C94; 241 242 /* 243 * XXX minsync and maxxfer _should_ be set up in MI code, 244 * XXX but it appears to have some dependency on what sort 245 * XXX of DMA we're hooked up to, etc. 246 */ 247 248 /* 249 * This is the value used to start sync negotiations 250 * Note that the NCR register "SYNCTP" is programmed 251 * in "clocks per byte", and has a minimum value of 4. 252 * The SCSI period used in negotiation is one-fourth 253 * of the time (in nanoseconds) needed to transfer one byte. 254 * Since the chip's clock is given in MHz, we have the following 255 * formula: 4 * period = (1000 / freq) * 4 256 */ 257 sc->sc_minsync = (1000 / sc->sc_freq); 258 sc->sc_maxxfer = 63 * 1024; 259 260 printf("\n%s", self->dv_xname); /* Pretty print */ 261 262 /* Do the common parts of attachment. */ 263 sc->sc_adapter.scsipi_cmd = ncr53c9x_scsi_cmd; 264 sc->sc_adapter.scsipi_minphys = minphys; 265 ncr53c9x_attach(sc, &asc_vsbus_dev); 266 } 267 268 /* 269 * Glue functions. 270 */ 271 272 static u_char 273 asc_vsbus_read_reg(struct ncr53c9x_softc *sc, int reg) 274 { 275 struct asc_vsbus_softc *asc = (struct asc_vsbus_softc *)sc; 276 277 return bus_space_read_1(asc->sc_bst, asc->sc_ncrh, 278 reg * sizeof(u_int32_t)); 279 } 280 281 static void 282 asc_vsbus_write_reg(sc, reg, val) 283 struct ncr53c9x_softc *sc; 284 int reg; 285 u_char val; 286 { 287 struct asc_vsbus_softc *asc = (struct asc_vsbus_softc *)sc; 288 289 bus_space_write_1(asc->sc_bst, asc->sc_ncrh, 290 reg * sizeof(u_int32_t), val); 291 } 292 293 static int 294 asc_vsbus_dma_isintr(sc) 295 struct ncr53c9x_softc *sc; 296 { 297 struct asc_vsbus_softc *asc = (struct asc_vsbus_softc *)sc; 298 return bus_space_read_1(asc->sc_bst, asc->sc_ncrh, 299 NCR_STAT * sizeof(u_int32_t)) & NCRSTAT_INT; 300 } 301 302 static void 303 asc_vsbus_dma_reset(sc) 304 struct ncr53c9x_softc *sc; 305 { 306 struct asc_vsbus_softc *asc = (struct asc_vsbus_softc *)sc; 307 308 if (asc->sc_flags & ASC_MAPLOADED) 309 bus_dmamap_unload(asc->sc_dmat, asc->sc_dmamap); 310 asc->sc_flags &= ~(ASC_DMAACTIVE|ASC_MAPLOADED); 311 } 312 313 static int 314 asc_vsbus_dma_intr(sc) 315 struct ncr53c9x_softc *sc; 316 { 317 struct asc_vsbus_softc *asc = (struct asc_vsbus_softc *)sc; 318 u_int tcl, tcm; 319 int trans, resid; 320 321 if ((asc->sc_flags & ASC_DMAACTIVE) == 0) 322 panic("asc_vsbus_dma_intr: DMA wasn't active"); 323 324 asc->sc_flags &= ~ASC_DMAACTIVE; 325 326 if (asc->sc_dmasize == 0) { 327 /* A "Transfer Pad" operation completed */ 328 tcl = NCR_READ_REG(sc, NCR_TCL); 329 tcm = NCR_READ_REG(sc, NCR_TCM); 330 NCR_DMA(("asc_vsbus_intr: discarded %d bytes (tcl=%d, tcm=%d)\n", 331 tcl | (tcm << 8), tcl, tcm)); 332 return 0; 333 } 334 335 resid = 0; 336 if ((resid = (NCR_READ_REG(sc, NCR_FFLAG) & NCRFIFO_FF)) != 0) { 337 NCR_DMA(("asc_vsbus_intr: empty FIFO of %d ", resid)); 338 DELAY(1); 339 } 340 if (asc->sc_flags & ASC_MAPLOADED) { 341 bus_dmamap_sync(asc->sc_dmat, asc->sc_dmamap, 342 0, asc->sc_dmasize, 343 asc->sc_flags & ASC_FROMMEMORY 344 ? BUS_DMASYNC_POSTWRITE 345 : BUS_DMASYNC_POSTREAD); 346 bus_dmamap_unload(asc->sc_dmat, asc->sc_dmamap); 347 } 348 asc->sc_flags &= ~ASC_MAPLOADED; 349 350 resid += (tcl = NCR_READ_REG(sc, NCR_TCL)); 351 resid += (tcm = NCR_READ_REG(sc, NCR_TCM)) << 8; 352 353 trans = asc->sc_dmasize - resid; 354 if (trans < 0) { /* transferred < 0 ? */ 355 printf("asc_vsbus_intr: xfer (%d) > req (%d)\n", 356 trans, asc->sc_dmasize); 357 trans = asc->sc_dmasize; 358 } 359 NCR_DMA(("asc_vsbus_intr: tcl=%d, tcm=%d; trans=%d, resid=%d\n", 360 tcl, tcm, trans, resid)); 361 362 *asc->sc_dmalen -= trans; 363 *asc->sc_dmaaddr += trans; 364 365 asc->sc_xfers++; 366 return 0; 367 } 368 369 static int 370 asc_vsbus_dma_setup(struct ncr53c9x_softc *sc, caddr_t *addr, size_t *len, 371 int datain, size_t *dmasize) 372 { 373 struct asc_vsbus_softc *asc = (struct asc_vsbus_softc *)sc; 374 375 asc->sc_dmaaddr = addr; 376 asc->sc_dmalen = len; 377 if (datain) { 378 asc->sc_flags &= ~ASC_FROMMEMORY; 379 } else { 380 asc->sc_flags |= ASC_FROMMEMORY; 381 } 382 if ((vaddr_t) *asc->sc_dmaaddr < VM_MIN_KERNEL_ADDRESS) 383 panic("asc_vsbus_dma_setup: dma address (%p) outside of kernel", 384 *asc->sc_dmaaddr); 385 386 NCR_DMA(("%s: start %d@%p,%d\n", sc->sc_dev.dv_xname, 387 (int)*asc->sc_dmalen, *asc->sc_dmaaddr, (asc->sc_flags & ASC_FROMMEMORY))); 388 *dmasize = asc->sc_dmasize = min(*dmasize, ASC_MAXXFERSIZE); 389 390 if (asc->sc_dmasize) { 391 if (bus_dmamap_load(asc->sc_dmat, asc->sc_dmamap, 392 *asc->sc_dmaaddr, asc->sc_dmasize, 393 NULL /* kernel address */, 394 BUS_DMA_NOWAIT|VAX_BUS_DMA_SPILLPAGE)) 395 panic("%s: cannot load dma map", sc->sc_dev.dv_xname); 396 bus_dmamap_sync(asc->sc_dmat, asc->sc_dmamap, 397 0, asc->sc_dmasize, 398 asc->sc_flags & ASC_FROMMEMORY 399 ? BUS_DMASYNC_PREWRITE 400 : BUS_DMASYNC_PREREAD); 401 bus_space_write_4(asc->sc_bst, asc->sc_bsh, ASC_REG_ADR, 402 asc->sc_dmamap->dm_segs[0].ds_addr); 403 bus_space_write_4(asc->sc_bst, asc->sc_bsh, ASC_REG_DIR, 404 asc->sc_flags & ASC_FROMMEMORY); 405 asc->sc_flags |= ASC_MAPLOADED; 406 } 407 408 return 0; 409 } 410 411 static void 412 asc_vsbus_dma_go(struct ncr53c9x_softc *sc) 413 { 414 struct asc_vsbus_softc *asc = (struct asc_vsbus_softc *)sc; 415 416 asc->sc_flags |= ASC_DMAACTIVE; 417 } 418 419 static void 420 asc_vsbus_dma_stop(struct ncr53c9x_softc *sc) 421 { 422 struct asc_vsbus_softc *asc = (struct asc_vsbus_softc *)sc; 423 424 if (asc->sc_flags & ASC_MAPLOADED) { 425 bus_dmamap_sync(asc->sc_dmat, asc->sc_dmamap, 426 0, asc->sc_dmasize, 427 asc->sc_flags & ASC_FROMMEMORY 428 ? BUS_DMASYNC_POSTWRITE 429 : BUS_DMASYNC_POSTREAD); 430 bus_dmamap_unload(asc->sc_dmat, asc->sc_dmamap); 431 } 432 433 asc->sc_flags &= ~(ASC_DMAACTIVE|ASC_MAPLOADED); 434 } 435 436 static int 437 asc_vsbus_dma_isactive(struct ncr53c9x_softc *sc) 438 { 439 struct asc_vsbus_softc *asc = (struct asc_vsbus_softc *)sc; 440 441 return (asc->sc_flags & ASC_DMAACTIVE) != 0; 442 } 443
Indexes created Tue Sep 30 17:09:57 GMT 2025