asc_vsbus.c revision 1.16
1 /* $NetBSD: asc_vsbus.c,v 1.16 2000/06/05 00:09:20 matt Exp $ */ 2 3 /*- 4 * Copyright (c) 1998 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Charles M. Hannum. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 #include "opt_vax46.h" 40 41 #include <sys/cdefs.h> /* RCS ID & Copyright macro defns */ 42 43 __KERNEL_RCSID(0, "$NetBSD: asc_vsbus.c,v 1.16 2000/06/05 00:09:20 matt Exp $"); 44 45 #include <sys/types.h> 46 #include <sys/param.h> 47 #include <sys/systm.h> 48 #include <sys/kernel.h> 49 #include <sys/errno.h> 50 #include <sys/ioctl.h> 51 #include <sys/device.h> 52 #include <sys/buf.h> 53 #include <sys/proc.h> 54 #include <sys/user.h> 55 #include <sys/reboot.h> 56 #include <sys/queue.h> 57 58 #include <dev/scsipi/scsi_all.h> 59 #include <dev/scsipi/scsipi_all.h> 60 #include <dev/scsipi/scsiconf.h> 61 #include <dev/scsipi/scsi_message.h> 62 63 #include <machine/bus.h> 64 #include <machine/vmparam.h> 65 66 #include <dev/ic/ncr53c9xreg.h> 67 #include <dev/ic/ncr53c9xvar.h> 68 69 #include <machine/cpu.h> 70 #include <machine/sid.h> 71 #include <machine/scb.h> 72 #include <machine/vsbus.h> 73 #include <machine/clock.h> /* for SCSI ctlr ID# XXX */ 74 75 struct asc_vsbus_softc { 76 struct ncr53c9x_softc sc_ncr53c9x; /* Must be first */ 77 struct evcnt sc_intrcnt; /* count interrupts */ 78 bus_space_tag_t sc_bst; /* bus space tag */ 79 bus_space_handle_t sc_bsh; /* bus space handle */ 80 bus_space_handle_t sc_dirh; /* scsi direction handle */ 81 bus_space_handle_t sc_adrh; /* scsi address handle */ 82 bus_space_handle_t sc_ncrh; /* ncr bus space handle */ 83 bus_dma_tag_t sc_dmat; /* bus dma tag */ 84 bus_dmamap_t sc_dmamap; 85 caddr_t *sc_dmaaddr; 86 size_t *sc_dmalen; 87 size_t sc_dmasize; 88 unsigned int sc_flags; 89 #define ASC_FROMMEMORY 0x0001 /* Must be 1 */ 90 #define ASC_DMAACTIVE 0x0002 91 #define ASC_MAPLOADED 0x0004 92 unsigned long sc_xfers; 93 }; 94 95 #define ASC_REG_KA46_ADR 0x0000 96 #define ASC_REG_KA46_DIR 0x000C 97 #define ASC_REG_KA49_ADR 0x0000 98 #define ASC_REG_KA49_DIR 0x0004 99 #define ASC_REG_NCR 0x0080 100 #define ASC_REG_END 0x00B0 101 102 #define ASC_MAXXFERSIZE 65536 103 #define ASC_FREQUENCY 25000000 104 105 static int asc_vsbus_match __P((struct device *, struct cfdata *, void *)); 106 static void asc_vsbus_attach __P((struct device *, struct device *, void *)); 107 108 struct cfattach asc_vsbus_ca = { 109 sizeof(struct asc_vsbus_softc), asc_vsbus_match, asc_vsbus_attach 110 }; 111 112 static struct scsipi_device asc_vsbus_dev = { 113 NULL, /* Use the default error handler */ 114 NULL, /* have a queue, served by this */ 115 NULL, /* have no async handler */ 116 NULL, /* use the default done handler */ 117 }; 118 119 /* 120 * Functions and the switch for the MI code 121 */ 122 static u_char asc_vsbus_read_reg __P((struct ncr53c9x_softc *, int)); 123 static void asc_vsbus_write_reg __P((struct ncr53c9x_softc *, int, u_char)); 124 static int asc_vsbus_dma_isintr __P((struct ncr53c9x_softc *)); 125 static void asc_vsbus_dma_reset __P((struct ncr53c9x_softc *)); 126 static int asc_vsbus_dma_intr __P((struct ncr53c9x_softc *)); 127 static int asc_vsbus_dma_setup __P((struct ncr53c9x_softc *, caddr_t *, 128 size_t *, int, size_t *)); 129 static void asc_vsbus_dma_go __P((struct ncr53c9x_softc *)); 130 static void asc_vsbus_dma_stop __P((struct ncr53c9x_softc *)); 131 static int asc_vsbus_dma_isactive __P((struct ncr53c9x_softc *)); 132 133 static struct ncr53c9x_glue asc_vsbus_glue = { 134 asc_vsbus_read_reg, 135 asc_vsbus_write_reg, 136 asc_vsbus_dma_isintr, 137 asc_vsbus_dma_reset, 138 asc_vsbus_dma_intr, 139 asc_vsbus_dma_setup, 140 asc_vsbus_dma_go, 141 asc_vsbus_dma_stop, 142 asc_vsbus_dma_isactive, 143 NULL, 144 }; 145 146 static u_int8_t asc_attached; /* can't have more than one asc */ 147 148 static int 149 asc_vsbus_match( struct device *parent, struct cfdata *cf, void *aux) 150 { 151 struct vsbus_attach_args *va = aux; 152 volatile u_int8_t *ncr_regs; 153 int dummy; 154 155 if (asc_attached) 156 return 0; 157 158 if (vax_boardtype == VAX_BTYP_46 || vax_boardtype == VAX_BTYP_48) { 159 if (cf->cf_loc[0] != 0x200c0080) 160 return 0; 161 #if 0 162 } else if (vax_boardtype == VAX_BTYP_49) { 163 if (cf->cf_loc[0] != 0x26000080) 164 return 0; 165 #endif 166 } else { 167 return 0; 168 } 169 170 ncr_regs = (volatile u_int8_t *) va->va_addr; 171 172 /* *** need to generate an interrupt here 173 * From trial and error, I've determined that an INT is generated 174 * only when the following sequence of events occurs: 175 * 1) The interrupt status register (0x05) must be read. 176 * 2) SCSI bus reset interrupt must be enabled 177 * 3) SCSI bus reset command must be sent 178 * 4) NOP command must be sent 179 */ 180 181 dummy = ncr_regs[NCR_INTR << 2] & 0xFF; 182 ncr_regs[NCR_CFG1 << 2] = 0x06; /* we're ID 6, turn on INT for SCSI reset */ 183 ncr_regs[NCR_CMD << 2] = NCRCMD_RSTSCSI; /* send the reset */ 184 ncr_regs[NCR_CMD << 2] = NCRCMD_NOP; /* send a NOP */ 185 DELAY(10000); 186 187 dummy = ncr_regs[NCR_INTR << 2] & 0xFF; 188 return (dummy & NCRINTR_SBR) != 0; 189 } 190 191 192 /* 193 * Attach this instance, and then all the sub-devices 194 */ 195 static void 196 asc_vsbus_attach(struct device *parent, struct device *self, void *aux) 197 { 198 struct vsbus_attach_args *va = aux; 199 struct asc_vsbus_softc *asc = (void *)self; 200 struct ncr53c9x_softc *sc = &asc->sc_ncr53c9x; 201 int error; 202 203 asc_attached = 1; 204 /* 205 * Set up glue for MI code early; we use some of it here. 206 */ 207 sc->sc_glue = &asc_vsbus_glue; 208 209 asc->sc_bst = va->va_iot; 210 asc->sc_dmat = va->va_dmat; 211 212 error = bus_space_map(asc->sc_bst, va->va_paddr - ASC_REG_NCR, 213 ASC_REG_END, 0, &asc->sc_bsh); 214 if (error) { 215 printf(": failed to map registers: error=%d\n", error); 216 return; 217 } 218 error = bus_space_subregion(asc->sc_bst, asc->sc_bsh, ASC_REG_NCR, 219 ASC_REG_END - ASC_REG_NCR, &asc->sc_ncrh); 220 if (error) { 221 printf(": failed to map ncr registers: error=%d\n", error); 222 return; 223 } 224 if (vax_boardtype == VAX_BTYP_46 || vax_boardtype == VAX_BTYP_48) { 225 error = bus_space_subregion(asc->sc_bst, asc->sc_bsh, 226 ASC_REG_KA46_ADR, sizeof(u_int32_t), &asc->sc_adrh); 227 if (error) { 228 printf(": failed to map adr register: error=%d\n", 229 error); 230 return; 231 } 232 error = bus_space_subregion(asc->sc_bst, asc->sc_bsh, 233 ASC_REG_KA46_DIR, sizeof(u_int32_t), &asc->sc_dirh); 234 if (error) { 235 printf(": failed to map dir register: error=%d\n", 236 error); 237 return; 238 } 239 } else { 240 /* This is a gross and disgusting kludge but it'll 241 * save a bunch of ugly code. Unlike the VS4000/60, 242 * the SCSI Address and direction registers are not 243 * near the SCSI NCR registers and are inside the 244 * block of general VAXstation registers. So we grab 245 * them from there and knowing the internals of the 246 * bus_space implementation, we cast to bus_space_handles. 247 */ 248 struct vsbus_softc *vsc = (struct vsbus_softc *) parent; 249 asc->sc_adrh = (bus_space_handle_t) (vsc->sc_vsregs + ASC_REG_KA49_ADR); 250 asc->sc_dirh = (bus_space_handle_t) (vsc->sc_vsregs + ASC_REG_KA49_DIR); 251 #if 0 252 printf("\n%s: adrh=0x%08lx dirh=0x%08lx", self->dv_xname, 253 asc->sc_adrh, asc->sc_dirh); 254 ncr53c9x_debug = NCR_SHOWDMA|NCR_SHOWINTS|NCR_SHOWCMDS|NCR_SHOWPHASE|NCR_SHOWSTART|NCR_SHOWMSGS; 255 #endif 256 } 257 error = bus_dmamap_create(asc->sc_dmat, ASC_MAXXFERSIZE, 1, 258 ASC_MAXXFERSIZE, 0, BUS_DMA_NOWAIT, &asc->sc_dmamap); 259 260 switch (vax_boardtype) { 261 #if defined(VAX46) 262 case VAX_BTYP_46: 263 sc->sc_id = (clk_page[0xbc/2] >> clk_tweak) & 7; 264 break; 265 #endif 266 default: 267 sc->sc_id = 6; /* XXX need to get this from VMB */ 268 break; 269 } 270 271 sc->sc_freq = ASC_FREQUENCY; 272 273 /* gimme Mhz */ 274 sc->sc_freq /= 1000000; 275 276 scb_vecalloc(va->va_cvec, (void (*)(void *)) ncr53c9x_intr, 277 &asc->sc_ncr53c9x, SCB_ISTACK, &asc->sc_intrcnt); 278 evcnt_attach_dynamic(&asc->sc_intrcnt, EVCNT_TYPE_INTR, NULL, 279 self->dv_xname, "intr"); 280 281 /* 282 * XXX More of this should be in ncr53c9x_attach(), but 283 * XXX should we really poke around the chip that much in 284 * XXX the MI code? Think about this more... 285 */ 286 287 /* 288 * Set up static configuration info. 289 */ 290 sc->sc_cfg1 = sc->sc_id | NCRCFG1_PARENB; 291 sc->sc_cfg2 = NCRCFG2_SCSI2; 292 sc->sc_cfg3 = 0; 293 sc->sc_rev = NCR_VARIANT_NCR53C94; 294 295 /* 296 * XXX minsync and maxxfer _should_ be set up in MI code, 297 * XXX but it appears to have some dependency on what sort 298 * XXX of DMA we're hooked up to, etc. 299 */ 300 301 /* 302 * This is the value used to start sync negotiations 303 * Note that the NCR register "SYNCTP" is programmed 304 * in "clocks per byte", and has a minimum value of 4. 305 * The SCSI period used in negotiation is one-fourth 306 * of the time (in nanoseconds) needed to transfer one byte. 307 * Since the chip's clock is given in MHz, we have the following 308 * formula: 4 * period = (1000 / freq) * 4 309 */ 310 sc->sc_minsync = (1000 / sc->sc_freq); 311 sc->sc_maxxfer = 63 * 1024; 312 313 printf("\n%s", self->dv_xname); /* Pretty print */ 314 315 /* Do the common parts of attachment. */ 316 sc->sc_adapter.scsipi_cmd = ncr53c9x_scsi_cmd; 317 sc->sc_adapter.scsipi_minphys = minphys; 318 ncr53c9x_attach(sc, &asc_vsbus_dev); 319 } 320 321 /* 322 * Glue functions. 323 */ 324 325 static u_char 326 asc_vsbus_read_reg(struct ncr53c9x_softc *sc, int reg) 327 { 328 struct asc_vsbus_softc *asc = (struct asc_vsbus_softc *)sc; 329 330 return bus_space_read_1(asc->sc_bst, asc->sc_ncrh, 331 reg * sizeof(u_int32_t)); 332 } 333 334 static void 335 asc_vsbus_write_reg(sc, reg, val) 336 struct ncr53c9x_softc *sc; 337 int reg; 338 u_char val; 339 { 340 struct asc_vsbus_softc *asc = (struct asc_vsbus_softc *)sc; 341 342 bus_space_write_1(asc->sc_bst, asc->sc_ncrh, 343 reg * sizeof(u_int32_t), val); 344 } 345 346 static int 347 asc_vsbus_dma_isintr(sc) 348 struct ncr53c9x_softc *sc; 349 { 350 struct asc_vsbus_softc *asc = (struct asc_vsbus_softc *)sc; 351 return bus_space_read_1(asc->sc_bst, asc->sc_ncrh, 352 NCR_STAT * sizeof(u_int32_t)) & NCRSTAT_INT; 353 } 354 355 static void 356 asc_vsbus_dma_reset(sc) 357 struct ncr53c9x_softc *sc; 358 { 359 struct asc_vsbus_softc *asc = (struct asc_vsbus_softc *)sc; 360 361 if (asc->sc_flags & ASC_MAPLOADED) 362 bus_dmamap_unload(asc->sc_dmat, asc->sc_dmamap); 363 asc->sc_flags &= ~(ASC_DMAACTIVE|ASC_MAPLOADED); 364 } 365 366 static int 367 asc_vsbus_dma_intr(sc) 368 struct ncr53c9x_softc *sc; 369 { 370 struct asc_vsbus_softc *asc = (struct asc_vsbus_softc *)sc; 371 u_int tcl, tcm; 372 int trans, resid; 373 374 if ((asc->sc_flags & ASC_DMAACTIVE) == 0) 375 panic("asc_vsbus_dma_intr: DMA wasn't active"); 376 377 asc->sc_flags &= ~ASC_DMAACTIVE; 378 379 if (asc->sc_dmasize == 0) { 380 /* A "Transfer Pad" operation completed */ 381 tcl = NCR_READ_REG(sc, NCR_TCL); 382 tcm = NCR_READ_REG(sc, NCR_TCM); 383 NCR_DMA(("asc_vsbus_intr: discarded %d bytes (tcl=%d, tcm=%d)\n", 384 tcl | (tcm << 8), tcl, tcm)); 385 return 0; 386 } 387 388 resid = 0; 389 if ((resid = (NCR_READ_REG(sc, NCR_FFLAG) & NCRFIFO_FF)) != 0) { 390 NCR_DMA(("asc_vsbus_intr: empty FIFO of %d ", resid)); 391 DELAY(1); 392 } 393 if (asc->sc_flags & ASC_MAPLOADED) { 394 bus_dmamap_sync(asc->sc_dmat, asc->sc_dmamap, 395 0, asc->sc_dmasize, 396 asc->sc_flags & ASC_FROMMEMORY 397 ? BUS_DMASYNC_POSTWRITE 398 : BUS_DMASYNC_POSTREAD); 399 bus_dmamap_unload(asc->sc_dmat, asc->sc_dmamap); 400 } 401 asc->sc_flags &= ~ASC_MAPLOADED; 402 403 resid += (tcl = NCR_READ_REG(sc, NCR_TCL)); 404 resid += (tcm = NCR_READ_REG(sc, NCR_TCM)) << 8; 405 406 trans = asc->sc_dmasize - resid; 407 if (trans < 0) { /* transferred < 0 ? */ 408 printf("asc_vsbus_intr: xfer (%d) > req (%d)\n", 409 trans, asc->sc_dmasize); 410 trans = asc->sc_dmasize; 411 } 412 NCR_DMA(("asc_vsbus_intr: tcl=%d, tcm=%d; trans=%d, resid=%d\n", 413 tcl, tcm, trans, resid)); 414 415 *asc->sc_dmalen -= trans; 416 *asc->sc_dmaaddr += trans; 417 418 asc->sc_xfers++; 419 return 0; 420 } 421 422 static int 423 asc_vsbus_dma_setup(struct ncr53c9x_softc *sc, caddr_t *addr, size_t *len, 424 int datain, size_t *dmasize) 425 { 426 struct asc_vsbus_softc *asc = (struct asc_vsbus_softc *)sc; 427 428 asc->sc_dmaaddr = addr; 429 asc->sc_dmalen = len; 430 if (datain) { 431 asc->sc_flags &= ~ASC_FROMMEMORY; 432 } else { 433 asc->sc_flags |= ASC_FROMMEMORY; 434 } 435 if ((vaddr_t) *asc->sc_dmaaddr < VM_MIN_KERNEL_ADDRESS) 436 panic("asc_vsbus_dma_setup: dma address (%p) outside of kernel", 437 *asc->sc_dmaaddr); 438 439 NCR_DMA(("%s: start %d@%p,%d\n", sc->sc_dev.dv_xname, 440 (int)*asc->sc_dmalen, *asc->sc_dmaaddr, (asc->sc_flags & ASC_FROMMEMORY))); 441 *dmasize = asc->sc_dmasize = min(*dmasize, ASC_MAXXFERSIZE); 442 443 if (asc->sc_dmasize) { 444 if (bus_dmamap_load(asc->sc_dmat, asc->sc_dmamap, 445 *asc->sc_dmaaddr, asc->sc_dmasize, 446 NULL /* kernel address */, 447 BUS_DMA_NOWAIT|VAX_BUS_DMA_SPILLPAGE)) 448 panic("%s: cannot load dma map", sc->sc_dev.dv_xname); 449 bus_dmamap_sync(asc->sc_dmat, asc->sc_dmamap, 450 0, asc->sc_dmasize, 451 asc->sc_flags & ASC_FROMMEMORY 452 ? BUS_DMASYNC_PREWRITE 453 : BUS_DMASYNC_PREREAD); 454 bus_space_write_4(asc->sc_bst, asc->sc_adrh, 0, 455 asc->sc_dmamap->dm_segs[0].ds_addr); 456 bus_space_write_4(asc->sc_bst, asc->sc_dirh, 0, 457 asc->sc_flags & ASC_FROMMEMORY); 458 NCR_DMA(("%s: dma-load %lu@0x%08lx\n", sc->sc_dev.dv_xname, 459 asc->sc_dmamap->dm_segs[0].ds_len, 460 asc->sc_dmamap->dm_segs[0].ds_addr)); 461 asc->sc_flags |= ASC_MAPLOADED; 462 } 463 464 return 0; 465 } 466 467 static void 468 asc_vsbus_dma_go(struct ncr53c9x_softc *sc) 469 { 470 struct asc_vsbus_softc *asc = (struct asc_vsbus_softc *)sc; 471 472 asc->sc_flags |= ASC_DMAACTIVE; 473 } 474 475 static void 476 asc_vsbus_dma_stop(struct ncr53c9x_softc *sc) 477 { 478 struct asc_vsbus_softc *asc = (struct asc_vsbus_softc *)sc; 479 480 if (asc->sc_flags & ASC_MAPLOADED) { 481 bus_dmamap_sync(asc->sc_dmat, asc->sc_dmamap, 482 0, asc->sc_dmasize, 483 asc->sc_flags & ASC_FROMMEMORY 484 ? BUS_DMASYNC_POSTWRITE 485 : BUS_DMASYNC_POSTREAD); 486 bus_dmamap_unload(asc->sc_dmat, asc->sc_dmamap); 487 } 488 489 asc->sc_flags &= ~(ASC_DMAACTIVE|ASC_MAPLOADED); 490 } 491 492 static int 493 asc_vsbus_dma_isactive(struct ncr53c9x_softc *sc) 494 { 495 struct asc_vsbus_softc *asc = (struct asc_vsbus_softc *)sc; 496 497 return (asc->sc_flags & ASC_DMAACTIVE) != 0; 498 } 499
Indexes created Wed Oct 01 07:09:59 GMT 2025